KR20050067008A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR20050067008A KR20050067008A KR1020040107867A KR20040107867A KR20050067008A KR 20050067008 A KR20050067008 A KR 20050067008A KR 1020040107867 A KR1020040107867 A KR 1020040107867A KR 20040107867 A KR20040107867 A KR 20040107867A KR 20050067008 A KR20050067008 A KR 20050067008A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 46
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 238000002955 isolation Methods 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 239000007772 electrode material Substances 0.000 claims description 2
- 238000009832 plasma treatment Methods 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 abstract description 19
- 239000002184 metal Substances 0.000 abstract description 19
- 239000010410 layer Substances 0.000 description 46
- 238000005516 engineering process Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28255—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
본 발명은 반도체 소자의 제조방법에 관한 것으로, 스트레인드 실리콘 채널층과 도핑된 SiGe층이 적층되어 형성된 SOI 기판을 이용하여 SiGe와 스트레인드 실리콘 간의 높은 식각선택비를 이용하여 상대적으로 용이하게 완전공핍평 채널소자를 제조할 수 있을 뿐만 아니라, 접합저항과 용량의 감소를 비교적 단순한 공정으로 가능하게 하는 소오스/드레인 공정과, 고성능 소자에 필수적인 금속 게이트의 적용과 게이트 폭의 축소가 용이한 반도체 소자의 제조 방법을 제공한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a semiconductor device, wherein a SOI substrate formed by stacking a strained silicon channel layer and a doped SiGe layer is relatively easily completed using a high etching selectivity between SiGe and strained silicon. In addition to fabricating a pip channel device, a source / drain process that allows a reduction in junction resistance and capacity in a relatively simple process, and the application of a metal gate essential to a high performance device and an easy reduction of the gate width of a semiconductor device It provides a manufacturing method.
Description
본 발명은 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device.
종래의 실리콘 반도체 소자들은 무어의 법칙에 따라 가격은 유지된 채로 매 18개월마다 집적도를 약 2배로 증가시켜서 경쟁력을 유지하기 위한 노력을 계속하고 있다. 즉 집적도를 증가시키기 위해서 단위 트랜지스터의 크기를 줄이는 노력이 계속되어 오고 있는 것이다.Conventional silicon semiconductor devices continue to strive to remain competitive by doubling the density every 18 months with the price maintained in accordance with Moore's Law. In other words, efforts have been made to reduce the size of unit transistors in order to increase the degree of integration.
이러한 소자의 스케일링은 소자의 크기가 나노미터급으로 줄어듦에 따라 새로운 많은 도전에 직면하여 혁신적인 기술이 많이 요구되고 있다. 또한 소자의 응용 범위도 기존의 소자들은 고속 동작과 고집적을 통한 매우 다양한 기능을 개별적으로 수행하는 기능 단위 규모에서 다양한 기능의 소자를 활용한 시스템 규모의 기능 수행을 위한 고집적도, 초고속 특성, 휴대용 전자기기를 위한 초저전력 특성이 요구되고 있으며, 초고주파 응용을 위한 연구도 활발히 진행되고 있는 실정이다.Scaling of these devices is faced with many new challenges as the size of the device is reduced to nanometers, requiring a number of innovative technologies. In addition, the application range of the existing devices, the high-density, high-speed characteristics, portable electronics for the performance of the system-scale function using the device of various functions from the functional unit scale to perform a variety of functions individually through high-speed operation and high integration Ultra low power characteristics are required for devices, and research for ultra high frequency applications is being actively conducted.
이러한 많은 새로운 도전을 위하여 해결하여야 하는 기술적 과제로는 누설전류의 저감, 단채널 현상 억제, 동작 속도 개선, 고주파 특성 개선, 광대역 특성, 신뢰성 개선, 생산성 및 경제성의 확보 등이 있다. Technical challenges to be solved for many of these new challenges include reducing leakage current, suppressing short channel phenomenon, improving operation speed, improving high frequency characteristics, broadband characteristics, improving reliability, and securing productivity and economy.
이를 위해서는 게이트 터널링 억제를 위한 고유전율 게이트 절연막의 도입, 단채널 현상 억제 및 동작 속도의 개선을 위한 공핍형 채널구조의 도입, 저항과 접합용량 감소를 위한 상승형 소스/드레인 구조, 금속게이트 전극의 도입, 고주파손실 억제를 위한 SOI 기판 재료의 도입, 초고속 동작을 위하여 전자의 이동도 특성이 매우 좋은 스트레인드 실리콘채널의 도입 등이 시도되고 있다. 그러나, 아직까지 만족할 만한 성과는 나오지 못하고 있는 실정이다.To this end, a high dielectric constant gate insulating film is introduced for gate tunneling suppression, a depletion channel structure is introduced for suppressing short-channel phenomenon and operation speed is increased, a rising source / drain structure for reducing resistance and junction capacitance, and a metal gate electrode are introduced. The introduction of SOI substrate material for suppressing high frequency loss and the introduction of a strained silicon channel having very good electron mobility for ultra-fast operation are being attempted. However, there is no satisfactory result yet.
본 발명은 상술한 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 목적은 접합저항과 용량의 감소를 위한 간단한 상승형 소스/드레인 제작 방법 및 특히 고성능 소자에 필수적인 금속 게이트의 적용과 게이트 폭의 축소가 용이한 구조의 반도체 소자의 제조방법을 제공하는 것이다. SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a simple method of fabricating a rising source / drain for reducing junction resistance and capacitance, and to reduce the gate width and the application of metal gates, which are essential for high-performance devices. It is to provide a method for manufacturing a semiconductor device having an easy structure.
본 발명의 다른 목적은 울트라 샬로우 접합(ultra shallow junction), 상승형 소오스/드레인(raised source/drain)등의 공정이 따로 필요 없이 해결가능하고, 금속게이트 전극 형성 등이 용이하며, 초미세 게이트 전극 형성이 리소그라피(lithography)기술에 의존하기 않는 구조을 개발함으로써, 생산비용의 절감과, 높은 생산성 뿐 만아니라, 고성능 특성 등을 동시에 얻을 수 있는 소자기술을 제공하는 것이다. Another object of the present invention can be solved without the need for an ultra shallow junction, a raised source / drain, etc., easy to form a metal gate electrode, and an ultra-fine gate electrode By developing a structure in which formation does not depend on lithography technology, it is to provide a device technology capable of simultaneously reducing production costs and high productivity as well as high performance characteristics.
본 발명의 또 다른 목적은 SiGe와 스트레인드 실리콘 간의 높은 식각선택비를 이용하여, 완전 공핍형 나노급 반도체 소자 제작에 있어서 채널 두께 균일도를 개선하고, 완전공핍형 초박막 채널을 제작할 수 있는 기술적 해결 방법을 제공하는 것이다. It is another object of the present invention to improve the channel thickness uniformity in fabricating a fully depleted nanoscale semiconductor device by using a high etching selectivity between SiGe and strained silicon, and to provide a technical solution capable of fabricating a fully depleted ultra thin channel. To provide.
본 발명의 또 다른 목적은 게이트 정의를 위한 리소그라피 공정시 CD(Critical Dimension)의 2 내지 3배 정도의 여유도를 가질 수 있기 때문에 현재의 광학 노광 기술의 활용이 가능하여 지므로 제작 공정이 단순화되어 경제성이 있는 양산 기술을 제공하는 것이다. Another object of the present invention is to have a margin of about 2 to 3 times the CD (Critical Dimension) in the lithography process for the gate definition, it is possible to utilize the current optical exposure technology, so the manufacturing process is simplified and economical This is to provide mass production technology.
상술한 문제점을 해결하기 위한 기술적 수단으로서, 본 발명의 일측면은 상부에, 스트레인드 실리콘 채널층과 도핑된 SiGe층이 형성된 SOI기판이 제공되는 단계와, 도핑된 SiGe층 상부에 제1 산화막과 실리콘 질화막을 형성하는 단계와, 실리콘 질화막 상부에 감광막을 도포하고 소자 분리 영역을 정의하기 위해 상기 실리콘 질화막, 상기 제1 산화막, 상기 도핑된 SiGe층 및 상기 스트레인드 실리콘 채널층을 식각하고, 소자 분리막을 형성하는 단계와, 전체 구조 상에 감광막을 도포하고 패터닝하여 게이트 형성 영역을 정의하는 단계와, 감광막을 마스크로 하여 상기 실리콘 질화막과 제1 산화막을 식각한 다음, 상기 도핑된 SiGe층을 선택 식각하는 단계와, 전체 구조 상에 패드 산화막을 형성하고, 열처리를 실시하여 소스/드레인 영역에 불순물이 주입되도록 하는 단계와, 채널 영역에 형성된 패드 산화막을 제거한 다음, 게이트 절연막을 형성하고, 게이트 전극용 재료를 증착 및 패터닝하여 게이트 전극을 형성하는 단계를 포함하는 반도체 소자의 제조방법을 제공한다.As a technical means for solving the above-described problems, one side of the present invention is a step of providing an SOI substrate having a strained silicon channel layer and a doped SiGe layer on the top, and a first oxide film on the doped SiGe layer and Etching the silicon nitride film, the first oxide film, the doped SiGe layer and the strained silicon channel layer to form a silicon nitride film, apply a photoresist film over the silicon nitride film, and define a device isolation region; Forming a gate; forming a gate forming region by applying and patterning a photoresist on the entire structure; etching the silicon nitride layer and the first oxide layer using the photoresist as a mask, and then selectively etching the doped SiGe layer And forming a pad oxide film on the entire structure and performing heat treatment to inject impurities into the source / drain regions. Removing the pad oxide film formed on the step, and a channel forming region and then the gate insulating film, and provides a method for manufacturing a semiconductor device comprising forming a gate electrode by depositing and patterning the gate electrode materials.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 제시되는 실시 예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 단지 본 실시예는 발명의 개시가 완전하도록 하며 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다. 한편, 도면상에서 동일 부호는 동일한 요소를 지칭하며, 중복되는 요소에 대해서는 설명을 생략하기로 한다. Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you. In the drawings, the same reference numerals refer to the same elements, and descriptions of overlapping elements will be omitted.
도 1 내지 도 13a, 13b는 본 발명의 일실시예에 따른 반도체 소자의 제조방법의 흐름도들이다.1 to 13A and 13B are flowcharts illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
도 1을 참조하면, 먼저 SOI 기판이 제공된다. SOI 기판 상부에는 스트레인드 실리콘 채널층(120)과 도핑된 SiGe층(110)이 형성되어 있다. 즉, SOI 기판은 예컨대 실리콘 웨이퍼(미도시) 상에, BOX(Buried oxide; 210)위에 예를 들어 두께 10 내지 200nm, 막 두께의 균일성 1 내지 2%(1 내지 4nm) 이하의 스트레인드 실리콘 채널층(120)이 형성되어 있고, 그 상부에 예를 들어 100 내지 1000nm, 막두께 균일성 약 3% (3 내지 30nm)이하의 도핑된 SiGe층(110)이 형성되어 있다. 1, an SOI substrate is first provided. A strained silicon channel layer 120 and a doped SiGe layer 110 are formed on the SOI substrate. That is, the SOI substrate is, for example, on a silicon wafer (not shown), for example, strained silicon having a thickness of 10 to 200 nm on the BOX (Buried oxide; 210) and a uniformity of 1 to 2% (1 to 4 nm) of film thickness or less. A channel layer 120 is formed, and a doped SiGe layer 110 having a thickness uniformity of about 3% (3 to 30 nm) or less, for example, 100 to 1000 nm is formed thereon.
상술한 SOI 기판은 스마트-커트(smart-cut)을 이용하는 Unibond 방법을 사용하여 제작할 수 있고, 특별히 고안된 다른 방법을 사용할 수도 있다. 예를 들어, 동출원인에 의한 한국출원번호 제2004-15070호에 개시된 방법을 이용할 수도 있다. 다음으로, 상기 도핑된 SiGe층(110) 상부에 제1 산화막(140)을 형성한다. 또한, 선택적으로는 도핑된 SiGe층(110)과 제1 산화막(140) 사이에 추가로 질화막을 얇게 증착할 수도 있다. The above-described SOI substrate can be manufactured using the Unibond method using smart-cut, and other specially designed methods can also be used. For example, the method disclosed in Korean Application No. 2004-15070 by the same applicant may be used. Next, a first oxide layer 140 is formed on the doped SiGe layer 110. In addition, a nitride film may be further deposited thinly between the doped SiGe layer 110 and the first oxide film 140.
제1 산화막(140)은 패드 산화막 또는 CVD공정을 이용하여 저온 산화막으로 형성할 수 있다. 바람직하게는, 응력이나 결함을 유발하지 않는 두께로 약 5 내지 50nm 두께의 제1 산화막(140)을 형성한 다음 제1 산화막(140) 상부에 실리콘 질화막(150)을 형성한다. 실리콘 질화막(150)은 STI(Shallow Trench Isolation) 형성에 필요한 CMP 배리어층으로 약 10 내지 300 nm 형성할 수 있다. 계속해서 전체 구조 상부에 감광막을 도포하고 패터닝하여 활성영역을 정의하기 위한 감광막 패턴(300)을 형성한다. The first oxide film 140 may be formed of a low temperature oxide film using a pad oxide film or a CVD process. Preferably, the first oxide film 140 having a thickness of about 5 to 50 nm is formed to a thickness that does not cause stress or defects, and then the silicon nitride film 150 is formed on the first oxide film 140. The silicon nitride film 150 may be formed of about 10 to 300 nm as a CMP barrier layer required for forming shallow trench isolation (STI). Subsequently, a photoresist film is coated and patterned on the entire structure to form a photoresist pattern 300 for defining an active region.
도 2를 참조하면, 패터닝된 감광막(300)을 마스크로 건식 식각을 실시하여 소자 분리 영역의 실리콘 질화막(150), 제1 산화막(140), 도핑된 SiGe층(110) 및 스트레인드 실리콘 채널층(120)층을 모두 식각한다. Referring to FIG. 2, dry etching is performed on the patterned photoresist layer 300 using a mask to form a silicon nitride layer 150, a first oxide layer 140, a doped SiGe layer 110, and a strained silicon channel layer in an isolation region. All 120 layers are etched.
도 3 밑 도 4를 참조하면, STI 공정을 실시하여 소자 분리막(310)을 형성하고, 그 후, 감광막 패턴(315)을 형성하고 사진석판 공정을 이용하여 게이트 형성 영역을 정의한다. 이때 감광막 패턴(315)의 해상도는 임계 해상도에 비해 약 1.5배에서 3배 정도 크게 형성할 수 있기 때문에 소자 형성을 위한 사진석판 공정은 기존의 ArF급 노광장비로도 가능하다. 계속해서, 감광막 패턴(315)을 식각 마스크로 사용하여 실리콘 질화막(150)과 제1 산화막(140)을 식각한 다음, 도핑된 SiGe층(110)을 선택적으로 식각하고 완료되면 식각을 종료하고 감광막 패턴(310)을 제거한 후, 채널표면의 손상층을 회복시키기 위한 세정과 산화공정을 실시한다. 이 경우, 채널표면의 거칠기와 손상층을 회복시키기 위하여, 세정과 리모트 수소 플라즈마 처리나, 수소 열처리, 또는 산화열처리 등을 실시하여 스트레인드 실리콘 채널층(120)의 표면을 세정한다. Referring to FIG. 3 and FIG. 4, the device isolation layer 310 is formed by performing an STI process, thereafter, a photoresist pattern 315 is formed, and a gate formation region is defined using a photolithography process. In this case, since the resolution of the photoresist pattern 315 may be about 1.5 to 3 times larger than the critical resolution, the photolithography process for forming the device may be performed using conventional ArF class exposure equipment. Subsequently, the silicon nitride film 150 and the first oxide film 140 are etched using the photoresist pattern 315 as an etch mask, and then the doped SiGe layer 110 is selectively etched and the etching is completed when the photoresist film is finished. After the pattern 310 is removed, cleaning and oxidation processes are performed to recover the damaged layer on the channel surface. In this case, in order to recover the roughness and damage layer of the channel surface, the surface of the strained silicon channel layer 120 is cleaned by performing cleaning and remote hydrogen plasma treatment, hydrogen heat treatment, or oxidation heat treatment.
도 5를 참조하면, 상기 전체 구조 상에 패드 산화막(320)을 1 내지 10nm 가량 증착하거나 성장시킨 다음 급속 열처리를 실시하여 소스/드레인 영역(120a, 120b)의 불순물이 주입되지 않은 영역과 LDD 영역에 불순물이 확산되도록 한다. 이 때 채널영역(120b)으로 불순물이 확산되지 않도록 공정조건을 확립한다. 계속해서 실리콘 질화막을 1 내지 100nm 가량 형성한 다음 실리콘 질화막의 스페이서(330)를 형성한다.Referring to FIG. 5, the pad oxide layer 320 is deposited or grown on the entire structure by about 1 to 10 nm, and then rapid heat treatment is performed to inject impurities into the source / drain regions 120a and 120b and the LDD region. Allow impurities to diffuse in. At this time, the process conditions are established so that impurities do not diffuse into the channel region 120b. Subsequently, the silicon nitride film is formed to about 1 to 100 nm, and then the spacer 330 of the silicon nitride film is formed.
도 6을 참조하면, 노출된 채널 영역에 형성된 패드 산화막(320)을 제거한 다음, 게이트 절연막(340)을 형성하고, 계속해서 게이트 전극용 도선재료를 형성한다. 이때 게이트 절연막(340)은 NO(Nitride/silicon Dioxide) 또는 NO + High-k 유전체의 복합 구조 또는 High-k 유전체 단독막일 수 있으며, 게이트 전극(350)은 불순물이 주입된 폴리실리콘 또는 polycide 또는 금속 적층막일 수 있다.Referring to FIG. 6, after the pad oxide layer 320 formed in the exposed channel region is removed, a gate insulating layer 340 is formed, and then a conductive material for a gate electrode is formed. In this case, the gate insulating layer 340 may be a composite structure of NO (Nitride / silicon Dioxide) or NO + High-k dielectric or a high-k dielectric single layer, and the gate electrode 350 may be polysilicon or polycide or metal implanted with impurities. It may be a laminated film.
도 7을 참조하면, CMP공정을 사용하여 High-k 적층 절연막 또는 NO 적층 절연막을 식각 장벽으로 사용하여 평탄화 공정을 실시한다. 이때 게이트 전극(350)과 절연막과의 식각선택비가 충분히 높은 조건에서 CMP 공정을 실시한 다음 세정공정을 실시한다.Referring to FIG. 7, a planarization process is performed using a high-k stacked insulating film or a NO stacked insulating film as an etch barrier using a CMP process. At this time, the CMP process is performed under the condition that the etching selectivity between the gate electrode 350 and the insulating film is sufficiently high, and then the cleaning process is performed.
도 8을 참조하면, 상기 전체 구조 상에 ILD(Inter Layer Dielectric)층(360)을 형성한다. 이때 ILD층(360)은 공정 조건에 따라 저유전율의 단일층 또는 다층 구조일 수 있다. Referring to FIG. 8, an interlayer dielectric (ILD) layer 360 is formed on the entire structure. In this case, the ILD layer 360 may be a single layer or multilayer structure having a low dielectric constant depending on process conditions.
도 9를 참조하면, 상기 구조상에 감광막(370)의 패턴 형성 공정을 사용하여 소스/드레인 및 게이트 영역에 컨택을 형성하기 위한 패턴을 형성한다. 이때 게이트 컨택패턴은 단면 모습에 포함되지 않았으나, 함께 정의된다.Referring to FIG. 9, a pattern for forming a contact in the source / drain and gate regions is formed on the structure by using a pattern forming process of the photoresist layer 370. In this case, the gate contact pattern is not included in the cross-sectional view, but is defined together.
도 10을 참조하면, 감광막(370)을 식각마스크로 사용하여 콘택홀을 형성한다. 이 과정을 좀 더 자세히 설명하면 다음과 같다. ILD층(360)을 먼저 식각한다. 이때 약간의 정렬오차는 고유전율막이 식각 장벽 역할을 하여 자동 정열특성을 확보할 수 있다. 계속해서 실리콘 질화막(150)과 제 2 산화막(140)을 식각한 모습을 나타낸다. 이때 좁은 면적에서 접촉 저항을 낮추기 위하여 소스/드레인(120a, 120b)의 모서리가 드러나도록 한다. Referring to FIG. 10, a contact hole is formed using the photoresist 370 as an etching mask. The process is explained in more detail as follows. The ILD layer 360 is first etched. In this case, a slight misalignment may be obtained by the high dielectric constant film acting as an etching barrier to ensure automatic alignment characteristics. Subsequently, the silicon nitride film 150 and the second oxide film 140 are etched. At this time, the edges of the sources / drains 120a and 120b are exposed to reduce the contact resistance in a narrow area.
도 11을 참조하면, 샐리사이드(self aligned silicide) 공정을 실시하되, Ti, Ta, Ni, Co 등의 금속들을 이용하여 샐리사이드층(380)을 형성한 다음, 제 2 산화막(140)에 있는 미반응물들을 제거한다. 이 때, 단차피복성이 좋은 ALD(Atomic Layer Deposition) 또는 CVD 공정을 사용하여 상술한 금속들을 증착하는 것이 바람직하다. 이 때 샐리사이드화 되는 영역은 소스/드레인 영역의 상부 뿐 아니라 SiGe층(110)의 측벽도 실리사이드 공정시 금속접촉에 활용된다. 샐리사이드 공정을 위한 접촉창 형성시, 접촉 면적을 최대화하기 위하여, 소스/드레인 영역의 수평면과 수직면이 모두 노출되도록 식각하는 것이 바람직하다.Referring to FIG. 11, a salicide (self aligned silicide) process is performed, and the salicide layer 380 is formed using metals such as Ti, Ta, Ni, and Co, and then the second oxide layer 140 is formed. Remove unreacted materials. At this time, it is preferable to deposit the above-mentioned metals using an ALD (Atomic Layer Deposition) or CVD process with good step coverage. In this case, the region to be salicided is utilized for metal contact during the silicide process, as well as the top of the source / drain regions, as well as the sidewalls of the SiGe layer 110. In forming the contact window for the salicide process, in order to maximize the contact area, it is preferable to etch such that both the horizontal and vertical surfaces of the source / drain regions are exposed.
도 12를 참조하면, 계속해서 ALD 또는 CVD 등의 고종횡비 패턴에서의 단차 피복성이 우수한 공정을 사용하여 금속층(390)을 형성한다. Referring to FIG. 12, the metal layer 390 is subsequently formed using a process having excellent step coverage in a high aspect ratio pattern such as ALD or CVD.
다음으로, 도 13a는 단층 금속 패턴 형성 후의 단면 모습을 나타내며, 경우에 따라서는 나노집적회로 공정시 감광막 패턴 형성 공정 여유도가 적거나, 고성능 고속 소자 특성을 위하여 난식각성 금속층을 사용할 경우에는 매립형 금속 도선 형성 공정을 사용할 수도 있다. 금속층(390)을 저저항과 고주파 특성이 좋은 Au/Ni/Ti 나 Au/Pt/Ti/Ni 등의 난식각성 다중 금속막을 사용할 경우에는 매립형 구조의 금속 배선 공정을 이용할 수도 있다(도 13b 참조). Next, FIG. 13A illustrates a cross-sectional view after forming a single layer metal pattern, and in some cases, a buried metal layer is used when the photoresist pattern forming process has little margin in the nano integrated circuit process, or when an etched metal layer is used for high performance high speed device characteristics A conducting wire formation process can also be used. When the metal layer 390 uses an etch-resistant multiple metal film such as Au / Ni / Ti or Au / Pt / Ti / Ni having good low resistance and high frequency characteristics, a metal wiring process having a buried structure may be used (see FIG. 13B). .
본 발명의 사상이나 범위로부터 이탈됨이 없이 본 발명의 다양한 변경이 가능해질 수 있다. 따라서, 본 발명에 따른 구현 예에 대한 상기의 설명은 예시의 목적으로만 제공될 것이며, 첨부된 청구 범위 및, 그것의 등가물에 의해서 한정되는 본 발명을 제한하기 위한 목적을 위해서 제공되는 것은 아니다. Various changes may be made in the present invention without departing from the spirit or scope of the invention. Accordingly, the foregoing description of embodiments in accordance with the present invention will be provided for purposes of illustration only, and not for the purpose of limiting the invention as defined by the appended claims and their equivalents.
본 발명의 효과는 다음과 같다.The effects of the present invention are as follows.
(1) 게이트 전극형성을 다마신 공정을 이용하여 수행하기에 용이하게 되어있기 때문에 고유전율 게이트적층 절연막과 금속게이트 전극의 적용에 매우 유리한 구조이다. 또한 게이트 전극의 형상이 역사다리꼴이기 때문에 전극저항을 줄이면서도 전극배선을 위한 접촉창 형성 공정이 상대적으로 유리하다.(1) Since the gate electrode formation is easy to be performed by the damascene process, the structure is very advantageous for the application of the high dielectric constant gate stacked insulating film and the metal gate electrode. In addition, since the gate electrode has an inverted trapezoidal shape, a contact window forming process for electrode wiring is relatively advantageous while reducing electrode resistance.
(2) 감광막을 이용하여 게이트 영역과 LDD 영역을 함께 정의함으로써 포토 리소그라피 공정을 단순화하여 생산비를 경감시키는 효과가 있다.(2) By defining the gate region and the LDD region together using the photoresist film, the photolithography process can be simplified to reduce the production cost.
(3) 스트레인드 채널 영역을 형성하기 위한 식각공정 시, SiGe층/실리콘층의 식각선택비가 매우 높고, 결함발생이 적은 건식식각공정과 SC1 습식식각공정을 사용하여 저결함, 고선택 식각으로 양질의 스트레인드 실리콘 채널을 확보할 수 있는 효과가 있다. (3) In the etching process for forming the strained channel region, the etching selectivity of the SiGe layer / silicon layer is very high, and the defects are high quality due to the low defect and the high selection etching using the dry etching process and the SC1 wet etching process with low defects. It is effective to secure a strained silicon channel.
(4) 활성영역을 형성한 후에, 별도의 STI공정을 이용한 소자분리막을 형성하지 않고, SOI기판 내의 베리드 옥사이드층과 측벽 질화막 스페이서를 이용하여 소자분리막을 형성가능함으로 공정의 단순함을 꾀할 수 있다.(4) After the active region is formed, the device isolation film can be formed using the buried oxide layer and the sidewall nitride film spacer in the SOI substrate without forming a device isolation film using a separate STI process, thereby simplifying the process. .
(5) CMP를 이용하여 전극을 형성하기 때문에 난식각성 금속재료의 사용이 가능한 구조이며, 게이트 영역을 정의할 때, 소자분리막 영역을 함께 정의 하여 게이트전극의 접촉창 형성부분의 매립 전극을 위한 영역이 확보되어 공정단계가 간단하고, 구현이 용이한 효과가 있다.(5) It is a structure that can use an etch-resistant metal material because the electrode is formed using CMP. When defining the gate region, the region for the buried electrode in the contact window forming part of the gate electrode is defined by defining the device isolation layer region together. This ensures a simple process step, there is an effect that is easy to implement.
(6) 소오스/드레인의 두께가 상대적으로 두껍기 때문에 상승형 소오스/드레인 공정이 필요 없으며, 다마신 게이트 공정에 유리하기 때문에 금속 게이트 적용이 용이하고, 게이트 스케빌리티(scalability)에 유리하다. (6) Since the thickness of the source / drain is relatively thick, an elevated source / drain process is not necessary. Since the damascene gate process is advantageous, the metal gate is easy to apply and the gate scalability is advantageous.
(7) 고성능 소자에 필수적인 금속 게이트의 적용과 게이트 폭의 축소가 용이한 구조의 소자제작 공정을 제공할 수 있는 효과가 있다. (7) There is an effect that can provide a device fabrication process having a structure in which the application of a metal gate, which is essential for a high-performance device, and the gate width can be easily reduced.
(8) 게이트 정의를 위한 리소그라피 공정시 CD(Critical Dimension)의 2 내지 3배 정도의 여유도를 가질 수 있기 때문에 현재의 광학 노광 기술의 활용이 가능하여 지므로 제작 공정이 단순화되어 경제성이 있는 양산 기술을 제공가능하게 된다. (8) In the lithography process to define the gate, it can have a margin of about 2 to 3 times the CD (Critical Dimension), which makes it possible to use the current optical exposure technology, so the manufacturing process is simplified and economical mass production technology. Can be provided.
(9) 금속 접촉창을 형성할 때, S/D 영역이 포함되면서, 소자분리영역이 추가로 일부 포함되도록 하여, S/D 영역의 측벽도 접촉면으로 활용함으로써, 접촉저항을 감소시키고, 소자구동 특성을 개선할 수 있는 효과가 있다.(9) When forming the metal contact window, the S / D region is included and the device isolation region is additionally included so that the sidewall of the S / D region is also used as the contact surface, thereby reducing the contact resistance and driving the element. There is an effect that can improve the characteristics.
(9) 상기의 기술을 통하여 나노급 신소자의 조속한 양산이 가능하여 질 경우, 고성능 기반의 신소자를 활용한 전자정보통신 기술의 발전속도의 가속화에 기여할 수 있는 효과가 있다. (9) When the mass production of nano-class new devices is possible through the above technology, there is an effect that can contribute to the acceleration of the development speed of electronic information communication technology using high-performance new devices.
도 1 내지 도 13a, 13b는 본 발명의 반도체 소자의 제조방법의 흐름도들이다.1 to 13A and 13B are flowcharts illustrating a method of manufacturing a semiconductor device of the present invention.
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| KR100814417B1 (en) * | 2006-10-02 | 2008-03-18 | 삼성전자주식회사 | Method of forming a silicon pattern having a single crystal and method of forming a non-volatile memory device using the same |
| KR100817074B1 (en) | 2006-11-08 | 2008-03-26 | 삼성전자주식회사 | Semiconductor device having fin type active area and method of manufacturing the same |
| US7629247B2 (en) * | 2007-04-12 | 2009-12-08 | Sandisk 3D Llc | Method of fabricating a self-aligning damascene memory structure |
| US8963257B2 (en) | 2011-11-10 | 2015-02-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin field effect transistors and methods for fabricating the same |
| KR101281152B1 (en) * | 2012-03-29 | 2013-07-02 | 고려대학교 산학협력단 | Method of fabricating multi-gate mosfet |
| CN103531467B (en) * | 2012-07-02 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof |
| KR102003276B1 (en) | 2013-02-14 | 2019-07-24 | 삼성전자 주식회사 | Method for fabricating semiconductor device |
| GB2529347B (en) * | 2013-06-28 | 2019-04-17 | Intel Corp | Making a defect free fin based device in lateral epitaxy overgrowth region |
| WO2014209396A1 (en) * | 2013-06-28 | 2014-12-31 | Intel Corporation | Integrating vlsi-compatible fin structures with selective epitaxial growth and fabricating devices thereon |
| KR101684616B1 (en) * | 2015-02-17 | 2016-12-07 | 경북대학교 산학협력단 | Semiconductor device and method of manufacturing thereof |
| RU2737136C2 (en) * | 2017-07-13 | 2020-11-25 | Интел Корпорейшн | Manufacturing of defects-free device based on a rib in the area of transverse epitaxial growth |
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| US9287401B2 (en) | 2013-11-15 | 2016-03-15 | Samsung Electronics Co., Ltd. | Semiconductor device having fin-type field effect transistor and method of manufacturing the same |
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