KR20050065044A - Method of fabricating semiconductor device including oxide layer contacted to source and drain - Google Patents

Abstract

A thermal oxide film covering the source / drain of the NMOS transistor is formed to redistribute the dopant of the source / drain of the NMOS transistor to reduce the source / drain resistance. After the formation of the NMOS transistor and the PMOS transistor, an oxide film covering the source / drain of the PMOS transistor is formed at low temperature by the ALD method. Accordingly, the PMOS transistor having a shallow junction can be formed to reduce the resistance of P ⁺ source / drain to increase the driving current of the PMOS transistor, and also to prevent the threshold voltage drop of the PMOS transistor due to the formation of the oxide film. Can be.

Description

Method of fabricating a semiconductor device having an oxide film in contact with a source and a drain {Method of fabricating semiconductor device including oxide layer contacted to source and drain}

TECHNICAL FIELD The present invention relates to the field of semiconductor device manufacturing, and more particularly, to a method for manufacturing a semiconductor device having an oxide film in contact with a source and a drain.

As the design rules of MOS transistors are rapidly reduced to 100 nm or less, source / drain formation of shallow junction heavily-doped structures is required. In terms of process technology, shallow junction formation of PMOS transistors is relatively more difficult than NMOS transistors. As or P used as a dopant to form an NMOS transistor has a low diffusivity, whereas B used as a dopant to form a PMOS transistor has a high diffusivity. to be.

Accordingly, many studies have been conducted on a method of increasing the driving current Idsat by forming a PMOS transistor having a low concentration in a shallow junction. As an example, attempts have been made to reduce diffusion by using heavy dopants such as BF ₂ or BF as P ⁺ dopants and ultimately to achieve shallow junctions. However, it is a general view that the use of heavy dopants alone is not only difficult to substantially reduce the diffusion of dopants, but also not sufficient to realize highly integrated devices of 100 nm or less.

A method of manufacturing a CMOS transistor according to the prior art will be described with reference to FIGS. 1A to 1C. 1A to 1C illustrate a peripheral circuit region of a semiconductor memory device having a cell region and a peripheral circuit region as an example.

As shown in FIG. 1A, after forming an isolation layer 11 to isolate an element in the semiconductor substrate 10, a p-type well 12 is formed in the semiconductor substrate 10 of the NMOS transistor region I. An n-type well 13 is formed in the semiconductor substrate 10 in the PMOS transistor region II. Subsequently, a gate oxide film 14 and a gate pattern G are formed on the p-type well 12 and the n-type well 13, respectively. The gate pattern G is formed by stacking and patterning the doped polysilicon layer 16, the tungsten silicide layer 17, and the hard mask layer 18. The hard mask layer 18 may be formed of a nitride film. Next, a re-oxide layer 18 is formed and ion implantation is performed to form a lightly doped drain (LDD). Subsequently, a gate buffer oxide film 19 and a spacer film 20 are deposited.

Next, a mask layer (not shown) covering the NMOS transistor region I is formed, and the spacer film 20, the gate buffer oxide film 19, and the reoxidation film 18 of the PMOS transistor region II are etched entirely. The spacer 20a is formed on the sidewall of the gate pattern G, and P ⁺ ion implantation, that is, BF ₂ or BF is ion implanted to form the p-type source / drain 21a. Subsequently, the mask layer covering the NMOS transistor region I is removed, a mask layer (not shown) covering the PMOS transistor region II is formed, and the spacer film 20 and the gate buffer of the NMOS transistor region I are formed. The oxide film 19 and the reoxidation film 18 are etched entirely to form a spacer 20a on the sidewall of the gate pattern G, and N ⁺ ion implantation, that is, As or P, is ion implanted to form an n-type source / drain ( 21b) to form an NMOS transistor and a PMOS transistor as shown in FIG. 1B. Next, the mask layer covering the PMOS transistor region II is removed. The source / drain 21a formation of the NMOS transistor and the source / drain 21b formation of the NMOS transistor may be performed in a reversed order.

Referring to FIG. 1C, an oxide film 22 is formed on the semiconductor substrate 10 on which an NMOS transistor and a PMOS transistor are formed to cover the source / drain 21a of the PMOS transistor and the source / drain 21b of the NMOS transistor. Subsequently, an interlayer insulating borophophosilicate glass (BPSG) 24 is formed on the oxide film 22. After the oxide film 22 is formed, the nitride film 23 for cell spacers may be formed.

As described above, the conventional CMOS transistor forming method deposits the oxide film 22 in contact with the source / drains 21a and 21b of the PMOS transistor and the NMOS transistor of the peripheral circuit. The oxide layer 22 may be formed by depositing hot temperature oxide (HTO) or tetraethylorthosilicate (TEOS) in a high temperature furnace type chamber or a low pressure chamber. However, it is known to reduce the resistances Rc and Rs of the p-type source / drain 21a regardless of the type of oxide film. The oxide film 22 serves as a diffusion barrier for P present in the BPSG 24 to prevent the counter-doping phenomenon of the p-type source / drain 21a, and the p-type source / drain 21a. It is presumed that this is because B existing in the X-ray pulls B to the interface of the oxide film 22. That is, according to the formation of the oxide film 22, it was found that ultimately, a shallow junction may be realized and the driving current Idsat may be increased to improve speed.

However, since the oxide film 22 is typically formed at a high temperature of 600 ° C. to 800 ° C., there is a problem in that adverse effects occur in device characteristics such as intensifying the threshold voltage of the PMOS transistor.

On the other hand, in high-integration devices of 100 nm or less, it is a challenge to form NMOS transistors having shallow source / drain junctions to reduce Rs and Rc resistances of NMOS transistor sources / drains as well as PMOS transistors.

SUMMARY OF THE INVENTION The present invention for solving the above problems provides a method of manufacturing a semiconductor device capable of forming an NMOS transistor having a shallow source / drain junction.

The present invention also provides a method of manufacturing a semiconductor device capable of forming an oxide film in contact with the source / drain of an NMOS transistor and a PMOS transistor at a low temperature.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a gate pattern of an NMOS transistor on a semiconductor substrate; Forming an n-type source / drain on a surface of the semiconductor substrate across the NMOS transistor gate pattern; And forming a thermal oxide film on the source / drain of the NMOS transistor.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: preparing a semiconductor substrate on which an NMOS transistor and a PMOS transistor are formed; And forming an ALD oxide film in contact with at least the source and drain of the PMOS transistor by atomic layer deposition.

In another embodiment, a method of manufacturing a semiconductor device includes forming gate patterns of an NMOS transistor and a PMOS transistor on a semiconductor substrate; Forming an n-type source / drain on a surface of the semiconductor substrate across the NMOS transistor gate pattern; Forming a thermal oxide film on the source / drain of the NMOS transistor; Forming a p-type source / drain on a surface of the semiconductor substrate across the gate pattern of the PMOS transistor; And forming an ALD oxide film in contact with the thermal oxide film and the p-type source / drain by atomic layer deposition.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.

A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 2A to 2G. 2A to 2G show a peripheral circuit region of a semiconductor memory device having a cell region and a peripheral circuit region as an example.

Referring to FIG. 2A, an isolation layer 110 isolating the semiconductor substrate 100 such as a silicon substrate. Subsequently, the p-type well 120 is formed in the semiconductor substrate 100 of the NMOS transistor region I, and the n-type well 130 is formed in the semiconductor substrate 100 of the PMOS transistor region II. The device isolation layer 110 may be formed by a shallow trench isolation (STI) process.

Referring to FIG. 2B, the gate insulating layer 140, the doped polysilicon layer 150, the silicide layer 160, and the hard layer are formed on the semiconductor substrate 100 on which the p-type well 120 and the n-type well 130 are formed. The mask layer 170 is stacked. The gate insulating layer 140, the polysilicon layer 150, the silicide layer 160, and the hard mask layer 170 may be 30 mV to 100 mV, 500 mV to 1000 mV, 800 mV to 1500 mV and 1500 mV, respectively. To 2500 kPa thick. The silicide layer 160 may be formed of tungsten silicide. A metal film may be formed in place of the silicide film 160. The hard mask layer 180 may be formed of a nitride film.

Referring to FIG. 2C, the hard mask layer 170, the silicide layer 160, and the polysilicon layer 150 are patterned to form a gate including a hard mask pattern 171, a silicide pattern 161, and a polysilicon pattern 151. The pattern G is formed.

Referring to FIG. 2D, in order to compensate for the damage generated during the etching process for forming the gate pattern G, a re-oxide layer 180 having a thickness of 30 to 70 70 is formed, and lightly doped Ion implantation is performed to form drains. Subsequently, the gate buffer oxide film 190 and the spacer film 200 are formed. The gate buffer oxide film 190 and the spacer film 200 may be formed to have a thickness of 80 to 150 GPa and 500 to 800 GPa, respectively. The spacer film 200 may be formed of a single film made of an oxide film or a double film of an oxide film and a nitride film.

Referring to FIG. 2E, the mask layer M covering the PMOS transistor region II is formed, and the spacer film 200, the gate buffer oxide film 190, and the reoxidation film 180 of the NMOS transistor region I are formed on the entire surface. By etching, the spacer 201 is formed on the sidewall of the gate pattern G of the NMOS transistor, and the n-type source / drain 211 is formed by implanting N ⁺ ions, that is, As or P. Then, to form a thermal oxidation film (thermal SiO _2, 220) on the source / drain 211 of the NMOS transistor. The thermal oxidation film 220 having a thickness of 30 kPa to 100 kPa may be formed by performing a dry or wet thermal oxidation process at a temperature of 700 ° C to 850 ° C.

As such, by forming the thermal oxide film 220 on the n-type source / drain 211 of the NMOS transistor, dopant redistribution may occur in the n-type source / drain 211. That is, when the thermal oxide film is formed on the source / drain 211 of the NMOS transistor including N ⁺ dopant such as As or P, since the segregation coefficient is larger than 1 and diffusion in the oxide film occurs slowly. After the thermal oxide film 220 is formed, a redistribution phenomenon occurs in which the dopant concentration on the surface of the source / drain 211 increases. Thus, the source / drain resistance of the highly integrated NMOS transistor can be reduced.

Referring to FIG. 2F, the mask layer M is removed, a mask layer (not shown) covering the NMOS transistor region I is formed, the spacer film 200 and the gate buffer of the PMOS transistor region II are formed. The oxide layer 190 and the reoxidation layer 180 are all etched to form a spacer 202 on the sidewall of the gate pattern G of the PMOS transistor, and P ⁺ ion implantation, that is, BF ₂ or BF is ion implanted to form a PMOS transistor. P-type source / drain 212 is formed. Next, the mask layer is removed.

Referring to FIG. 2G, an ALD oxide layer 230 is formed on the semiconductor substrate 100 on which an NMOS transistor and a PMOS transistor are formed to cover the p-type source / drain 212 and the thermal oxide layer 220. Subsequently, an interlayer insulating BPSG (borophophosilicate glass, 250) is formed on the ALD oxide layer 230. After the formation of the ALD oxide layer 230, the nitride film 240 for cell spacers having a thickness of 150 to 250 Å may be formed.

The ALD oxide layer 230 may be formed by depositing SiO ₂ by atomic layer deposition (ALD). At this time, a series of processes consisting of source gas supply / purge / oxidant gas supply / purge are repeatedly performed until the ALD oxide film 230 having a desired thickness is obtained. SiCl ₄ or Si ₂ Cl ₆ may be supplied as a source gas, and H ₂ O may be supplied as an oxidizing gas. When source gas is supplied, C ₅ H ₅ N or NH ₃ may be supplied as a catalyst after the source gas is supplied. The ALD oxide layer 230 may be formed at a temperature of 100 ° C. to 300 ° C. Therefore, it is possible to prevent the threshold voltage drop of the PMOS transistor by forming the ALD oxide film 230 at a high temperature. In addition, since ALD is deposited on an atomic layer basis, the ALD may form an ALD oxide layer 230 having excellent step coverage and may prevent oxidation of the metal layer or the metal silicide forming the gate pattern G. .

The interlayer insulating BPSG film 250 is formed to have a thickness of 6000 kPa to 8000 kPa, and a gap-fill flow process may be performed for 20 to 40 minutes at a temperature of 800 to 850 ° C. in a wet oxidizing atmosphere. .

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

According to the present invention, the thermal oxide film covering the source / drain of the NMOS transistor can be formed to redistribute the source / drain dopant of the NMOS transistor to reduce the source / drain resistance. After the formation of the NMOS transistor and the PMOS transistor, an oxide film covering the source / drain of the PMOS transistor is formed at low temperature by the ALD method. Accordingly, the PMOS transistor having a shallow junction can be formed to reduce the resistance of P ⁺ source / drain to increase the driving current of the PMOS transistor, and also to prevent the threshold voltage drop of the PMOS transistor due to the formation of the oxide film. Can be.

1A to 1C are cross-sectional views of a manufacturing process of a semiconductor device according to the prior art.

2A to 2G are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Explanation of reference numerals for the main parts of the drawing

100: semiconductor substrate 110: device isolation film

120: p-type well 130: n-type well

G: gate patterns 211 and 212: source / drain

220: thermal oxide film 230: ALD oxide film

Claims (8)

Forming a gate pattern of the NMOS transistor on the semiconductor substrate; Forming an n-type source / drain on a surface of the semiconductor substrate across the NMOS transistor gate pattern; And Forming a thermal oxide film on a source / drain of the NMOS transistor. Providing a semiconductor substrate on which an NMOS transistor and a PMOS transistor are formed; And Forming an ALD oxide film in contact with at least the source and drain of said PMOS transistor by atomic layer deposition. Forming gate patterns of an NMOS transistor and a PMOS transistor on a semiconductor substrate; Forming an n-type source / drain on a surface of the semiconductor substrate across the NMOS transistor gate pattern; Forming a thermal oxide film on the source / drain of the NMOS transistor; Forming a p-type source / drain on a surface of the semiconductor substrate across the gate pattern of the PMOS transistor; And Forming an ALD oxide film in contact with the thermal oxide film and the p-type source / drain by atomic layer deposition. The method of claim 2 or 3, The ALD oxide film is a method of manufacturing a semiconductor device, characterized in that formed at a temperature of 100 ℃ to 300 ℃. The method of claim 4, wherein The ALD oxide is A method of manufacturing a semiconductor device, characterized by supplying SiCl ₄ or Si ₂ Cl ₆ as a source gas, supplying H ₂ O as an oxidizing gas, and supplying C ₅ H ₅ N or NH ₃ as a catalyst. The method according to any one of claims 3 to 5, The p-type source / drain is formed by ion implantation of BF ₂ or BF. The method according to claim 1 or 3, The thermal oxide film is a method of manufacturing a semiconductor device, characterized in that formed by performing a dry or wet thermal oxidation process at a temperature of 700 ℃ to 850 ℃. The method according to any one of claims 1 to 3, The semiconductor substrate includes a cell region and a peripheral circuit region, And the NMOS transistor and the PMOS transistor are formed in the peripheral circuit region.