KR20050062853A - Mask for forming the poly silicon layer and crystallization method of silicon using it - Google Patents

Abstract

The mask for polycrystals according to the present invention comprises a first group having a plurality of first slits,

A second group having a plurality of second slits and a third slit, wherein the first group includes two or more first slits arranged in the Y-axis direction at intervals smaller than the Y-axis length of the first slit; The second slit is formed at a position overlapping with a portion of the first slit when is moved in parallel in the X-axis direction, and the third slit is formed at a position overlapping with two adjacent first slits.

Description

Mask for polycrystalline and silicon crystallization method using the same {Mask for forming the poly silicon layer and crystallization method of silicon using it}

The present invention relates to a mask for forming a polycrystalline silicon layer of a thin film transistor array panel and a silicon crystallization method using the same.

Generally, silicon may be divided into amorphous silicon and crystalline silicon according to the crystal state. Amorphous silicon can be deposited at a low temperature to form a thin film, and is mainly used for switching elements of liquid crystal panels using glass having a low melting point as a substrate.

However, the amorphous silicon thin film has difficulty in large area of the display device due to problems such as low field effect mobility. Therefore, there is a need for the application of polycrystalline silicon having high field effect mobility, high frequency operating characteristics, and low leakage current electrical characteristics.

The electrical properties of thin films using polycrystalline silicon are greatly influenced by the size and uniformity of the grains. That is, as the size and uniformity of the particles increase, the field effect mobility also increases. Therefore, there is increasing interest in a method of forming uniform polycrystalline silicon while increasing the particle size.

Methods for forming polycrystalline silicon include ELA (eximer laser anneal), furnace annealing (chamber annal), etc. Recently, a sequential lateral solidification (SLS) technique for producing polycrystalline silicon by inducing lateral growth of silicon crystals with a laser has been proposed. .

This SLS technology takes advantage of the fact that silicon particles grow at the interface between liquid silicon and solid silicon in a direction perpendicular to the interface, and shift the size of the laser beam energy and the shift of the irradiation range of the laser beam to an optical system and a mask. It is appropriately controlled by using to crystallize the amorphous silicon by causing the silicon particles to grow laterally by a predetermined length.

 At this time, the laser beam passes through the transmission region of the mask having a slit shape to completely dissolve the amorphous silicon, and forms a slit-shaped liquid region in the amorphous silicon layer. Subsequently, the liquid amorphous silicon is crystallized while cooling, and the crystal grows from the interface between the solid and liquid regions where the laser is not irradiated, and grows in a direction perpendicular to the interface. The growth of the crystals stops when they meet at the center of the liquid region.

This process proceeds by moving the mask having a slit shape perpendicularly to the growth direction of the crystal. This process then proceeds through the entire area of the amorphous silicon layer, where the crystal size grows by the slit width of the mask.

However, when the slit width of the mask having a slit shape is larger than the growth length of the crystal, it is located at a portion farther from the interface than the amorphous silicon of the liquid which is located near the interface between the solid region and the liquid region, that is, located at the center of the liquid region. The liquid amorphous silicon cools faster and forms nucleations in the central portion of the liquid region. At this time, the crystal of the region where the nucleus is formed has a problem of very low crystallinity.

Therefore, conventionally, the slit width of the mask having a slit shape is made small so that nucleation does not occur in the slit liquid region.

However, when the crystallization process is performed using such a conventional polycrystalline mask, when the slit width of the mask is smaller than the growth length of the crystal, the crystal that has grown in the direction perpendicular to the interface from the interface between the solid and liquid regions is lost. In the center of the liquid region, bumps are formed to collide with each other, and silicon is concentrated in the projections. In the protruding portion, the crystal grows more unevenly than other portions, such as the width of the crystal rapidly widens.

When the channel portion of the thin film transistor is located at a portion where the crystal grows unevenly, the characteristics of the thin film transistor are deteriorated, and thus, the image quality of the display device is uneven, and so is the case in the organic light emitting display device. The organic light emitting diode display is a display device using an organic material that emits light due to a flowing current, and the flow of the current is sensitively reacted according to the uniformity of the polycrystal.

The present invention has been made to solve the above problems and to provide a polycrystalline mask capable of forming a polycrystalline silicon layer having uniform crystals.

In addition, another technical problem of the present invention is to provide a silicon crystallization method for forming a polycrystalline silicon layer having uniform crystals using a polycrystalline mask.

In order to achieve the above object, the present invention provides a polycrystalline mask and a silicon crystallization method using the same.

More specifically, the second group includes a first group having a plurality of first slits, a second group having a plurality of second slits, and a third slit, wherein the first group includes two or more first slits having a Y-axis length of the first slit. Arranged in the Y-axis direction at smaller intervals, the second slit is formed at a position overlapping with a portion of the first slit when the second group is moved in the X-axis direction, and the third slit is adjacent to each other. The polycrystalline mask formed in the position which overlaps between 1st slit is provided.

Here, the first to third slits preferably define a transmission region through which a laser beam or light is transmitted.

Moreover, it is preferable that the X-axis length of a 2nd slit is formed equal to the X-axis length of a 1st slit.

In addition, it is preferable that the second slits overlap each other by the same length from the center of the first slit to both sides of the Y axis.

In addition, it is preferable that the third slit overlaps a portion of two first slits adjacent to each other, but overlaps by the same length along the Y axis.

Alternatively, depositing an amorphous silicon layer on an insulating substrate, and performing a sequential side crystallization process using a polycrystalline mask to crystallize the amorphous silicon layer into a polycrystalline silicon layer, wherein the polycrystalline mask includes a plurality of first slits And a second group having a first group having a plurality of second slits and a third slit, wherein the first group has two or more first slits arranged in the Y-axis direction at intervals smaller than the Y-axis length of the first slit. And the second slit is formed at a position overlapping with a portion of the first slit when the second group is moved in the X-axis direction in parallel, and the third slit is overlapped with two neighboring first slits. The silicon crystallization method formed in the process is provided.

In addition, the sequential side crystallization step is preferably performed while moving the mask for polycrystal from left to right.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. In contrast, when a part is just above another part, it means that there is no other part in between.

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a view showing a polycrystalline mask according to an embodiment of the present invention. Hereinafter, the up and down direction of the figure is referred to as the Y-axis direction and the left and right directions are referred to as the X-axis direction.

As shown in FIG. 1, the polycrystalline mask 300 according to the embodiment of the present invention includes a first group G1 including a plurality of first slits 310 and a plurality of second and third slits 320. , 330 is divided into a second group G2. Here, the first group G1 and the second group G2 are formed parallel to each other by a predetermined distance in the X-axis direction.

Next, the first group G1 and the second group G2 of the polycrystalline mask 300 will be described in more detail.

First, in the first group G1, the first slits 310 are arranged at regular intervals with respect to the Y axis at intervals of a length smaller than the Y axis length of the first slit 310. In this case, the Y-axis length of the first slit 310 is a portion corresponding to the first slit 310, that is, the first slit 310 when the SLS crystallization process is performed using the first slit 310. It is widely formed to cause nucleation in a portion of the liquid amorphous silicon layer having the same shape as.

The second group G2 is adjacent to the second slit 320 formed at a position overlapping with a portion of the first slit 310 when the second group is moved in parallel in the X-axis direction. And a third slit 330 formed at a position overlapping with a portion of the slit 310. At this time, the X-axis length of the second slit 320 and the third slit 330 is the same as the X-axis length of the first slit 310. In addition, the second slit 320 is formed to overlap the center portion of the first slit 310, that is, the portion where nucleation occurs, and the first slit 310 remaining after the second slit 320 overlaps the X axis. It is formed symmetrically with respect to. That is, the second slits 320 overlap with each other by the same length from the center of the first slits 310 to both sides of the Y axis. In addition, the third slit 330 similarly overlaps a portion of two first slits 310 neighboring each other, but overlaps the two first slits 310 neighboring each other by the same length on the Y axis.

Next, a method of forming a polycrystalline silicon layer according to an embodiment of the present invention using a polycrystalline mask according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a view schematically showing a sequential solid phase crystallization process of crystallizing amorphous silicon into polycrystalline silicon by laser irradiation, and FIG. 3 is a grain of a polycrystalline silicon layer crystallized using a polycrystalline mask according to an embodiment of the present invention. SEM picture taken.

As shown in FIG. 2, the first group G1 includes a plurality of first slits 310 and the second group G2 includes a plurality of second and third slits 320 and 330. The laser beam is irradiated through the polycrystalline mask 300. In addition, the amorphous silicon layer 150 corresponding to the first to third slits 310, 320, and 330 which locally melts the amorphous silicon layer 150 formed on the insulating substrate 110 to define a transmission region. ) To form first to third liquid regions 210, 220, and 230. At this time, the particles of the polycrystalline silicon grow in the direction perpendicular to the interface at the interface between the first to the third liquid region 210, 220, 230 irradiated with the laser and the solid region 200 not irradiated with the laser beam, respectively. . At this time, the growth of the particles in the second and third slit (320, 330) corresponding to the second and third liquid region (220, 230) the width of the second and third slits (320, 330) is nucleation Since it is formed small so as not to occur, it stops when it meets each other at the center of the second and third liquid regions 220 and 230.

On the other hand, since the first slit 310 is formed so that the width of the first slit 310 is wide to cause nucleation, the first liquid region 210 of the amorphous silicon layer 150 corresponding to the first slit 310. ) And at the interface 211 of the solid region 200 to which the laser beam is not irradiated, grow in a direction perpendicular to the interface 211, and at the central portion of the first liquid region 210. 231) Generation occurs. That is, the nucleus 231 is formed in the central portion of the first liquid region 210 so that the crystal grows again in the C direction (see FIG. 3). As a result, the height of the protrusions formed while the crystals growing in the direction perpendicular to the interface from the interface between the solid region and the liquid region collide with each other at the center of the liquid region can be lowered.

Next, a method of forming the polycrystalline silicon layer according to the exemplary embodiment of the present invention using the polycrystalline mask according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 4. 4 is a diagram illustrating a moving position of a polycrystalline mask and a corresponding irradiation area in a sequential side crystallization process.

As shown in FIG. 4, when the first shot process is performed, the polycrystalline mask 300 is moved to the mask position of the first shot to irradiate a laser beam. Subsequently, when the second shot process is performed, the polycrystalline mask 300 is moved to the mask position of the second shot to irradiate a laser beam. At this time, the polycrystalline mask 300 is moved by 1/2 of the X-axis length of the polycrystalline mask 300 so that the first group of the mask of the first shot and the second group of the mask of the second shot overlap. do. In addition, when irradiating a laser beam at a position where the first group of the mask of the first shot and the second group of the mask of the second shot overlap, when the laser beam is irradiated at the mask position of the first shot, The laser beam is irradiated and crystallized through the second and third slits of the second group of masks of the second shot to the solid-state region where the laser beam is not irradiated by the first slit of the first group and the region where nucleation has occurred. .

The shot is repeated several times, scanning in the right direction (B direction), and irradiating a laser beam to crystallize any one horizontal line of the amorphous silicon layer 150 to the polycrystalline silicon layer. The laser beam is then stepped below the left first starting point of the primary scanning. The laser beam is irradiated with a second scanning from left to right. Therefore, the other horizontal line adjacent to the horizontal line crystallized into the polycrystalline silicon layer by the first order scanning is crystallized into the polycrystalline silicon layer. By repeating this process, all horizontal lines are crystallized into a polycrystalline silicon layer so that all amorphous silicon layers 150 are crystallized.

The polysilicon layer and the polycrystalline mask therefor according to the embodiment of the present invention may be equally applicable to a thin film transistor array panel for an organic light emitting display device including the polycrystalline silicon layer and a method of manufacturing the same. It will be described in detail.

5 is a layout view of a thin film transistor array panel for an organic light emitting diode display according to an exemplary embodiment of the present invention, and FIGS. 6A and 6B are cross-sectional views taken along lines VIa-VIa 'and VIb-VIb' of FIG. 5, respectively. .

5 to 6B, a blocking layer 111 made of silicon oxide or the like is formed on the insulating substrate 110, and the polycrystalline silicon layers 153a 154a, 155a, 153b, and 154b are formed on the blocking layer 111. 155b and 157 are formed.

The polysilicon layers 153a, 154a, 155a, 153b, 154b, 155b, and 157 may include the first transistor portions 153a, 154a, 155a, the second transistor portions 153b, 154b, 155b, and the storage electrode portion 157. Include. The source region (first source region 153a) and the drain region (first drain region, 155a) of the first transistor portions 153a, 154a, and 155a are doped with n-type impurities, and the second transistor portions 153b and 154b. The source region (second source region 153b) and the drain region (second drain region 155b) of 155b are doped with p-type impurities. In this case, depending on the driving conditions, the first source region 153a and the drain region 155a may be doped with p-type impurities, and the second source region 153b and the drain region 155b may be doped with n-type impurities. .

A gate insulating layer 140 made of silicon oxide or silicon nitride is formed on the polycrystalline silicon layers 153a, 154a, 155a, 153b, 154b, 155b, and 157. On the gate insulating layer 140, a gate line 121 made of metal such as aluminum, chromium, molybdenum, or an alloy thereof, first and second gate electrodes 124a and 124b, and a storage electrode 133 are formed.

The first gate electrode 124a is formed in the shape of a branch of the gate line 121 and overlaps the channel region (first channel region 154a) of the first transistor, and the second gate electrode 124b is a gate line ( 121 and overlap with the channel region (second channel region 154b) of the second transistor. The storage electrode 133 is connected to the second gate electrode 124b and overlaps the storage electrode portion 157 of the polysilicon layer. One end of the gate line 121 may be formed wider than the width of the gate line 121 to receive a signal transmitted from an external driving circuit (not shown).

An interlayer insulating film 801 is formed on the gate line 121, the first and second gate electrodes 124a and 124b, and the storage electrode 133, and on the interlayer insulating film 801, the first and second data lines ( 171a and 171b, first and second source electrodes 173a and 173b, and first and second drain electrodes 175a and 175b are formed.

The first source electrode 173a is connected to the first source region 153a as a branch of the first data line 171a through a contact hole 181 penetrating through the interlayer insulating film 801 and the gate insulating film 140. The second source electrode 173b is a branch of the second data line 171b and a second source region 153b through a contact hole 184 penetrating through the interlayer insulating film 801 and the gate insulating film 140. It is connected. The first drain electrode 175a is in contact with the first drain region 155a and the second gate electrode 124b through the contact holes 182 and 183 penetrating the interlayer insulating layer 801 and the gate insulating layer 140. The second drain electrode 175b is connected to the second drain region 155b through a contact hole 185 penetrating through the gate insulating layer 140 and the interlayer insulating layer 801. On the other hand, the second data line 171b overlaps the sustain electrode 133.

An interlayer insulating film 802 having a contact hole 186 exposing the second drain electrode 175 is formed on the data lines 171a, 171b, 173a, and 173b and the drain electrodes 175a and 175b.

The pixel electrode 190 connected to the second drain electrode 175b is formed on the interlayer insulating layer 802 through the contact hole 186. The pixel electrode 190 is preferably formed of a material having excellent reflectivity such as aluminum. However, if necessary, the pixel electrode 190 may be formed of a transparent insulating material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

A partition wall 803 made of an organic insulating material is formed on the pixel electrode 190. The partition 803 surrounds the pixel electrode 190 to define a region in which the organic emission layer 70 is to be filled.

The partition wall 803 is formed by exposing and developing a photosensitive agent including a black pigment to serve as a light shielding film, and at the same time, the forming process may be simplified. The organic emission layer 70 is formed in an area on the pixel electrode 190 surrounded by the partition 802. The organic light emitting layer 70 is formed of an organic material emitting one of red, green, and blue light, and the red, green, and blue organic light emitting layers 70 are repeatedly arranged in sequence.

The buffer layer 804 is formed on the organic light emitting layer 70 and the partition 803. The buffer layer 804 may be omitted as necessary.

The common electrode 270 is formed on the buffer layer 804. The common electrode 270 is made of a transparent conductive material such as ITO or IZO. If the pixel electrode 190 is made of a transparent conductive material such as ITO or IZO, the common electrode 270 is formed of a metal having good reflectivity such as aluminum.

Although not shown, an auxiliary electrode may be formed of a metal having low resistance to compensate for the conductivity of the common electrode 270. The auxiliary electrode may be formed between the common electrode 270 and the buffer layer 804 or on the common electrode 270. The auxiliary electrode may be formed in a matrix shape along the partition wall 803 so as not to overlap the organic light emitting layer 70. . Here, the second data line 171b is connected to a constant voltage power supply.

The driving of the thin film transistor array panel for the organic light emitting diode display will be briefly described.

When an on pulse is applied to the gate line 121, the first transistor is turned on, and an image signal voltage applied through the first data line 171a is transferred to the second gate electrode 124b. . When the image signal voltage is applied to the second gate electrode 124b, the second transistor is turned on, and a current transmitted through the second data line 171b is transferred to the common electrode 270 through the pixel electrode 190 and the organic emission layer 70. Will flow). The organic light emitting layer 70 emits light in a specific wavelength band when current flows. The amount of light emitted by the organic light emitting layer 70 varies according to the amount of current flowing, thereby changing the brightness. At this time, the amount of current that the second transistor can flow is determined by the magnitude of the image signal voltage transmitted through the first transistor.

A method of manufacturing the thin film transistor array panel for the organic light emitting display device described above will be described in detail with reference to FIGS. 7 to 16B and FIGS. 5 to 6B.

7, 9, 11, 13, and 15 are layout views at an intermediate stage of a method of manufacturing a thin film transistor array panel for an organic light emitting diode display according to an exemplary embodiment of the present invention. 8A and 8B are cross-sectional views taken along the lines VIIIa-VIIIXa 'and VIIIb-VIIIb' of FIG. 7, respectively, and FIGS. 10A and 10B are XA-Xa 'of FIG. 9, respectively. 12A and 12B are cross-sectional views taken along the lines XIIa-XIIa 'and XIIb-XIIb' of FIG. 11, respectively, and FIGS. 14A and 14B are cross-sectional views taken along the line XB-Xb '. 13 are cross-sectional views taken along the lines XIVa-XIVa 'and XIVb-XIVb' of FIG. 13, and FIGS. 16A and 16B are cross-sectional views taken along the XVIa-XVIa 'and XVIb-XVIb' lines of FIG. 15, respectively. to be.

First, as shown in FIGS. 7 to 8B, a silicon oxide or the like is deposited on the insulating substrate 110 to form a blocking layer 111, and an amorphous silicon film is deposited on the blocking layer 111. The deposition of the amorphous silicon film may be performed by low temperature chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVE), or sputtering. Next, the amorphous silicon film is crystallized by the crystallization method using the polycrystalline masks according to the first and second embodiments of the present invention to form a polycrystalline silicon film having uniform grains (see FIGS. 2 to 4).

Next, the polycrystalline silicon film is patterned by a photolithography process to form the first and second transistor parts and the sustain electrode part 157.

As shown in FIG. 9 to FIG. 10B, the gate insulating layer 140 is deposited on the polycrystalline silicon layers 150a, 150b, and 157. Subsequently, metal is deposited to form a gate metal film 120. Thereafter, a photoresist film is coated on the gate metal film 120, followed by exposure and development to form a first photoresist film pattern PR1.

Next, the gate metal film 120 is etched using the first photoresist film pattern PR1 as a mask to form the second gate electrode 124b and the sustain electrode 133, and the exposed second transistor unit 150b. The p-type impurity ions are implanted into the polysilicon layer to form the second source region 153b, the second drain region 155b, and the second channel region 154b which is not doped with impurities. In this case, the polycrystalline silicon layer of the first transistor unit 150a is covered and protected by the first photoresist film pattern PR1 and the gate metal film 120. At this time, since the sustain electrode part 157 overlaps with the data line 171b formed later, the sustain electrode part 157 is protected by the photosensitive film so that impurities are not doped.

As shown in FIGS. 11 to 12B, the first photoresist pattern PR1 is removed, the photoresist is newly applied, exposed to light, and developed to form a second photoresist pattern PR2. The gate metal film 120 is etched using the second photosensitive film pattern PR2 as a mask to form the first gate electrode 124a and the gate line 121, and the exposed first polycrystalline silicon 150a polysilicon is formed. The n-type impurity ions are implanted into the layer to form the first source region 153a, the first drain region 155a, and the first channel region 154a which is not doped with impurities. At this time, the second transistor units 153b, 154b, and 155b and the storage electrode unit 157 are covered and protected by the second photosensitive film pattern PR2.

Next, as shown in FIGS. 13 to 14B, the interlayer insulating layer 801 is stacked on the gate lines 121, 124a, 124b, and 133, and the interlayer insulating layer 801 and the gate insulating layer 140 are formed by a photolithography process. The interlayer and the contact holes 181, 182, 184, and 185 exposing the first source region 173a, the first drain region 175a, the second source region 173b, and the second drain region 175b, respectively, by etching. The insulating layer 801 is etched to form a contact hole 183 exposing one end of the second gate electrode 124b.

Next, the data metal film is stacked and the data lines 171a, 171b, 173a and 173b and the drain electrodes 175a and 175b are formed by a photolithography process.

As shown in FIGS. 15 to 16B, the interlayer insulating layer 802 is formed on the data lines 171a, 171b, 173a, and 173b and the drain electrodes 175a and 175b, and then the interlayer insulating layer 802 is formed by a photolithography process. By etching, the contact hole 186 exposing the second drain electrode 175b is formed.

Subsequently, a metal having excellent reflectivity such as aluminum is deposited on the interlayer insulating layer 802 and patterned by a photolithography process to form a pixel electrode 190 connected to the second drain electrode 175b through the contact hole 186.

Next, as illustrated in FIGS. 5 to 6B, an organic film including a black pigment is coated on the data lines 171a, 171b, 173a, and 173b and the drain electrodes 175a and 175b, and exposed and developed to partition the barrier rib 803. The organic light emitting layer 70 is formed in each pixel area. At this time, the organic light emitting layer 70 usually has a multilayer structure. The organic light emitting layer 70 is deposited after masking, or formed by inkjet printing or the like.

Next, a conductive organic material is coated on the organic emission layer 70 to form a buffer layer 804, and ITO or IZO is deposited on the buffer layer 804 to form a common electrode 270.

At this time, although not shown, the auxiliary electrode may be formed of a low resistance material such as aluminum before or after the common electrode 270 is formed. In addition, when the pixel electrode 190 is formed of a transparent conductive material, the common electrode 270 is formed using a metal having excellent reflectivity.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary and can be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. There will be. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

As described above, when the amorphous silicon layer is crystallized using the polycrystalline mask according to the present invention, a uniform polycrystalline silicon layer can be obtained. Therefore, when the display panel including the polycrystalline silicon layer is formed, the current characteristics of the polycrystalline silicon layer are improved, thereby obtaining a high quality display panel.

1 is a view showing a mask for polycrystalline according to an embodiment of the present invention,

2 is a view schematically showing a sequential solid-state crystallization process of crystallizing amorphous silicon into polycrystalline silicon by irradiation with a laser,

FIG. 3 is an SEM photograph of crystal grains of a polycrystalline silicon layer crystallized using a polycrystalline mask according to an embodiment of the present invention.

4 is a view showing a moving position of the mask and the corresponding irradiation area in the sequential side crystallization process,

5 is a layout view of a thin film transistor array panel for an organic light emitting diode display according to an exemplary embodiment of the present invention.

6A and 6B are cross-sectional views taken along the lines VIa-VIa 'and VIb-VIb' of FIG. 5, respectively.

7, 9, 11, 13, and 15 are layout views in an intermediate step of a method of manufacturing a thin film transistor array panel for an organic light emitting diode display according to an exemplary embodiment of the present invention. The drawings are listed in the order of the process.

8A and 8B are cross-sectional views taken along the lines VIIIa-VIIIXa 'and VIIIb-VIIIb' of FIG. 7, respectively.

10A and 10B are cross-sectional views taken along the lines Xa-Xa 'and Xb-Xb' of FIG. 9, respectively.

12A and 12B are cross-sectional views taken along the lines XIIa-XIIa 'and XIIb-XIIb' of FIG. 11, respectively.

14A and 14B are cross-sectional views taken along lines XIVa-XIVa 'and XIVb-XIVb' of FIG. 13, respectively.

16A and 16B are cross-sectional views taken along the lines XVIa-XVIa 'and XVIb-XVIb' of FIG. 15, respectively.

Claims (7)

A first group having a plurality of first slits, A second group having a plurality of second slits and third slits, In the first group, at least two of the first slits are arranged in the Y-axis direction at intervals smaller than the Y-axis length of the first slit, When the second group is moved in parallel in the X-axis direction, the second slit is formed at a position overlapping with a portion of the first slit, and the third slit overlaps between two adjacent first slits. The polycrystalline mask formed at the position to be made. In claim 1, And the first to third slits define a transmission region through which a laser beam or light is transmitted. In claim 1, The X-axis length of the second slit is formed equal to the X-axis length of the first slit. In claim 1, And the second slit overlaps the same length from the center of the first slit to both sides of the Y axis by the same length. In claim 1, And the third slit overlaps a portion of two first slits adjacent to each other but overlaps the same length along the Y axis. Depositing an amorphous silicon layer on the insulating substrate, Performing a sequential side crystallization process using a polycrystalline mask to crystallize the amorphous silicon layer into a polycrystalline silicon layer, The polycrystalline mask includes a first group having a plurality of first slits, a second group having a plurality of second slits, and a third slit, wherein the first group includes two or more of the first slits in the first slit. Are arranged in the Y-axis direction at intervals smaller than the Y-axis length of the second slits, and when the second group is moved in parallel in the X-axis direction, the second slits are formed at positions overlapping with portions of the first slits, And the third slit is formed at a position overlapping with two adjacent first slits. In claim 6, And the sequential side crystallization step is performed while moving the polycrystalline mask from left to right.