KR100928053B1 - Crystallization Process of Thin Film Transistor for TOC LCD - Google Patents

Abstract

In the present invention, the array element including the thin film transistor and the pixel electrode and the color filter are aligned on the same substrate by using the structural characteristics of the thin film transistor on color filter (TOC) structure liquid crystal display device. As the SLS crystallization process is performed under process conditions in which a separate alignment key manufacturing process is omitted by forming keys simultaneously, firstly, only a desired position can be selectively crystallized as the crystallization process is performed using an alignment key. Since the position of grain boundary can be controlled, the device characteristics of the thin film transistor can be maintained uniformly over the entire pixel region, and secondly, in the same process as the color filter by using the structural characteristics in which the color filter is formed under the array elements. Separate alignment keymakers can be formed by using the same material to form alignment keys. Depending on the number, and, third, the color filter layer formed on the lower portion of the buffer layer to be omitted, by acting as a heat preservation layer in the SLS crystallization process of the color filter, it has the advantage to improve the crystallinity of the silicon layer.

Description

Crystallization Process of Thin Film Transistor for Array Thin Film Transistor Type Liquid Crystal Display Device}             

 1A shows a pattern of a mask used in SLS crystallization, and FIG. 1B shows a silicon layer crystallized by the mask pattern of FIG. 1A.

2 is a plan view of a crystallized polycrystalline silicon layer.

3A-3C are schematic cross-sectional views of an SLS crystallization process according to a first embodiment of the present invention.

4A through 4G are cross-sectional views illustrating a step of a manufacturing process of a thin film transistor for a TOC liquid crystal display including an SLS crystallization process according to a second embodiment of the present invention.

5A through 5F are cross-sectional views illustrating a manufacturing process of a TOC liquid crystal display including an SLS crystallization process according to a third embodiment of the present invention.

6A and 6B are process diagrams for a TOC liquid crystal display device according to a fourth exemplary embodiment of the present invention. The SLS crystallization process is illustrated, FIG. 6A is a cross-sectional view of the process, and FIG. 6B is a SLS crystallized silicon layer. Top view for.

7 is a cross-sectional view of a TOC liquid crystal display device according to a fifth embodiment of the present invention.                 

<Description of Symbols for Main Parts of Drawings>

210: substrate 212: color filter layer

214: alignment key 216: buffer layer

218: amorphous silicon layer IV: first region

V: second region

The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing a thin film transistor for a liquid crystal display device.

Recently, with the rapid development of the information society, there is a need for a flat panel display having excellent characteristics such as thinning, light weight, and low power consumption. Among them, a liquid crystal display having excellent color reproducibility, etc. displays are actively being developed.

In general, a liquid crystal display device is formed by arranging two substrates on which electric field generating electrodes are formed so that the surfaces on which the two electrodes are formed face each other, inserting a liquid crystal material between the two substrates, and then applying voltage to the two electrodes. It is a device that expresses an image by the transmittance of light that varies depending on the movement of liquid crystal molecules by moving the liquid crystal molecules by an electric field.                         

In the above-described liquid crystal display device, an active matrix type liquid crystal display device having a thin film transistor, which is a switching element for turning on / off a voltage for each pixel that is a minimum unit for displaying a screen, is mainly used. Recently, a liquid crystal display device employing a thin film transistor using poly-silicon (poly-Si) has been widely researched and developed. In a liquid crystal display using polycrystalline silicon, the thin film transistor and the driving circuit can be formed on the same substrate, and the process of connecting the thin film transistor and the driving circuit is unnecessary, thereby simplifying the process. In addition, since polycrystalline silicon has a field effect mobility of about 100 to 200 times larger than amorphous silicon, the response speed is fast and the stability of temperature and light is excellent.

Crystallization to polycrystalline silicon is the mainstream of the laser heat treatment process through the laser beam irradiation. However, since the surface temperature of the silicon film irradiated with the laser beam is about 1400 ° C., the surface of the silicon film is easily oxidized. In particular, in the laser heat treatment crystallization method, since the laser beam is irradiated many times, when the laser heat treatment is performed in the air, the surface of the silicon film irradiated with the laser beam is oxidized to generate SiO ₂ . Therefore, laser heat treatment should be carried out in a vacuum of about 10 ^-7 to 10 ^-6 torr.

In order to make up for the shortcomings of the crystallization method by laser heat treatment, a method of crystallizing by sequential lateral solidification (hereinafter referred to as SLS method) using a laser has recently been proposed and widely studied.                         

The SLS method takes advantage of the fact that the grain of silicon grows in the direction perpendicular to the interface at the interface between the silicon liquid region and the solid state region of the silicon, and moves the grain according to the size of the laser energy and the irradiation range of the laser beam. Crystallization method of the amorphous silicon thin film which can improve the size of the silicon grain by lateral growth by a predetermined length (Robert S. Sposilli, MA Crowder, and James S. Im, Mat. Res. Soc. Symp. Proc. Vol. 452, 956 to 957, 1997). The SLS method enables the fabrication of a thin film transistor having a single crystal silicon channel region by forming an SLS silicon thin film on the substrate with a large size of silicon grains.

This SLS crystallization method will be described below with reference to the accompanying drawings.

FIG. 1A illustrates a pattern of a mask used in SLS crystallization, and FIG. 1B illustrates a silicon layer crystallized by the mask pattern of FIG. 1A.

As shown in Fig. 1A, the mask 10 used for SLS crystallization has a slit pattern 12 of several mu m so that the laser beam is incident on the silicon layer with a width of several mu m. Here, the interval between the slit pattern 12 is also several μm, and the width of the slit pattern 12 may be 2 to 3 μm.

When the laser beam is irradiated to the amorphous silicon layer 20 of FIG. 1B through the slit pattern 12 of the mask 10, the amorphous silicon layer 22 to which the laser beam is irradiated is completely melted and then solidified to grow. In this case, grains 24a and 24b are laterally grown from both ends of the region 22 to which the laser beam is irradiated to stop growth at the portions where the grains 24a and 24b meet. Where these crystals meet is a grain boundary (28b).

Here, the mask 10 has a plurality of slit patterns 12, and the region to be crystallized corresponding to the size of the mask 10 is called a unit region.

Then, by irradiating the laser beam again including the crystallized region, the same process is repeated to crystallize all of the amorphous silicon layer.

A part of the polycrystalline silicon layer crystallized by the above method is shown in FIG.

As illustrated, the polycrystalline silicon layer includes a plurality of unit regions 30, and the first and second overlapping regions 40 and 50 where the irradiation of the laser beam overlap between the neighboring unit regions 30 are formed. Occurs. The first overlapping region 40 is positioned between the unit regions 30 adjacent in the horizontal direction, and the second overlapping region 50 is positioned between the unit regions 30 adjacent in the vertical direction.

Here, since the laser beam is irradiated several times, the first and second overlapping regions 40 and 50 have non-uniform portions. When the regions are located in the pixel region of the liquid crystal display, the image quality is deteriorated.

In order to solve this problem, it is an object of the present invention to provide an SLS crystallization process that can accurately control the position of the grain boundary.

To this end, the present invention is to provide a thin film transistor having a uniform device characteristics as a whole by controlling the position of the grain boundary as the crystallization proceeds precisely to the position in the design using the align key.

In still another object of the present invention, a color filter is utilized by utilizing the structural characteristics of a thin film transistor on color filter (TOC) structure liquid crystal display in which an array element including a thin film transistor and a pixel electrode and a color filter are formed on the same substrate. By forming the alignment key at the same time in the manufacturing process of, the SLS crystallization process to proceed under the process conditions that the separate alignment key manufacturing process is omitted.

The TOC liquid crystal display device can prevent the aperture ratio loss due to mis-alignment by forming the color filter and the array element on the same substrate, and as the color filter is positioned under the array element, the array element Wiring portions (gate wirings, data wirings) formed at the upper portion of the color filter are positioned at color boundaries, and thus, an additional black matrix manufacturing process can be omitted.

In addition, in the TOC liquid crystal display, since the color filter layer is positioned on the lowermost layer of the substrate, the color filter layer may act as a heat preservation layer in the SLS crystallization process, and thus may have an additional effect of improving crystallinity.

In order to achieve the above object, in the first aspect of the present invention, a color resin is used on a display area and a substrate on which a non-display area is defined outside the display area, and color is displayed in the display area. Forming an alignment key in the filter layer and the non-display area; Forming a buffer layer over the substrate over the color filter layer and the alignment key; Forming an amorphous silicon layer over the buffer layer over the substrate; Selectively crystallizing a first region of the amorphous silicon layer with respect to the alignment key using an energy density that completely melts the amorphous silicon layer; Patterning the crystallized silicon layer into a semiconductor layer based on the alignment key; Forming a gate insulating film and a gate electrode sequentially stacked on the center of the semiconductor layer based on the alignment key; Doping the crystallized silicon layer exposed to the outside of the gate electrode using the gate electrode as a blocking mask to form a source region and a drain region, respectively; Forming an interlayer insulating film having first and second contact holes exposing the source and drain regions, respectively, over the gate insulating film; Forming a source and a drain electrode on the interlayer insulating layer, the source and drain electrodes being in contact with and spaced apart from the source and drain regions, respectively, wherein the color filter layer is used as a heat preservation layer in the crystallization step. To provide.

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In the second aspect of the present invention, a color filter layer and the non-display area are used for the display area by using a color resin on a display area and a substrate on which a non-display area is defined outside the display area. Forming an alignment key in the; Forming a buffer layer over the substrate over the color filter layer and the alignment key; Forming an amorphous silicon layer over the buffer layer over the substrate; Forming a dummy pattern in a first region on the amorphous silicon layer based on the alignment key; Doping the exposed amorphous silicon layer region using the dummy pattern as a mask; Removing the dummy pattern; Based only on the alignment key, only the portion of the doped regions including the first region, including the first region, to form a semiconductor layer of polysilicon, using an energy density capable of completely melting the doped silicon layer Crystallizing with a polysilicon layer; Patterning the polysilicon layer based on the alignment key to form a semiconductor layer of polysilicon having the first undoped first region and a source and drain region doped with impurities on both sides of the first region Wow; Forming a gate insulating film over the semiconductor layer of polysilicon; Forming a gate electrode on the gate insulating layer corresponding to the second region; Forming an interlayer insulating layer over the gate electrode, and patterning the interlayer insulating layer and the lower gate insulating layer to form a first contact hole exposing the source and drain regions; Forming a source and a drain electrode on the interlayer insulating layer through the first contact hole, the source and drain electrodes being in contact with and spaced apart from each other, wherein in the crystallization step, the color filter layer is used as a heat preservation layer. A method of manufacturing a substrate for a display device is provided.

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In the first and second aspects of the present invention, the forming of the color filter layer may include forming red, green, and blue color filters in order, wherein the crystallized silicon layer includes a plurality of grains and the grains. And a sub-grain boundary located at the boundary between the grains, and a grain boundary located at the boundary between the grain groups, wherein the color filter layer is used to grow the grain size in the crystallization step.

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Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

First Embodiment                     

3A to 3C are schematic cross-sectional views of an SLS crystallization process according to a first embodiment of the present invention.

3A illustrates forming a buffer layer 112 on a substrate 110 in which a first region I and a second region II positioned at both sides of the first region I are defined, and a buffer layer 112. In this step, the alignment key 114 is formed in the second region II.

The buffer layer 112 is formed to a thickness value having a step at a position corresponding to the alignment key 114, is selected from a silicon insulating material, for example, a silicon oxide film (SiO ₂ ).

The alignment key 114 may be formed by a photolithography process using chromium (Cr).

In FIG. 3B, the amorphous silicon layer 116 is formed in an area covering the alignment key 114, and in FIG. 3C, the third region (1) of the first region I is based on the alignment key 114. III) selectively only SLS crystallization.

The third region III corresponds to a semiconductor layer formation region.

As described above, according to the SLS crystallization process according to the present embodiment, since only the desired region can be selectively crystallized using the alignment key, the process efficiency can be increased, and the position of the grain boundary can be easily controlled. do.

However, this embodiment has a disadvantage in that a separate process for forming an alignment key is added.                     

In order to improve this disadvantage, another embodiment of the present invention relates to an SLS crystallization process of a TOC liquid crystal display device in which a color filter layer and an array element are formed on the same substrate, and in the case of the TOC structure, the color filter layer is disposed under the array element layer. In the following embodiment, the separate alignment key manufacturing process may be omitted by simultaneously forming the alignment key in the manufacturing process of the color filter layer.

Second Embodiment

4A through 4G are cross-sectional views illustrating a manufacturing process of a thin film transistor for a TOC liquid crystal display including an SLS crystallization process according to a second exemplary embodiment of the present invention, and a SA (self-aligned) structure thin film transistor is an example. Present it.

In FIG. 4A, a first region IV is formed on a substrate 210 on which a first region IV and a second region V positioned on both sides of the first region IV are defined. ) To form the color filter layer 212 and to form the alignment key 214 in the second region (V).

Although not shown in detail in the drawings, the color resin corresponds to red, green, and blue color resins, and the forming of the color filter layer 212 includes forming red, green, and blue color filters in order. The alignment key 214 may be made of a single color resin material or may be formed in a pattern in which a plurality of color resins are combined.

For example, the color resin may correspond to a color resin having any one of red, green, and blue color resins, and the color filter layer and the alignment key may correspond to each pattern formed of a single color color resin. .

In this step, it is possible to omit the step of forming a separate black matrix on each color boundary.

In FIG. 4B, the buffer layer 216 is formed in the region covering the color filter layer 212 and the alignment key 214, and the amorphous silicon layer 218 is formed in the region covering the buffer layer 216.

In FIG. 4C, a step of selectively SLS crystallizing the amorphous silicon layer 218 positioned in the first region IV based on the alignment key 214, and FIG. 4D is a patterned semiconductor layer by patterning the crystallized silicon layer. Forming layer 220 is a step.

In FIG. 4E, the gate insulating layer 222 and the gate electrode 224 are sequentially formed in the center of the semiconductor layer 220 based on the alignment key 214. In FIG. 4F, the gate electrode 224 is formed. A step of doping the exposed semiconductor layer 220 using a mask is performed.

Through this step, the semiconductor layer 220 includes an active region VI positioned to correspond to the gate electrode 224, and a source region VII and a drain region VIII which are doped regions.

In FIG. 4G, first and second contact holes 226 and 228 positioned in a region covering the gate electrode 224 and partially exposing the source region VII and the drain region VIII of the semiconductor layer 220. Forming an interlayer insulating film 230 having a source layer; and a source electrode 232 connected to the source region VII of the semiconductor layer 220 through the first contact hole 226 on the interlayer insulating film 230; And forming a drain electrode 234 connected to the drain region VIII of the semiconductor layer 220 through the second contact hole 228.

The semiconductor layer 220, the gate electrode 224, the source electrode 232, and the drain electrode 234 form a thin film transistor T.

Third Embodiment

5A through 5F are cross-sectional views illustrating a manufacturing process of a TOC liquid crystal display including an SLS crystallization process according to a third embodiment of the present invention. FIG. 5A through 5F illustrate a non self-aligned thin film transistor as an example. It was.

5A and 5B, as shown in FIGS. 4A and 4B, the color filter layer 312 is formed in the first region IV using color resin on the substrate 310, and is aligned with the second region V. Referring to FIGS. Forming the key 314 (FIG. 5A), and sequentially forming the buffer layer 316 and the amorphous silicon layer 318 in the region covering the color filter layer 312 and the alignment key 314 (FIG. 5B). )to be.

Next, in FIG. 5C, the dummy pattern 320 is formed in the active region VI of the first region IV, and the exposed amorphous silicon layer 318 region is formed using the dummy pattern 320 as a mask. Doping treatment step.

The active area VI corresponds to a channel area defined as a movement path of a carrier.

In FIG. 5D, the dummy pattern 320 is removed and the first region IV is SLS-crystallized based on the alignment key 314 to form the crystalline silicon layer 322.

In FIG. 5E, the semiconductor layer 324 is formed based on the alignment key 314.

In this step, the region corresponding to the third region VI forms the active region VI described above, and both sides of the active region VI form the source region VII and the drain region VIII.

Since the silicon layer region doped using the above-described dummy pattern (320 of FIG. 5C) is formed based on the dummy pattern (320 of FIG. 5C) and the alignment key 314 in step 5C, the silicon layer region of FIG. When the crystalline silicon layer (322 of FIG. 5D) is patterned based on the alignment key 314, the doped region may be defined as the source region VII and the drain region VIII.

In FIG. 5F, the gate insulating layer 326 and the gate electrode 328 are sequentially formed in the center of the semiconductor layer 324.

In FIG. 5G, the source electrode 330 and the drain electrode 332 are formed on the gate electrode 328, and the semiconductor layer 324, the gate electrode 328, the source electrode 330, and the drain electrode ( 332 forms a thin film transistor (T).

This embodiment has the following advantages compared to the existing SLS crystallization process.

First, as the crystallization process is performed using the align key, only the desired position can be crystallized selectively, and thus the grain boundary can be controlled to maintain the device characteristics of the thin film transistor uniformly over the entire pixel region. have.

Second, when the SLS crystallization process is performed in the TOC liquid crystal display, since the color filter layer is formed under the array element, an alignment key is manufactured by forming an alignment key using the same material in the same process as the color filter layer. The process can be omitted.

Third, as the color filter layer is formed under the buffer layer, it acts as a heat preservation layer in the SLS crystallization process of the color filter layer, thereby improving the crystallinity of the silicon layer.

Fourth Embodiment

6A and 6B are process diagrams for a TOC liquid crystal display device according to a fourth exemplary embodiment of the present invention. The SLS crystallization process is illustrated, FIG. 6A is a cross-sectional view of the process, and FIG. 6B is a SLS crystallized silicon layer. This is a plan view of the.

As shown in FIG. 6A, a color filter layer 412 is formed on the substrate 410, a buffer layer 414 is formed on the color filter layer 412, and a crystallization process is performed on the buffer layer 414 through an SLS crystallization process. A silicon layer 416 is formed that includes the treated crystalline silicon region IX.

The color filter layer 412 is disposed under the buffer layer 414 and serves as a kind of heat preservation layer in the SLS crystallization process, and serves to prevent the heat energy irradiated to the silicon layer from escaping to the outside. It is characterized by playing a role of improving crystallinity.

6B, the crystalline silicon layer 418 may include a plurality of grains 420 and a sub grain boundary 422 positioned at a boundary between the grains 420. And a grain boundary 424 located at the boundary between the groups of grains 420.

The crystalline silicon layer 418 is crystallized through a melting and solidification process, wherein the grain size (X) is determined by the solidification rate. If the solidification speed is high, the gray size X may be decreased, and if the solidification speed is slowed, the grain size X may be increased.

According to such a crystallization principle of silicon, the present embodiment is characterized in that it is used as a kind of heat preservation layer in the SLS crystallization process of the color filter layer located in the lowermost layer of the substrate due to the TOC structure characteristic. That is, in the SLS crystallization process, the rate at which heat energy radiated to the silicon layer is transferred to the outside is suppressed by the color filter layer, thereby improving crystallinity.

Conventionally, a stack structure in which a plurality of buffer layers are formed in order to improve crystallinity by a method of improving thermal preservation has been proposed, but in the present invention, the effect of using a color filter layer as a heat preservation layer without any additional process is provided. It has the added advantage.

In conclusion, in the present invention, since the color filter is located under the buffer layer due to the characteristic of the TOC structure, the advantage that the TOC structure has the advantage of having the + preservation ability is added.

Fifth Embodiment                     

7 is a cross-sectional view of a TOC liquid crystal display according to a fifth embodiment of the present invention.

As illustrated, the first and second substrates 510 and 550 are disposed to face each other, the color filter layer 512 is formed on the first substrate 510, and the color boundaries of the color filter layer 512 are provided. And a planarization layer 514 is formed on the upper portion. The planarization layer 514 corresponds to a pattern for increasing planarization characteristics of the color filter layer 512, and may be omitted in some cases.

Although not shown in detail in the drawings, the color filter layer 512 has a structure in which red, green, and blue color filters are sequentially arranged in sequence, and are illustrated with an area including blue and red color filters on the drawing.

A buffer layer 518 is formed on the planarization layer 514, and a thin film transistor including a semiconductor layer 520, a gate electrode 522, a source electrode 524, and a drain electrode 526 on the buffer layer 518. (T) is formed. A protective layer 530 having a drain contact hole 528 exposing a part of the drain electrode 526 is formed at a position covering the thin film transistor T, and a drain contact hole 528 is formed on the protective layer 530. A pixel electrode 532 is formed to be connected to the drain electrode 526 through the first electrode, and a first alignment layer 534 is formed in a region covering the pixel electrode 532.

The semiconductor layer 520 includes an active region VI corresponding to the gate electrode 522, a source region VII and a drain region VIII located on both sides of the active region VI. The source region VII and the drain region VIII are doped regions, which are not shown in the drawing but doped by an NSA process using an alignment key made of the same material in the same process as the color filter layer 512. It features.

The common electrode 552 and the second alignment layer 554 are sequentially formed on the inner surface of the second substrate 550, and the liquid crystal layer 560 is interposed between the first and second alignment layers 534 and 554. It is.

The present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention.

As described above, according to the SLS crystallization process for the TOC liquid crystal display according to the present invention, first, as the crystallization process is performed by using an alignment key, only a desired position can be selectively crystallized, thereby controlling the position of the grain boundary. Therefore, the device characteristics of the thin film transistor can be maintained uniformly over the entire pixel region, and secondly, by using the structural characteristic of forming a color filter under the array element, an alignment key is used using the same material in the same process as the color filter. As a result, a separate alignment key manufacturing process can be omitted. Third, as the color filter layer is formed under the buffer layer, the crystal layer of the silicon layer acts as a heat preservation layer in the SLS crystallization process of the color filter layer. Can be improved.

Claims (12)

Forming a color filter layer in the display area and an alignment key in the non-display area by using a color resin on a display area and a substrate on which a non-display area is defined outside the display area. Wow; Forming a buffer layer over the substrate over the color filter layer and the alignment key; Forming an amorphous silicon layer over the buffer layer over the substrate; Selectively crystallizing a first region of the amorphous silicon layer with respect to the alignment key using an energy density that completely melts the amorphous silicon layer; Patterning the crystallized silicon layer into a semiconductor layer based on the alignment key; Forming a gate insulating film and a gate electrode sequentially stacked on the center of the semiconductor layer based on the alignment key; Doping the crystallized silicon layer exposed to the outside of the gate electrode using the gate electrode as a blocking mask to form a source region and a drain region, respectively; Forming an interlayer insulating film having first and second contact holes exposing the source and drain regions, respectively, over the gate insulating film; Forming a source and a drain electrode on the interlayer insulating layer, the source and drain electrodes being in contact with and spaced apart from the source and drain regions, respectively. And a color filter layer used as a heat preservation layer in the crystallization step. delete delete delete Forming a color filter layer in the display area and an alignment key in the non-display area by using a color resin on a display area and a substrate on which a non-display area is defined outside the display area. Wow; Forming a buffer layer over the substrate over the color filter layer and the alignment key; Forming an amorphous silicon layer over the buffer layer over the substrate; Forming a dummy pattern in a first region on the amorphous silicon layer based on the alignment key; Doping the exposed amorphous silicon layer region using the dummy pattern as a mask; Removing the dummy pattern; Based only on the alignment key, only the portion of the doped regions including the first region, including the first region, to form a semiconductor layer of polysilicon, using an energy density capable of completely melting the doped silicon layer Crystallizing with a polysilicon layer; Patterning the polysilicon layer based on the alignment key to form a semiconductor layer of polysilicon having the first undoped first region and a source and drain region doped with impurities on both sides of the first region Wow; Forming a gate insulating film over the semiconductor layer of polysilicon; Forming a gate electrode on the gate insulating layer corresponding to the second region; Forming an interlayer insulating layer over the gate electrode, and patterning the interlayer insulating layer and the lower gate insulating layer to form a first contact hole exposing the source and drain regions; Forming source and drain electrodes on the interlayer insulating layer, the source and drain electrodes being in contact with the source and drain regions and spaced apart from each other through the first contact hole; And a color filter layer used as a heat preservation layer in the crystallization step. delete delete The method according to any one of claims 1 to 5, The forming of the color filter layer may include forming red, green, and blue color filters in order. delete The method according to any one of claims 1 to 5, And wherein the buffer layer has a step corresponding to the alignment key. The method according to any one of claims 1 to 5, The crystallized silicon layer is composed of a plurality of grains, a sub grain boundary located at the boundary between the grains, and a grain boundary located at the boundary between the grain groups, and in the crystallization step, the color filter layer grows the grain size. The manufacturing method of the board | substrate for liquid crystal display devices used for carrying out. delete

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