KR20050060958A - Liquid crystal display device and manufacturing and testing method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device capable of simplifying a substrate structure and manufacturing process, a manufacturing method thereof, and an inspection method.

According to an exemplary embodiment of the present invention, a liquid crystal display includes: a gate pattern including a gate electrode of a thin film transistor, a gate line connected to a gate electrode, and a gate pad lower electrode connected to a gate line on a substrate; A source / drain pattern including a source electrode and a drain electrode of the thin film transistor, a data line connected to the source electrode, and a data pad lower electrode connected to the data line; A semiconductor pattern formed below the source / drain pattern; A transparent electrode including a pixel electrode connected to the drain electrode, a gate pad upper electrode connected to the gate pad lower electrode and having a line width of 26 μm or more, and a data pad upper electrode connected to the data pad lower electrode and of a line width of 26 μm or more An electrode pattern; And a gate insulating pattern and a protective layer pattern stacked in the remaining regions except for the region in which the transparent electrode pattern is formed.

Description

Liquid crystal display, manufacturing method and inspection method {LIQUID CRYSTAL DISPLAY DEVICE AND MANUFACTURING AND TESTING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a thin film transistor array substrate capable of simplifying a substrate structure and a manufacturing process, and a manufacturing method and an inspection method thereof.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

The liquid crystal panel includes a thin film transistor array substrate and a color filter array substrate facing each other, a spacer positioned to maintain a constant cell gap between the two substrates, and a liquid crystal filled in the cell gap.

The thin film transistor array substrate includes gate lines and data lines, thin film transistors formed of switch elements at intersections of the gate lines and data lines, pixel electrodes formed in liquid crystal cells and connected to the thin film transistors, and the like. It consists of the applied alignment film. The gate lines and the data lines receive signals from the driving circuits through the respective pad parts. The thin film transistor supplies the pixel voltage signal supplied to the data line to the pixel electrode in response to the scan signal supplied to the gate line.

The color filter array substrate includes color filters formed in units of liquid crystal cells, a black matrix for distinguishing between color filters and reflecting external light, a common electrode for supplying a reference voltage to the liquid crystal cells in common, and an alignment layer applied thereon. It consists of.

The liquid crystal panel is completed by separately manufacturing a thin film transistor array substrate and a color filter array substrate, and then injecting and encapsulating a liquid crystal.

In such a liquid crystal panel, the thin film transistor array substrate includes a semiconductor process and requires a plurality of mask processes, and thus, the manufacturing process is complicated, which is a major cause of the increase in the manufacturing cost of the liquid crystal panel. In order to solve this problem, the thin film transistor array substrate is developing in a direction of reducing the number of mask processes. This is because one mask process includes many processes such as a deposition process, a cleaning process, a photolithography process, an etching process, a photoresist stripping process, and an inspection process. Accordingly, in recent years, a four-mask process that reduces one mask process has emerged in the five-mask process, which is a standard mask process of a thin film transistor array substrate.

FIG. 1 is a plan view of a thin film transistor array substrate employing a four mask process, for example. FIG. 2 is a cross-sectional view of the thin film transistor array substrate of FIG. 1 taken along line II ′.

The thin film transistor array substrate shown in FIGS. 1 and 2 includes a gate line 2 and a data line 4 intersecting each other with a gate insulating film 44 interposed on the lower substrate 42, and a thin film formed at each intersection thereof. The transistor 6 and the pixel electrode 18 formed in the cell area provided in the cross structure are provided. The thin film transistor array substrate includes a storage capacitor 20 formed at an overlapping portion of the pixel electrode 18 and the front gate line 2, a gate pad portion 26 connected to the gate line 2, and a data line ( And a data pad portion 34 connected to 4).

The thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, and a drain electrode 12 connected to the pixel electrode 16. And an active layer 14 overlapping the gate electrode 8 and forming a channel between the source electrode 10 and the drain electrode 12. The active layer 14 is formed to overlap the data pad lower electrode 36, the storage electrode 22, the data line 4, the source electrode 10, and the drain electrode 12, and the source electrode 10 and the drain electrode ( 12) further comprises a channel section therebetween. An ohmic contact layer 48 for ohmic contact with the data pad lower electrode 36, the storage electrode 22, the data line 4, the source electrode 10, and the drain electrode 12 is further formed on the active layer 14. do. The thin film transistor 6 causes the pixel voltage signal supplied to the data line 4 to be charged and held in the pixel electrode 18 in response to the gate signal supplied to the gate line 2.

The pixel electrode 18 is connected to the drain electrode 12 of the thin film transistor 6 through the first contact hole 16 penetrating the protective film 50. The pixel electrode 18 generates a potential difference from the common electrode formed on the upper substrate (not shown) by the charged pixel voltage. Due to this potential difference, the liquid crystal positioned between the thin film transistor substrate and the upper substrate rotates by dielectric anisotropy, and transmits light incident through the pixel electrode 18 from the light source (not shown) toward the upper substrate.

The storage capacitor 20 includes the front gate line 2, the storage electrode 22 overlapping the gate line 2, the gate insulating layer 44, the active layer 14, and the ohmic contact layer 48 therebetween. And a pixel electrode 22 which is overlapped with the storage electrode 22 and the passivation layer 50 interposed therebetween and connected via the second contact hole 24 formed in the passivation layer 50. The storage capacitor 20 allows the pixel voltage charged in the pixel electrode 18 to be stably maintained until the next pixel voltage is charged.

The gate line 2 is connected to a gate driver (not shown) through the gate pad part 26. The gate pad portion 26 is formed through the gate pad lower electrode 28 extending from the gate line 2, and the gate pad lower electrode through the third contact hole 30 penetrating through the gate insulating layer 44 and the passivation layer 50. And a gate pad upper electrode 32 connected to (28).

The data line 4 is connected to a data driver (not shown) through the data pad unit 34. The data pad part 34 is connected to the data pad lower electrode 36 through the data pad lower electrode 36 extending from the data line 4 and the fourth contact hole 38 penetrating through the passivation layer 50. The data pad upper electrode 40 is formed.

The thin film transistor array substrate having this configuration is formed in a four mask process.

3A to 3D are cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate in stages.

Referring to FIG. 3A, gate patterns are formed on the lower substrate 42.

The gate metal layer is formed on the lower substrate 42 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask to form gate patterns including the gate line 2, the gate electrode 8, and the gate pad lower electrode 28. As the gate metal, chromium (Cr), molybdenum (Mo), aluminum-based metal, etc. are used in a single layer or a double layer structure.

Referring to FIG. 3B, the gate insulating layer 44, the active layer 14, the ohmic contact layer 48, and the source / drain patterns are sequentially formed on the lower substrate 42 on which the gate patterns are formed.

The gate insulating layer 44, the amorphous silicon layer, the n + amorphous silicon layer, and the source / drain metal layer are sequentially formed on the lower substrate 42 on which the gate patterns are formed by a deposition method such as PECVD or sputtering.

A photoresist pattern is formed on the source / drain metal layer by a photolithography process using a second mask. In this case, by using a diffraction exposure mask having a diffraction exposure portion in the channel portion of the thin film transistor, the photoresist pattern of the channel portion has a lower height than other source / drain pattern portions.

Next, the source / drain metal layer is patterned by a wet etching process using a photoresist pattern, so that the data line 4, the source electrode 10, the drain electrode 12 integrated with the source electrode 10, and the storage electrode 22 are formed. Source / drain patterns including are formed.

Next, the n + amorphous silicon layer and the amorphous silicon layer are simultaneously patterned by a dry etching process using the same photoresist pattern to form the ohmic contact layer 48 and the active layer 14.

The photoresist pattern having a relatively low height in the channel portion is removed by an ashing process, and then the source / drain pattern and the ohmic contact layer 48 of the channel portion are etched by a dry etching process. Accordingly, the active layer 14 of the channel portion is exposed to separate the source electrode 10 and the drain electrode 12.

Subsequently, the photoresist pattern remaining on the source / drain pattern portion is removed by a stripping process.

As the material of the gate insulating film 44, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used. As a source / drain metal, molybdenum (Mo), molybdenum alloy (Mo alloy), AlNd (alunium neodium), etc. are used.

Referring to FIG. 3C, a passivation layer 50 including first to fourth contact holes 16, 24, 30, and 38 is formed on the gate insulating layer 44 on which the source / drain patterns are formed.

The passivation layer 50 is entirely formed on the gate insulating layer 44 on which the source / drain patterns are formed by a deposition method such as PECVD. The passivation layer 50 is patterned by a photolithography process and an etching process using a third mask to form first to fourth contact holes 16, 24, 30, and 38. The first contact hole 16 is formed to pass through the passivation layer 50 to expose the drain electrode 12, and the second contact hole 24 is formed to pass through the passivation layer 50 to expose the storage electrode 22. do. The third contact hole 30 is formed to pass through the passivation layer 50 and the gate insulating layer 44 to expose the gate pad lower electrode 28. The fourth contact hole 38 is formed through the passivation layer 50 to expose the lower data pad electrode 36.

As the material of the protective film 50, an inorganic insulating material such as the gate insulating film 94 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB is used.

Referring to FIG. 3D, transparent electrode patterns are formed on the passivation layer 50.

The transparent electrode material is entirely deposited on the passivation layer 50 by a deposition method such as sputtering. Subsequently, the transparent electrode material is immersed through a photolithography process and an etching process using a fourth mask, thereby forming transparent electrode patterns including the pixel electrode 18, the gate pad upper electrode 32, and the data pad upper electrode 40. Is formed. The pixel electrode 18 is electrically connected to the drain electrode 12 through the first contact hole 16, and the storage electrode 22 overlaps the previous gate line 2 through the second contact hole 24. And electrically connected. The gate pad upper electrode 32 is electrically connected to the gate pad lower electrode 28 through the third contact hole 30. The data pad upper electrode 40 is electrically connected to the data pad lower electrode 36 through the fourth contact hole 38. Indium tin oxide (ITO), tin oxide (TO) or indium zinc oxide (IZO) is used as the transparent electrode material.

As described above, the thin film transistor substrate of the conventional liquid crystal display device and the method of manufacturing the same may reduce the number of manufacturing processes and reduce manufacturing costs in proportion to the case of using the five mask process by employing a four mask process. However, since the four-mask process is still a complicated manufacturing process and there is a limit in cost reduction, there is a need for a thin film transistor substrate and a method of manufacturing the same, which further simplify the manufacturing process and further reduce manufacturing costs.

Accordingly, it is an object of the present invention to provide a liquid crystal display device, a manufacturing method and an inspection method which can simplify the substrate structure and the manufacturing process by employing a three mask process.

In order to achieve the above object, a liquid crystal display according to an exemplary embodiment of the present invention includes a gate pattern including a gate electrode of a thin film transistor, a gate line connected to a gate electrode, and a gate pad lower electrode connected to a gate line on a substrate; ; A source / drain pattern including a source electrode and a drain electrode of the thin film transistor, a data line connected to the source electrode, and a data pad lower electrode connected to the data line; A semiconductor pattern formed below the source / drain pattern; A transparent electrode including a pixel electrode connected to the drain electrode, a gate pad upper electrode connected to the gate pad lower electrode and having a line width of 26 μm or more, and a data pad upper electrode connected to the data pad lower electrode and of a line width of 26 μm or more An electrode pattern; And a gate insulating pattern and a protective layer pattern stacked in the remaining regions except for the region in which the transparent electrode pattern is formed.

The data pad upper electrode is in contact with the lower substrate and is in lateral contact with the data pad upper electrode.

And at least one dummy pattern disposed between the data pad upper electrode and the lower substrate.

The dummy pattern is made of the same material as the gate insulating pattern.

And a storage capacitor including a storage electrode overlapping the gate line with the gate line, the gate insulating pattern, and the semiconductor pattern interposed therebetween.

Line widths of the gate pad upper electrode and the data pad upper electrode are about 34 to 38 μm.

A method of manufacturing a liquid crystal display according to the present invention includes forming a gate pattern on a substrate, the gate pattern including a gate electrode of a thin film transistor, a gate line connected to the gate electrode, and a gate pad lower electrode connected to the gate line; Forming a gate insulating film on the substrate on which the gate pattern is formed; A source / drain pattern including a source electrode and a drain electrode of the thin film transistor, a data line connected to the source electrode, and a data pad lower electrode connected to the data line is formed on the gate insulating layer. Forming a semiconductor pattern formed under the pattern; A transparent electrode including a pixel electrode connected to the drain electrode, a gate pad upper electrode connected to the gate pad lower electrode and having a line width of 26 μm or more, and a data pad upper electrode connected to the data pad lower electrode and of a line width of 26 μm or more Forming an electrode pattern and forming a gate insulating pattern and a passivation layer pattern stacked in the remaining regions other than the region where the transparent electrode pattern is formed.

The data pad upper electrode is in contact with the lower substrate and is in lateral contact with the data pad upper electrode.

The method may further include forming at least one dummy pattern disposed between the data pad upper electrode and the lower substrate.

The dummy pattern may be formed of the same material as the gate insulating pattern.

The forming of the dummy pattern may include forming a passivation layer on a substrate on which the data pad lower electrode is formed; Forming a photoresist pattern on the protective film; Patterning a portion of the passivation layer and the gate insulating layer by a dry etching process using the photoresist pattern as a mask and using an etching gas to which O ₂ is added relatively more than SF ₆ ; In addition to using the photoresist pattern as a mask than O ₂ Patterning the data pad lower electrode by a dry etching process using an etching gas to which SF ₆ is further added; Using the photoresist pattern as a mask and patterning the semiconductor pattern by a dry etching process using an etching gas containing Cl ₂ or HCl to retain the small amount of the semiconductor pattern; And patterning the gate insulating film using the photoresist pattern as a mask to leave a small amount of the gate insulating film in a position overlapping the small amount of the semiconductor pattern.

The etching gas used in the protective film pattern is SF ₆ and The ratio of O ₂ is about 1: 3.

The etching gas used to pattern the data pad lower electrode is SF ₆ and The ratio of O ₂ is 3 to 10: 1.

The forming of the transparent electrode pattern, the gate insulation pattern, and the passivation layer pattern may include forming a passivation layer on the substrate on which the source / drain pattern is formed; Forming a photoresist pattern on the protective film; SF ₆ and using the photoresist pattern as a mask Patterning the drain electrode and the semiconductor pattern formed between the passivation layer, the gate insulation layer, the passivation layer and the gate insulation layer by an O ₂ dry etching process, and the gate insulation pattern, the passivation layer pattern, and side surfaces thereof are parallel to the passivation layer and the gate insulation pattern. Forming a; Depositing a transparent electrode material on a substrate on which the photoresist pattern remains; And removing the photoresist pattern and the transparent electrode material thereon to form a transparent electrode pattern by stripping.

And forming a storage capacitor including a storage electrode overlapping the gate line with the gate line, the gate insulation pattern, and the semiconductor pattern interposed therebetween.

Line widths of the gate pad upper electrode and the data pad upper electrode are about 34 to 38 μm.

An inspection method of a liquid crystal display according to the present invention includes a thin film transistor positioned in an area where a data line and a gate line intersect in a matrix shape, a protective film for protecting the thin film transistor, and a boundary between the protective film and the protective film being formed. Forming a thin film transistor array substrate having non-pixel electrodes and transparent conductive patterns formed on respective pad electrode portions; Forming a color filter array substrate corresponding to the thin film transistor array substrate; forming a liquid crystal display device under test by combining the thin film transistor array substrate and the color filter array substrate; Providing an automatic inspection device having a diameter smaller than the width of the transparent electrode formed on the pad electrode portion of the thin film transistor array substrate; The liquid crystal display device to be inspected using the automatic inspection device characterized in that the inspection of the abnormality of the product.

The diameter of the inspection pin of the automatic inspection device is characterized in that 26㎛.

The width of the transparent conductive pattern formed on the pad electrode is characterized in that 26㎛ or more.

The thin film transistor array substrate may be manufactured by three photolithography processes and one lift-off process.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

First, prior to the detailed description of the embodiment of the present invention, a thin film transistor array substrate using the three-mask process proposed in the prior application No. 02-88323 directly related to the present invention and a manufacturing method thereof will be described. .

FIG. 4 is a plan view illustrating a thin film transistor array substrate of a liquid crystal display device proposed in Korean Patent Application No. 02-88323. FIG. 5 is a cross-sectional view of the thin film transistor array substrate illustrated in FIG. 4 taken along a line II-II '. One cross section.

4 and 5 include a gate line 52 and a data line 58 formed on the lower substrate 88 so as to intersect with the gate insulation pattern 90 therebetween, and formed at each intersection thereof. The thin film transistor 80 and the pixel electrode 72 formed in the cell area provided in the cross structure are provided. The thin film transistor array substrate includes a storage capacitor 78 formed at an overlapping portion of the storage electrode 66 connected to the pixel electrode 72 and the front gate line 52, and a gate pad part connected to the gate line 52. And a data pad portion 84 connected to the data line 58.

The thin film transistor 80 includes a gate electrode 54 connected to the gate line 52, a source electrode 60 connected to the data line 58, and a drain electrode 62 connected to the pixel electrode 72. And a semiconductor pattern including an active layer 92 overlapping with the gate electrode 54 and the gate insulating pattern 90 therebetween and forming a channel 70 between the source electrode 60 and the drain electrode 62. do. The thin film transistor 80 allows the pixel voltage signal supplied to the data line 58 to be charged and held in the pixel electrode 72 in response to the gate signal supplied to the gate line 52.

The semiconductor pattern includes a channel portion between the source electrode 60 and the drain electrode 62 and overlaps the source electrode 60, the drain electrode 62, the data line 58, and the data pad lower electrode 64. An active layer 92 is formed to partially overlap the gate line 52 with the gate insulating pattern 90 interposed therebetween, including a portion overlapping the storage electrode 66. The semiconductor pattern is an ohmic contact formed on the active layer 92 for ohmic contact with the source electrode 60, the drain electrode 62, the storage electrode 66, the data line 58, and the data pad lower electrode 64. Further comprises layer 94.

The pixel electrode 72 is connected to the drain electrode 62 of the thin film transistor 80 exposed to the outside of the passivation layer pattern 98. The pixel electrode 72 generates a potential difference with the common electrode formed on the upper substrate (not shown) by the charged pixel voltage. This potential difference causes the liquid crystal located between the thin film transistor substrate and the upper substrate to rotate by dielectric anisotropy, and transmits light incident through the pixel electrode 72 from the light source (not shown) toward the upper substrate.

The storage capacitor 78 overlaps the front gate line 52 with the gate line 52 interposed therebetween with the gate insulating pattern 90, the active layer 92, and the ohmic contact layer 94 interposed therebetween. And a storage electrode 66 connected thereto. The pixel electrode 72 is connected to the storage electrode 66 exposed to the outside of the passivation layer 98. The storage capacitor 78 allows the pixel voltage charged in the pixel electrode 72 to be stably maintained until the next pixel voltage is charged.

The gate line 52 is connected to a gate driver (not shown) through the gate pad portion 82. The gate pad portion 82 includes a gate pad lower electrode 56 extending from the gate line 52 and a gate pad upper electrode 74 connected to the gate pad lower electrode 56.

The data line 58 is connected to a data driver (not shown) through the data pad unit 84. The data pad portion 84 includes a data pad lower electrode 64 extending from the data line 58 and a data pad upper electrode 76 connected to the data pad lower electrode 64. The data pad unit 84 further includes a gate insulation pattern 90, an active layer 92, and an ohmic contact layer 94 formed between the data pad lower electrode 64 and the lower substrate 88.

The gate insulation pattern 90 and the passivation layer pattern 98 are formed in regions where the pixel electrode 72, the gate pad upper electrode 74, and the data pad upper electrode 76 are not formed.

The thin film transistor array substrate having such a configuration is formed by a three mask process. A thin film transistor array substrate manufacturing method according to an embodiment of the present invention using a three mask process includes a first mask process for forming gate patterns, a second mask process for forming semiconductor patterns and source / drain patterns, and gate insulation A third mask process for forming the pattern 90, the passivation layer 98 pattern, and the transparent electrode patterns may be included.

6A through 8D are plan and cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate in accordance with an embodiment of the present invention.

6A and 6B are plan views and cross-sectional views illustrating gate patterns formed on a lower substrate 88 by a first mask process in a method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the present invention.

The gate metal layer is formed on the lower substrate 88 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask to form gate patterns including the gate line 52, the gate electrode 54, and the gate pad lower electrode 56. As the gate metal, Cr, MoW, Cr / Al, Cu, Al (Nd), Mo / Al, Mo / Al (Nd), Cr / Al (Nd) and the like are used in a single layer or a double layer structure.

7A to 7C are plan views and cross-sectional views of a substrate including a source / drain pattern and a semiconductor pattern formed by a second mask process in a method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the present invention.

In detail, the gate insulating layer 90a, the amorphous silicon layer, the n + amorphous silicon layer, and the source / drain metal layer are sequentially formed on the lower substrate 88 on which the gate patterns are formed through a deposition method such as PECVD or sputtering. As the material of the gate insulating layer 90a, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used. Molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy), etc. are used as a source / drain metal.

Subsequently, as shown in FIG. 7B, the photoresist pattern 71b is formed by a photolithography process and an etching process using the second mask. In this case, the photoresist pattern of the channel portion has a lower height than the source / drain pattern portion by using a diffraction exposure mask having a diffraction exposure portion in the channel portion of the thin film transistor as the second mask.

Subsequently, referring to FIG. 7C, the source / drain metal layer is patterned by a wet etching process using the photoresist pattern 71b, so that the data line 58, the source electrode 60, and the drain electrode integrated with the source electrode 60 ( 62), source / drain patterns including the storage electrode 66 and the data pad lower electrode 66 are formed.

Next, the n + amorphous silicon layer and the amorphous silicon layer are simultaneously patterned by a dry etching process using the same photoresist pattern 71b to form the ohmic contact layer 94 and the active layer 92.

Then, the photoresist pattern 71a having a relatively low height in the channel portion is removed by an ashing process, and then the source / drain pattern and the ohmic contact layer 94 of the channel portion are etched by a dry etching process. Accordingly, the active layer 92 of the channel portion is exposed to separate the source electrode 60 and the drain electrode 62.

Subsequently, the photoresist pattern remaining on the source / drain pattern portion is removed by a stripping process.

8A to 8D are plan views and cross-sectional views of a substrate including a gate insulating pattern 90, a passivation layer pattern 98, and a transparent electrode pattern formed by a third mask process in a method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the present disclosure. to be.

Specifically, an inorganic insulating material such as SiNx or SiOx, an acrylic organic compound having a low dielectric constant, an organic insulating material such as BCB or PFCB, or the like may be deposited on the gate insulating film 90a on which the source / drain patterns are formed. A protective film 98a using a material is deposited on the entire surface, and a photoresist is applied on the protective film 98a. Subsequently, as shown in FIG. 8B, a photoresist pattern 71c is formed by a photolithography process using a third mask. Subsequently, the passivation layer 98a and the gate insulating layer 90a are patterned using the photoresist pattern 71c as a mask so that the gate insulation pattern 90 and the passivation layer pattern 98 are formed in the remaining regions except for the region where the transparent electrode pattern remains. Is formed. Subsequently, the transparent electrode material 74a is entirely deposited on the substrate 88 on which the photoresist pattern 71c remains, as shown in FIG. 8C, by a deposition method such as sputtering. Indium tin oxide (ITO), tin oxide (TO), or indium zinc oxide (IZO) is used as the transparent electrode 74a. The photoresist pattern 71c is removed by a strip process using a lift off method on the thin film transistor array substrate on which the transparent electrode material 74a is entirely deposited. At this time, the transparent electrode material 74a deposited on the photoresist pattern 71c is removed while the photoresist pattern 71c is separated, so that the gate pad upper electrode 74 and the pixel electrode 72 are shown in FIG. 8D. And a transparent electrode pattern including the data pad upper electrode 76.

The gate pad upper electrode 74 is connected to the gate pad lower electrode 56, and the pixel electrode 72 is electrically connected to the drain electrode 62 of the thin film transistor and the storage electrode 66 of the storage capacitor 78. The data pad upper electrode 85 is electrically connected to the data pad lower electrode 64.

On the other hand, when the protective film 98 is etched using the photoresist pattern 71c as a mask in the three mask process, the gate insulating film 90, which is the same as or similar to the protective film 98, is overetched, thereby draining as shown in FIG. 9A. Source / drain patterns of the electrode 62, the storage electrode 66, and the like, and an under cut phenomenon under the semiconductor pattern 147 may be generated, thereby causing disconnection A of the pixel electrode 72. To prevent this, the protective layer 98 is etched and the drain electrode 62, the storage electrode 66, and the semiconductor pattern 147 disposed under the photoresist pattern 71c used as a mask for the protection layer 98 are masked. Part of the SF ₆ and By etching by a dry etching process using an etching gas containing O ₂ , disconnection of the pixel electrode 72 is prevented. In the case of etching the source / drain pattern and the semiconductor pattern 147, the data pad lower electrode 64 of the data pad portion 84 and the semiconductor pattern 147 disposed below are also etched, as shown in FIG. 9B. Likewise, the data pad upper electrode 76 is in side contact with the data pad lower electrode 64.

The thin film transistor array substrate is bonded to the color filter array substrate on which the black matrix, the color filter, and the like are formed through the sealant.

As described above, the thin film transistor array substrate and the manufacturing method of the liquid crystal display device according to the present invention can be manufactured by a three mask process using a lift-off method, thereby simplifying the substrate structure and manufacturing process, thereby reducing the manufacturing cost. In addition, the production yield can be improved.

However, in the case of forming the transparent electrode pattern using the lift-off method described above, the inspection pin and the data pad upper electrode 76 (or the gate pad upper electrode 74) The contact of the is not easy, and it is impossible to determine whether the data line 58 (or the gate line 52) is abnormal. In other words, unlike the related art, the data pad upper electrode 76 (or gate upper electrode 74) is not exposed to the outside of the passivation layer 98a as shown in FIG. 10, so that the line width W2 is about 20 to 24 μm. The test pin 80 having a line width W1 that is 26 to 30 μm larger than the upper data pad upper electrode 76 (or the gate pad upper electrode 74) is the data pad upper electrode 76 (or the gate pad). It cannot be connected to the upper electrode 74. As a result, a problem arises in that it is impossible to inspect whether each data line 58 (or gate line 52) is defective.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 11 to 13.

FIG. 11 is a plan view illustrating a thin film transistor array substrate of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 12 is a cross-sectional view of the thin film transistor array substrate of FIG. 11 taken along line III-III ′. .

The thin film transistor array substrate of the liquid crystal display shown in FIGS. 11 and 12 has a gate pad upper electrode 74 and a data pad of pads 82 and 84 as compared to the thin film transistor array substrate shown in FIGS. 4 and 5. The line width of the upper electrode 76 is formed to be relatively wide, and the data pad upper electrode 76 is in side contact with the data pad lower electrode 64 and between the data pad upper electrode 76 and the lower substrate 88. Since the dummy pattern 85 has the same component except that the detailed description thereof will be omitted.

The gate line 52 of the thin film transistor array substrate of the liquid crystal display shown in FIGS. 11 and 12 is connected to a gate driver (not shown) through the gate pad part 82. The gate pad portion 82 includes a gate pad lower electrode 56 extending from the gate line 52 and a gate pad upper electrode 74 connected to the gate pad lower electrode 56. Here, when the line width d2 of the gate pad portion 82 is about 40 to 44 μm, the line width d1 of the gate pad upper electrode 76 in contact with the gate pad lower electrode 74 is 26 μm or more. Preferably it is about 34-38 micrometers.

The data line 58 is connected to a data driver (not shown) through the data pad unit 84. The data pad portion 84 includes a data pad lower electrode 64 extending from the data line 58 and a data pad upper electrode 76 connected to the data pad lower electrode 64. The data pad unit 84 further includes a gate insulation pattern 90, an active layer 192, and an ohmic contact layer 94 formed between the data pad lower electrode 64 and the lower substrate 88. Here, when the line width d2 of the data pad portion 84 is about 40 to 44 μm, the line width d1 of the data pad upper electrode 76 in contact with the data pad lower electrode 64 is 26 μm or more. Preferably it is about 34-38 micrometers.

As described above, the gate pad upper electrode 74 and the data pad upper electrode 76 are formed to have the same relatively wide line width. As a result, an inspection pin having a line width of about 26 μm may be easily contacted with the gate pad upper electrode 74 and the data pad upper electrode 76 during the automatic inspection (A / P) process, thereby providing the gate line 52 and the data line. It is possible to determine whether or not the defect (58) is present.

In addition, as shown in FIG. 9A, a circuit for preventing disconnection A of the pixel electrode 72, which may be caused by an under cut phenomenon due to overetching of the gate insulating layer 90 in the three mask process. When etching a portion of the source / drain pattern and the semiconductor pattern 147, the data pad lower electrode 64 and the semiconductor pattern 147 of the data pad portion 84 are also etched, so that the data pad upper electrode 76 is lower than the data pad. Side contact with the electrode 64 is made. Here, the contact side surface (F) may be formed to be bent, so that the contact area can be somewhat widened.

Here, the position of the photoresist pattern formed by the photolithography process using the three masks is appropriately adjusted, and the etching speeds of the data pad 84 and the semiconductor pattern 147 and the gate insulating layer 90 disposed thereunder are adjusted. By appropriate adjustment, at least one dummy pattern 85 which is part of the gate insulating film 90 is formed between the lower substrate 88 and the data pad upper electrode 76. The dummy pattern 85 may minimize the generation of static electricity in other subsequent processes such as forming the data pad upper electrode 76. In addition, by being located at the corner of the relatively weak data pad portion 84 serves to improve the adhesion between the data pad upper electrode 76 and the lower substrate 88.

The thin film transistor array substrate of the liquid crystal display device having such a configuration is formed by a three mask process. A thin film transistor array substrate manufacturing method according to an embodiment of the present invention using a three mask process includes a first mask process for forming gate patterns, a second mask process for forming semiconductor patterns and source / drain patterns, and gate insulation A third mask process for forming the pattern 90, the passivation layer 98 pattern, and the transparent electrode patterns may be included.

The method of manufacturing the thin film transistor array substrate of the liquid crystal display according to the exemplary embodiment of the present invention is compared with the method of manufacturing the thin film transistor array substrate illustrated in FIGS. 6A to 8D. Line width d1 is relatively wide, and the data pad upper electrode 76 is in lateral contact with the data pad lower electrode 64 and between the data pad upper electrode 76 and the lower substrate 88. Except that the dummy pattern 84 is formed of the same material as the gate insulating material is formed by the same method. Accordingly, detailed description of the same content as the manufacturing method shown in 6a to 7c will be omitted.

8A to 8D are plan views and cross-sectional views of a substrate including a gate insulating pattern 90, a passivation layer pattern 98, and a transparent electrode pattern formed by a third mask process in a method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the present disclosure. to be.

Specifically, an inorganic insulating material such as SiNx or SiOx, an acrylic organic compound having a low dielectric constant, an organic insulating material such as BCB or PFCB, or the like may be deposited on the gate insulating film 90a on which the source / drain patterns are formed. A protective film 198a using a material is deposited on the entire surface, and a photoresist is applied on the protective film 98a. Subsequently, as shown in FIG. 8B, a photoresist pattern 71c is formed by a photolithography process using a third mask. Subsequently, the passivation layer 98a and the gate insulating layer 90a are patterned using the photoresist pattern 71c as a mask so that the gate insulation pattern 90 and the passivation layer pattern 98 are formed in the remaining regions except for the region where the transparent electrode pattern remains. A dummy pattern 85, which is a small amount of gate insulating material that is not removed at the time of patterning the gate insulating film 90, is formed in the data pad part 84.

Hereinafter, a process of forming the photoresist pattern 71c and the dummy pattern 85 will be described in detail with reference to FIGS. 13A to 13D.

First, as shown in FIG. 13A, when the line width d2 of the data pad portion 84 (or the gate pad portion 82) is about 40 to 44 μm, the data pad upper electrode 76 (or the gate pad upper electrode) is shown. The line width d1 of the protective film 98a exposed by the photoresist pattern 71c is also 26 μm or more, so that the line width d1 of (74) is 26 μm or more, preferably about 34 to 38 μm. Preferably, the photoresist pattern 71c is formed to have a thickness of about 34 to 38 μm.

Then, utilizing the photoresist pattern (71c) as a mask, and as well as than SF ₆ The protective film 98a is patterned by a dry etching process using an etching gas to which O ₂ is relatively added. At this time, as shown in FIG. 13B, a small amount of the photoresist pattern 71c is removed to etch a portion D of the gate insulating layer 98a that is the same or similar material as the passivation layer 98a. Where SF ₆ and The ratio of O ₂ is about 1: 3.

Subsequently, as shown in FIG. 9A, a photoresist pattern used in patterning the passivation layer 98a and the gate insulating layer 90a to prevent disconnection A of the pixel electrode 72 due to overetching of the gate insulating layer 90a ( 71c) as a mask and more than O ₂ The data pad lower electrode 64 is etched by a dry etching process using an etching gas that further includes SF ₆ . Where SF ₆ and The ratio of O ₂ is about 3-10: 1.

Subsequently, the semiconductor pattern is etched by a dry etching process using the photoresist pattern 71c as a mask and an etching gas containing Cl ₂ or HCl. At this time, by appropriately adjusting the etching rate, as shown in FIG. 13C, a portion 147a of a small amount of the semiconductor pattern overlapping the corner portion C of the photoresist pattern 171c is left.

Then, utilizing the photoresist pattern (71c) as a mask, and as well as than SF ₆ The gate insulating layer 90 is etched by a dry etching process using an etching gas to which O ₂ is relatively further added. Here, the dummy pattern 85 is formed as shown in FIG. 13D by leaving a small amount of gate insulating film in a region overlapping with the portion 147a of the remaining small amount of semiconductor pattern by adjusting the etching rate.

Subsequently, the transparent electrode material 74a is entirely deposited on the substrate 88 on which the photoresist pattern 71c remains, as shown in FIG. 8C, by a deposition method such as sputtering. Indium tin oxide (ITO), tin oxide (TO), or indium zinc oxide (IZO) is used as the transparent electrode 74a. The photoresist pattern 71c is removed by a strip process using a lift off method on the thin film transistor array substrate on which the transparent electrode material 74a is entirely deposited. At this time, the transparent electrode material 74a deposited on the photoresist pattern 71c is removed together with the photoresist pattern 71c falling off, so that the pixel electrode, 26 μm or more, preferably 34 to 38, as shown in FIG. 8D. A transparent electrode pattern including a gate pad upper electrode 74 and a data pad upper electrode 76 having a line width of about μm is formed.

The gate pad upper electrode 174 is connected to the gate pad upper electrode 76, and the pixel electrode 72 is electrically connected to the drain electrode 62 of the thin film transistor and the storage electrode 66 of the storage capacitor 78. The data pad upper electrode 76 is electrically connected to the side surface of the data pad lower electrode 64. Here, the contact side surface (F) may be formed to be bent, so that the contact area can be somewhat widened.

An inspection method of a liquid crystal display according to an exemplary embodiment of the present invention includes a thin film transistor array substrate, a color filter, a black matrix, and the like, formed by using the above three photolithography processes, an etching hole, and one lift-off process. The contact hole of the gate and the data pads 82 and 84 of the liquid crystal display device bonded by the sealant with the substrate between the liquid crystals is formed larger than the diameter (or line width) of the inspection pin 80 of the automatic inspection device. That is, the inspection pin 80 of the automatic inspection device has a diameter smaller than that of the contact holes of the gate and data pad portions 82 and 84.

Subsequently, the inspection pin 80 of the automatic inspection apparatus is placed on the gate pad upper electrode 74 and the data pad upper electrode 76 formed in the contact hole having a line width relatively larger than the diameter of the inspection pin 80 of the automatic inspection apparatus. Contact. As a result, it is possible to inspect whether the gate line 52 and the data line 58 are defective. Here, the diameter of the test pin 80 is about 26 to 30 μm, and the line widths of the data pad upper electrode 76 and the gate upper electrode 74 formed in the contact hole are at least 26 μm or more, and preferably 34 to 38 μm. It is enough.

As described above, the thin film transistor array substrate and the manufacturing method of the liquid crystal display device according to the embodiment of the present invention are made by a three mask process using a lift-off method to further reduce the manufacturing cost by further simplifying the substrate structure and manufacturing process. In addition to this, the production yield can be improved. In addition, the dummy pattern 85, which is a part of the gate insulating layer 98a, remains between the data pad upper electrode 76 and the lower substrate 88 to minimize the generation of static electricity in other subsequent processes such as forming the data pad upper electrode 76. In addition, the adhesion between the data pad upper electrode 76 and the lower substrate 88 may be improved.

In addition, the inspection method of the liquid crystal display device according to the present invention is the diameter of the inspection pin used in the automatic inspection (A / P) process of the line width of the gate pad upper electrode 74 and the data pad upper electrode 76 of the liquid crystal display device It is formed wider to facilitate contact between the test pins, thereby determining whether the gate line 52 and the data line 58 are defective.

As described above, the thin film transistor array substrate according to the embodiment of the present invention, the manufacturing method and the inspection method thereof are made by the three mask process using the lift-off method, thereby further simplifying the substrate structure and manufacturing process, thereby further increasing the manufacturing cost. In addition to the reduction, the manufacturing yield can be improved, and the dummy pattern, which is part of the gate insulating film, remains between the data pad lower electrode and the lower substrate, thereby minimizing the generation of static electricity in other subsequent processes such as formation of the data pad upper electrode. The adhesion between the data pad upper electrode and the lower substrate can be improved.

In addition, the line widths of the gate pad upper electrode and the data pad upper electrode are formed to be wider than the diameter of the test pin to facilitate contact of the test pin during the automatic inspection (A / P) process, thereby determining whether each signal line is defective.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a plan view showing a portion of a thin film transistor array substrate of a conventional liquid crystal display device.

FIG. 2 is a cross-sectional view of the thin film transistor array substrate of FIG. 1 taken along the line II ′. FIG.

3A to 3D are cross-sectional views sequentially illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 2.

4 is a plan view showing a thin film transistor array substrate of a pre-applied invention having a direct relationship with the present invention.

FIG. 5 is a cross-sectional view of the thin film transistor array substrate of FIG. 4 taken along a line II-II '.

6A through 8D are cross-sectional views illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 5.

9A and 9B are views for explaining a process added in the third mask process illustrated in FIGS. 8A to 8D.

FIG. 10 is a view illustrating non-contact between an inspection pin and an upper electrode of a pad part during an automatic inspection process. FIG.

11 is a plan view illustrating a thin film transistor array substrate according to an exemplary embodiment of the present invention.

FIG. 12 is a cross-sectional view taken along the line III-III ′ of the thin film transistor array substrate of FIG. 11.

13A to 13D are diagrams illustrating in detail the process of forming the dummy pattern illustrated in FIG. 12.

<Explanation of symbols for the main parts of the drawings>

2, 52: gate line 4, 58: data line

6, 80 thin film transistor 8, 54 gate electrode

10, 60: source electrode 12, 62: drain electrode

14, 92: active layer 16: the first contact hole

18, 72: pixel electrodes 20, 78: storage capacitor

22, 66: storage electrode 24: second contact hole

26, 82: gate pad portion 28, 56: gate pad

30: third contact hole 32, 74: gate pad upper electrode

34, 84: data pad portion 38: fourth contact hole

40, 76: data pad upper electrode 42, 88: lower substrate

44 gate insulating film 48, 94 ohmic contact layer

Claims (20)

A gate pattern including a gate electrode of the thin film transistor on the substrate, a gate line to which the gate electrode is connected, and a gate pad lower electrode to which the gate line is connected; A source / drain pattern including a source electrode and a drain electrode of the thin film transistor, a data line connected to the source electrode, and a data pad lower electrode connected to the data line; A semiconductor pattern formed below the source / drain pattern; A transparent electrode including a pixel electrode connected to the drain electrode, a gate pad upper electrode connected to the gate pad lower electrode and having a line width of 26 μm or more, and a data pad upper electrode connected to the data pad lower electrode and of a line width of 26 μm or more An electrode pattern; And a gate insulating pattern and a protective layer pattern stacked in the remaining regions except for the region where the transparent electrode pattern is formed. The method of claim 1, And the upper surface of the data pad is in contact with the lower substrate, and the upper surface of the data pad is in contact with the upper surface of the data pad. The method of claim 1, And at least one dummy pattern disposed between the data pad upper electrode and the lower substrate. The method of claim 3, wherein The dummy pattern is the same material as the gate insulating pattern. The method of claim 1, And a storage capacitor comprising a storage electrode overlapping the gate line with the gate line, the gate insulating pattern, and the semiconductor pattern interposed therebetween. The method of claim 1, And a line width between the gate pad upper electrode and the data pad upper electrode is about 34 to 38 μm. Forming a gate pattern including a gate electrode of the thin film transistor, a gate line connected to the gate electrode, and a gate pad lower electrode connected to the gate line on the substrate; Forming a gate insulating film on the substrate on which the gate pattern is formed; A source / drain pattern including a source electrode and a drain electrode of the thin film transistor, a data line connected to the source electrode, and a data pad lower electrode connected to the data line is formed on the gate insulating layer. Forming a semiconductor pattern formed under the pattern; A transparent electrode including a pixel electrode connected to the drain electrode, a gate pad upper electrode connected to the gate pad lower electrode and having a line width of 26 μm or more, and a data pad upper electrode connected to the data pad lower electrode and of a line width of 26 μm or more Forming an electrode pattern and forming a gate insulating pattern and a protective layer pattern stacked in the remaining regions except for the region where the transparent electrode pattern is formed. The method of claim 7, wherein And the data pad upper electrode is in contact with the lower substrate and is in contact with the data pad upper electrode laterally. The method of claim 7, wherein And forming at least one dummy pattern disposed between the data pad upper electrode and the lower substrate. The method of claim 9, And the dummy pattern is formed of the same material as the gate insulating pattern. The method of claim 9, Forming the dummy pattern Forming a protective film on a substrate on which the data pad lower electrode is formed; Forming a photoresist pattern on the protective film; Patterning a portion of the passivation layer and the gate insulating layer by a dry etching process using the photoresist pattern as a mask and using an etching gas to which O ₂ is added relatively more than SF ₆ ; In addition to using the photoresist pattern as a mask than O ₂ Patterning the data pad lower electrode by a dry etching process using an etching gas to which SF ₆ is further added; Using the photoresist pattern as a mask and patterning the semiconductor pattern by a dry etching process using an etching gas containing Cl ₂ or HCl to retain the small amount of the semiconductor pattern; And patterning the gate insulating film using the photoresist pattern as a mask to leave a small amount of the gate insulating film at a position overlapping with the small amount of the semiconductor pattern. The method of claim 11, The etching gas used in the protective film pattern is SF ₆ and A method of manufacturing a liquid crystal display device, wherein the ratio of O ₂ is about 1: 3. The method of claim 11, The etching gas used to pattern the lower electrode of the data pad is SF₆Wow O₂ The ratio of 3 to 10: 1 manufacturing method of the liquid crystal display device. The method of claim 7, wherein Forming the transparent electrode pattern, the gate insulating pattern and the protective film pattern Forming a protective film on the substrate on which the source / drain pattern is formed; Forming a photoresist pattern on the protective film; SF ₆ and using the photoresist pattern as a mask Patterning the drain electrode and the semiconductor pattern formed between the passivation layer, the gate insulation layer, the passivation layer and the gate insulation layer by an O ₂ dry etching process, and the gate insulation pattern, the passivation layer pattern, and side surfaces thereof are parallel to the passivation layer and the gate insulation pattern. Forming a; Depositing a transparent electrode material on a substrate on which the photoresist pattern remains; And removing the photoresist pattern and the transparent electrode material thereon by a stripping process to form a transparent electrode pattern. The method of claim 7, wherein And forming a storage capacitor including a storage electrode overlapping the gate line with the gate line, the gate insulating pattern, and the semiconductor pattern interposed therebetween. The method of claim 7, wherein The line width of the gate pad upper electrode and the data pad upper electrode is about 34 ~ 38㎛ manufacturing method of the liquid crystal display device. In the method for inspecting the liquid crystal display using an automatic inspection equipment, A thin film transistor positioned at an area where the data line and the gate line intersect in a matrix shape, a passivation layer for protecting the thin film transistor, a pixel electrode bordering the passivation layer, and the passivation layer is not formed, and each pad electrode portion. Forming a thin film transistor array substrate having the formed transparent conductive pattern; Forming a color filter array substrate corresponding to the thin film transistor array substrate; Bonding the thin film transistor array substrate and the color filter array substrate to form a liquid crystal display device under test; Providing an automatic inspection device having a diameter smaller than the width of the transparent electrode formed on the pad electrode portion of the thin film transistor array substrate; And inspecting the liquid crystal display device to be inspected for abnormality of the product using the automatic inspection device. The method of claim 17, The inspection pin of the automatic inspection device has a diameter of 26㎛ the inspection method of the liquid crystal display device. The method of claim 17, The transparent conductive pattern formed on the pad electrode has a width of 26 μm or more. The method of claim 17, And the thin film transistor array substrate is manufactured by three photolithography processes and one lift-off process.