KR20050055357A - Fabrication method of polycrystalline silicon tft - Google Patents

Abstract

A method of manufacturing a polycrystalline silicon thin film transistor according to the present invention includes the steps of forming an amorphous silicon layer on a substrate; Crystallizing and patterning the amorphous silicon layer to form a polycrystalline semiconductor layer; Performing plasma surface treatment on the polycrystalline semiconductor layer; Forming a gate insulating film on the polycrystalline semiconductor layer on which the plasma surface treatment has been performed; H ₂ 0 Performing vapor annealing; H ₂ 0 Forming a gate electrode on the vapor heat-treated gate insulating film; Performing impurity doping on the resultant and forming an LDD region and an n-type impurity layer in the semiconductor layer; Activating and hydrogen doping the LDD region and the n-type impurity layer; Forming an interlayer insulating film on the resultant and forming a source / drain electrode; It includes.

According to the present invention, in performing the plasma surface treatment on the polycrystalline semiconductor layer, the surface treatment is performed using fluorine plasma.

Description

Fabrication method of polycrystalline silicon TFT

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor, and more particularly, to a method for manufacturing a polycrystalline silicon thin film transistor capable of improving device characteristics of a thin film transistor.

Recently, as the information society changes rapidly, there is a need for a flat panel display having excellent characteristics such as thinning, light weight, and low power consumption. Among them, a liquid crystal display having excellent color reproducibility, etc. displays are actively being developed.

As is known, a liquid crystal display is formed by arranging two substrates each having electrodes formed on one side thereof so that the surfaces on which the two electrodes are formed face each other and injecting a liquid crystal material between the two substrates. In addition, the liquid crystal display device is a device for representing an image by changing the transmittance of light by moving the liquid crystal molecules by an electric field generated by applying a voltage to the two electrodes.

The lower substrate of the liquid crystal display device is an array substrate including a thin film transistor for applying a signal to a pixel electrode, and is formed by repeating a process of forming a metal film and an insulating film and then etching the photo. In addition, the upper substrate of the liquid crystal display device is a substrate including a color filter, and the color filter is sequentially arranged three colors of red (R), green (G), blue (B), pigment dispersion method or dyeing method It is produced by a method such as electrodeposition.

In general, amorphous silicon (a-Si: H) is mainly used for semiconductor layers used in thin film transistors of liquid crystal display devices. This is because a large area is easy to manufacture, high productivity, and can be deposited at a low substrate temperature of 350 ° C. or lower, so that an inexpensive insulating substrate can be used.

However, because hydrogenated amorphous silicon has a disordered atomic arrangement, weak Si-Si bonds and dangling bonds exist, and thus, the Si-Si is changed into a quasi-stable state when irradiated with light or applied with an electric field to be used as a thin film transistor device. Stability is a problem.

In particular, the amorphous silicon has a problem of deterioration in characteristics due to light irradiation, and is used as a driving circuit due to electrical characteristics (low field effect mobility: 0.1 to 1.0 cm 2 / V · s) and reliability of the display pixel driving element. The disadvantage is that it is difficult to do.

Furthermore, when the resolution of the liquid crystal panel for a liquid crystal display device is increased, the pad pitch outside the substrate connecting the gate wiring and the data wiring of the thin film transistor substrate with the TCP becomes narrow, which makes the TCP bonding itself difficult.

However, since polycrystalline silicon has a greater field effect mobility than amorphous silicon, a driving circuit can be made on a substrate. If the driving circuit is directly made on the substrate, the IC cost can be reduced and the mounting can be simplified.

In addition, the polycrystalline silicon has a field effect mobility of about 100 times to about 200 times greater than that of the amorphous silicon, so that the response speed is high and the stability to temperature and light is excellent. In addition, there is an advantage that the driving circuit can be formed on the same substrate.

Various methods of manufacturing polycrystalline silicon having the above-mentioned advantages are known. Generally, in order to form polycrystalline silicon, an amorphous material is formed by plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition. A method of depositing silicon and crystallizing it again is widely used.

Hereinafter, an array substrate including a polycrystalline silicon thin film transistor of a general liquid crystal display device and a method of manufacturing a conventional liquid crystal display device will be described with reference to the accompanying drawings.

1A and 1B are cross-sectional views illustrating thin film transistors of a pixel portion and a driving circuit portion of a general liquid crystal display, respectively, in which both the pixel portion and the driving circuit portion are top gate type in which gate electrodes are positioned on a semiconductor layer. It relates to a thin film transistor.

First, in the pixel portion thin film transistor I of FIG. 1A, a buffer layer 114 is formed over an entire surface of an insulating substrate 100, and a semiconductor layer 116 is formed over the buffer layer 114. The gate insulating layer 118 and the gate electrode 120 are stacked on the central portion of the semiconductor layer 116.

An interlayer insulating layer 124 including first and second semiconductor layer contact holes 122a and 122b is formed on the gate electrode 120. In addition, the source electrode 126 and the drain electrode 128, which are connected to the semiconductor layer 116 through the first and second semiconductor layer contact holes 122a and 122b, are formed to be spaced apart from each other by a predetermined interval.

A protective layer 132 including a drain contact hole 130 is formed on the source electrode 126 and the drain electrode 128, and the drain contact hole 130 is formed on the protective layer 132. The pixel electrode 134 connected to the drain electrode 128 is formed.

Meanwhile, in the semiconductor layer 116, a region corresponding to the gate insulating layer 118 forms an activation layer 116a, and a portion of the semiconductor layer 116 contacting the source electrode 126 and the drain electrode 128 is n ⁺ doped n. It is formed of the type impurity layer 116c. A lightly doped drain (LDD) layer 116b is formed at a junction between the source and drain electrodes 126 and 128 and the gate electrode 120 between the activation layer 116a and the n-type impurity layer 116c. This is located.

The LDD layer 116b may be doped to a low concentration to disperse hot carriers, thereby preventing an increase in leakage current and minimizing an on-state current loss.

In FIG. 1B, the CMOS structure thin film transistor of the driving circuit portion is a thin film transistor (II) having a channel by n-type ion doping treatment and a thin film transistor (III) having a channel by p-type ion doping treatment. For convenience of description, the same elements are denoted with the reference numerals in the order of II and III.

As illustrated in FIG. 1B, the n-type semiconductor layer 140 and the p-type semiconductor layer 142 are formed to be spaced apart from each other on the insulating substrate 100 on which the buffer layer 114 is formed. The gate insulating layers 144a and 144b and the gate electrodes 146a and 146b are formed on the n-type and p-type semiconductor layers 140 and 142, respectively. In addition, an interlayer insulating layer 124 including semiconductor layer contact holes 147a, 147b, 147c, and 147d is formed over the entire surface of the gate electrodes 146a and 146b.

The source and drain electrodes 150a and 152a are respectively connected to the n-type and p-type semiconductor layers 140 and 142 through the semiconductor layer contact holes 147a, 147b, 147c, and 147d on the interlayer insulating layer 124, respectively. And 150b and 152b, and a protective layer 132 is formed over the entire surface of the source and drain electrodes 150a and 152a and 150b and 152b.

The n-type semiconductor layer 140 contacts the source and drain electrodes 150a and 152a with the active layer 140a having a region in contact with the gate insulating layer 144a as in the semiconductor layer 116 of FIG. 1A. The n-type impurity layer 140c is included, and the region therebetween is composed of the LDD layer 140b.

Hereinafter, a manufacturing process of a conventional liquid crystal display device including the thin film transistor of the pixel portion and the CMOS structure thin film transistor of the driving circuit portion will be described.

FIG. 2 is a flowchart illustrating a manufacturing process of a conventional liquid crystal display device having a top gate polycrystalline silicon thin film transistor according to FIGS. 1A and 1B. In this manufacturing process, a photoresist is used. A photolithography process (hereinafter abbreviated as mask process) is involved.

First, an insulating substrate is prepared, and a buffer layer is formed on the insulating substrate (S100). As the material of the buffer layer, an inorganic insulating film such as a silicon nitride film (SiN _X ) or a silicon oxide film (SiO _X ) is mainly used.

In operation S110, a semiconductor layer is formed on the buffer layer.

In this step, an amorphous silicon (a-Si) layer is deposited to a thickness of about 550 상 에 on the substrate on which the buffer layer is formed, and subjected to dehydrogenation. Here, crystalline silicon, such as polycrystalline or monocrystalline silicon, is formed through a crystallization step, and the crystalline silicon layer is used to form a semiconductor layer by a first mask process.

Thereafter, a gate insulating film and a gate electrode are formed (S120).

In more detail, a gate insulating film is formed by depositing about 1000 GPa of silicon oxide film (SiO ₂ ) on a substrate on which the semiconductor layer is formed. After depositing a metal such as molybdenum (Mo) on the gate insulating layer, a gate electrode is formed through a second mask process.

In addition, an n-type semiconductor layer is completed. An LDD layer is formed by performing n ⁻ doping on a substrate on which the gate electrode and the gate insulating layer are formed, and then n ⁺ doped n-type impurity layer is formed through a third mask process. It forms (S130). Subsequently, p ⁺ doped p-type impurity layers are formed on the substrate on which the n-type impurity layer is formed through a fourth mask process (S140).

Thereafter, an interlayer insulating film is formed. An inorganic insulating film, such as a silicon nitride film or a silicon oxide film, is deposited on the resultant, and an interlayer insulating film having a semiconductor layer contact hole is formed by a fifth mask process (S150).

Subsequently, about 500 kW of molybdenum and about 3000 kW of aluminum neodium (AlNd) are sequentially deposited on the substrate on which the interlayer insulating film is formed, and then collectively etched by the sixth mask process, through the semiconductor layer contact hole. Source and drain electrodes connected to the impurity layer are formed (S160).

On the substrate on which the source and drain electrodes are formed, a silicon nitride film of about 4000 kV is deposited to form a protective layer, and a hydrogenation heat treatment process is performed (S170). Here, the hydrogenation heat treatment process is generally performed once using nitrogen (N ₂ ) gas at 380 ° C.

Thereafter, a drain contact hole is formed in the passivation layer through a seventh mask process, and finally, a pixel electrode is formed on the passivation layer (S180). In this step, after depositing about 500 kW of Indium Tin Oxide (ITO) on the substrate on which the protective layer is formed, a pixel electrode connected to the drain electrode through the drain contact hole is formed by an eighth mask process.

Meanwhile, in manufacturing a liquid crystal display device through a series of processes as described above, in the structure of the low temperature polycrystalline silicon thin film transistor, the interface characteristics between the polycrystalline silicon layer and the gate insulating film affect the device characteristics.

In the manufacturing process of such a liquid crystal display device, grain boundaries exist in the polycrystalline silicon, unlike single crystal silicon, and many defects exist in the grain boundaries. In addition, since it is a low temperature process using glass as a substrate, a silicon oxide film (SiO ₂ ) is grown as a gate insulating film on the polycrystalline silicon layer using plasma chemical vapor deposition equipment (PECVD).

At this time, a considerable number of Si dangling bonds (> 10 ¹⁸ / cm ³ ) that do not bond with oxygen exist at the interface between the polycrystalline silicon layer and the gate insulating film. In addition, these defects serve as scattering centers that hinder the movement of carriers and cause initial characteristics of the thin film transistor. In addition, there is a problem that the characteristics of the thin film transistor element is deteriorated by the stress (stress) generated therefrom.

An object of the present invention is to provide a polycrystalline silicon thin film transistor manufacturing method that can improve the device characteristics of the thin film transistor in manufacturing a polycrystalline silicon thin film transistor.

In order to achieve the above object, a polycrystalline silicon thin film transistor manufacturing method according to the present invention comprises the steps of forming an amorphous silicon layer on a substrate; Crystallizing and patterning the amorphous silicon layer to form a polycrystalline semiconductor layer; Performing plasma surface treatment on the polycrystalline semiconductor layer; Forming a gate insulating film on the polycrystalline semiconductor layer on which the plasma surface treatment has been performed; H ₂ 0 Performing vapor annealing; H ₂ 0 Forming a gate electrode on the vapor heat-treated gate insulating film; Performing impurity doping on the resultant and forming an LDD region and an n-type impurity layer in the semiconductor layer; Activating and hydrogen doping the LDD region and the n-type impurity layer; Forming an interlayer insulating film on the resultant and forming a source / drain electrode; Its features are to include.

In addition, another example of the polycrystalline silicon thin film transistor manufacturing method according to the present invention for achieving the above object comprises the steps of forming an amorphous silicon layer on a substrate; Crystallizing and patterning the amorphous silicon layer to form a polycrystalline semiconductor layer; Performing a plasma surface treatment on the polycrystalline semiconductor layer and forming a gate insulating film on the polycrystalline semiconductor layer on which the plasma surface treatment has been performed; Forming a gate electrode on the gate insulating film; Performing impurity doping on the resultant and forming an LDD region and an n-type impurity layer in the semiconductor layer; Activating and hydrogen doping the LDD region and the n-type impurity layer; Forming an interlayer insulating film on the resultant and forming a source / drain electrode; Its features are to include.

According to the present invention, in manufacturing a polycrystalline silicon thin film transistor, there is an advantage that can improve the device characteristics of the thin film transistor.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a flowchart illustrating a process of manufacturing a liquid crystal display device having a general top gate type polycrystalline silicon thin film transistor shown in FIGS. 1A and 1B according to the method of manufacturing a polycrystalline silicon thin film transistor according to the present invention. As is known, such a manufacturing process involves a photolithography process using photosensitive photo resist (PR).

First, an insulating substrate (for example, glass) is prepared, and a buffer layer is formed on the insulating substrate (S300). As the material of the buffer layer, an inorganic insulating film such as a silicon nitride film (SiN _X ) or a silicon oxide film (SiO _X ) is mainly used.

In operation S310, an amorphous silicon layer is formed on the buffer layer, and crystallization and patterning are performed on the formed amorphous silicon layer to form a polycrystalline silicon semiconductor layer (S310). In this step, an amorphous silicon (a-Si) layer is deposited to a thickness of about 550 상 에 on the substrate on which the buffer layer is formed, and subjected to dehydrogenation. Then, crystalline silicon such as polycrystalline or monocrystalline silicon is formed through a crystallization step, and the crystalline silicon layer is used to form a semiconductor layer by a first mask process.

In this case, a method of forming a polycrystalline silicon layer using the amorphous silicon layer includes a laser annealing method of growing an amorphous silicon layer by applying an excimer laser while heating the substrate temperature to about 250 ° C., and a metal on the amorphous silicon layer. Metal induced crystallization (MIC) method of depositing a metal to form polycrystalline silicon as a seed, and solid phase crystallization (SPC) method of forming amorphous silicon by heat treatment for a long time at high temperature.

Thereafter, plasma surface treatment is performed on the polycrystalline silicon semiconductor layer (S320). Here, the plasma surface treatment is performed by using a fluorine plasma (fluorine plasma) to generate a fluorine plasma using a gas containing NF ₃ , SF ₆ in the plasma chemical vapor deposition equipment (PECVD).

By such a fluorine plasma surface treatment, it is possible to reduce defects that hinder the movement of the carrier through the combination of the dangling bond and fluorine ions present in the grain boundary of the polycrystalline silicon semiconductor layer. 4 is a view for explaining a fluorine plasma treatment process in the manufacturing process of the liquid crystal display device with a top gate type polycrystalline silicon thin film transistor according to the present invention.

That is, in the present invention, as shown in FIG. 4, the polycrystalline silicon layer 403 is subjected to surface treatment using fluorine plasma on the polycrystalline silicon layer 403 formed in the buffer layer 402 on the substrate 401. It is possible to reduce the defect formed. At this time, since the polycrystalline silicon semiconductor layer may be etched by fluorine plasma, the surface treatment conditions should be appropriately set. Here, one example of the fluorine plasma treatment process conditions according to the present invention may be carried out at 350mT or more, 1000W or less, 30sec or less.

In operation S330, a gate insulating layer is formed on the polycrystalline silicon semiconductor layer on which the plasma surface treatment is performed. In more detail, as an example, a gate insulating film is formed by depositing about 1000 GPa of silicon oxide film (SiO ₂ ) on a substrate on which the polycrystalline silicon semiconductor layer is formed.

Then, for the resultant, as shown in FIG. 5, H ₂ 0 Vapor annealing is performed (S340). 5 is a view for explaining a heat treatment process using H ₂ O vapor in the manufacturing process of the liquid crystal display device with a top gate type polycrystalline silicon thin film transistor according to the present invention. Here, reference numeral 505 denotes a gate insulating film.

As such, H ₂ 0 When heat treatment is performed in a furnace using a vapor, it is possible to reduce defects of dangling bonds present at the interface due to the combination of oxygen and silicon by H ₂ O decomposition. . At this time, as the temperature of the heat treatment is increased, the reaction between silicon and oxygen is activated to form an oxide film having a strong bond on the surface. However, when glass is used as a substrate, the heat treatment is performed at a temperature of 500 ° C. or less. do.

Subsequently, the H ₂ 0 A gate electrode is formed on the gate heat-treated gate insulating film (S350). As an example, after depositing 2000 μmol of molybdenum (Mo), a gate electrode may be formed through a second mask process.

Then, to complete the n-type semiconductor layer, n ^- doping treatment to form an LDD layer on the substrate on which the gate electrode is formed, and then n ⁺ doped n-type impurity layer is formed through a third mask process ( S360). Subsequently, p ⁺ doped p-type impurity layers are formed on the substrate on which the n-type impurity layer is formed through a fourth mask process (S370).

Thereafter, an interlayer insulating film is formed. An inorganic insulating film such as a silicon nitride film or a silicon oxide film of about 7000 kV is deposited on the resultant, and an interlayer insulating film having a semiconductor layer contact hole is formed by a fifth mask process (S380).

Subsequently, about 500 kW of molybdenum and about 3000 kW of aluminum neodium (AlNd) are sequentially deposited on the substrate on which the interlayer insulating film is formed, and then collectively etched by the sixth mask process, through the semiconductor layer contact hole. Source and drain electrodes connected to the impurity layer are formed (S390).

Then, on the substrate on which the source and drain electrodes are formed, a silicon nitride film of about 4000 kV is deposited to form a protective layer, and a hydrogenation heat treatment process is performed (S400). Here, the hydrogenation heat treatment process is generally performed once using nitrogen (N ₂ ) gas at 380 ° C.

Thereafter, a drain contact hole is formed in the passivation layer through a seventh mask process, and finally, a pixel electrode is formed on the passivation layer (S410). In this step, after depositing about 500 kW of Indium Tin Oxide (ITO) on the substrate on which the protective layer is formed, a pixel electrode connected to the drain electrode through the drain contact hole is formed by an eighth mask process.

According to the method of manufacturing a polycrystalline silicon thin film transistor according to the present invention, as described above, through the surface treatment using fluorine plasma and the heat treatment using H ₂ O steam, the grain boundary defects and the dangling bonds are reduced Through this, it is possible to improve the characteristics of the thin film transistor element.

6 is a flowchart illustrating a process of manufacturing a liquid crystal display device having a general top gate type polycrystalline silicon thin film transistor shown in FIGS. 1A and 1B according to another embodiment of the method of manufacturing a polycrystalline silicon thin film transistor according to the present invention. will be. In the following description of each process, the same manufacturing process as described with reference to FIG. 3 will be briefly described.

First, an insulating substrate (for example, glass) is prepared, and a buffer layer is formed on the insulating substrate (S600). In operation S610, an amorphous silicon layer is formed on the buffer layer, and a polycrystalline silicon semiconductor layer is formed by performing crystallization and patterning on the formed amorphous silicon layer (S610).

Thereafter, a plasma surface treatment is performed on the polycrystalline silicon semiconductor layer, and a gate insulating film is formed on the polycrystalline silicon semiconductor layer on which the plasma surface treatment is performed in an in-situ process (S620).

In this case, the plasma surface treatment is performed by using a nitrogen plasma to generate a nitrogen plasma using a gas containing N ₂ O in a plasma chemical vapor deposition equipment (PECVD). By such nitrogen plasma surface treatment, defects that hinder the movement of the carrier can be reduced through the combination of dangling bonds and nitrogen ions present in the grain boundary of the polycrystalline silicon semiconductor layer. FIG. 7 is a view for explaining a nitrogen plasma treatment process in a manufacturing process of a liquid crystal display device having a top gate type polycrystalline silicon thin film transistor according to the present invention.

That is, in the present invention, as shown in FIG. 7, the surface treatment using nitrogen plasma is performed on the polycrystalline silicon layer 703 formed in the buffer layer 702 on the substrate 701 to thereby apply the surface to the polycrystalline silicon layer 703. It is possible to reduce the defect formed. FIG. 7 is a view for explaining a nitrogen plasma treatment process in another embodiment of a manufacturing process of a liquid crystal display device having a top gate type polycrystalline silicon thin film transistor according to the present invention.

In the chamber in which the nitrogen plasma surface treatment has been performed, a process of forming a gate insulating film on the polycrystalline silicon semiconductor layer on which the plasma surface treatment has been performed is continuously performed in an in-situ process. In this case, as an example, a gate insulating layer may be formed by depositing a silicon oxide layer (SiO ₂ ) of about 1000 GPa on the substrate on which the polycrystalline silicon semiconductor layer is formed.

As such, by continuously performing the nitrogen plasma surface treatment process and the deposition process for the gate insulating film in the same chamber without a 'vacuum break', the single film characteristics of the silicon oxide film can be compensated for, and nitrogen (N) and silicon ( By the combination of Si), it is possible to reduce defects of dangling bonds existing at the interface.

Subsequently, a gate electrode is formed on the gate insulating film (S630). As an example, after depositing 2000 μmol of molybdenum (Mo), a gate electrode may be formed through a second mask process.

Then, to complete the n-type semiconductor layer, n ^- doping treatment to form an LDD layer on the substrate on which the gate electrode is formed, and then n ⁺ doped n-type impurity layer is formed through a third mask process ( S640). Subsequently, a p ⁺ doped p-type impurity layer is formed on the substrate on which the n-type impurity layer is formed through a fourth mask process (S650).

Thereafter, an interlayer insulating film is formed. An inorganic insulating film such as a silicon nitride film or a silicon oxide film of about 7000 kV is deposited on the resultant, and an interlayer insulating film having a semiconductor layer contact hole is formed by a fifth mask process (S660).

Subsequently, about 500 kW of molybdenum and about 3000 kW of aluminum neodium (AlNd) are sequentially deposited on the substrate on which the interlayer insulating film is formed, and then collectively etched by the sixth mask process, through the semiconductor layer contact hole. Source and drain electrodes connected to the impurity layer are formed (S670).

On the substrate on which the source and drain electrodes are formed, a silicon nitride film of about 4000 kV is deposited to form a protective layer, and a hydrogenation heat treatment process is performed (S680). Thereafter, a drain contact hole is formed in the passivation layer through a seventh mask process, and finally, a pixel electrode is formed on the passivation layer (S690).

According to another embodiment of the method of manufacturing a polycrystalline silicon thin film transistor according to the present invention, as described above, the interface without further processing through the reduction of defects such as grain boundaries by nitrogen plasma and the continuous gate insulating film deposition in the same chamber It is possible to improve the characteristics.

As described above, according to the method of manufacturing a polycrystalline silicon thin film transistor according to the present invention, in manufacturing a polycrystalline silicon thin film transistor, there is an advantage of improving the device characteristics of the thin film transistor.

1A and 1B are cross-sectional views respectively showing cross-sections of a top gate polycrystalline silicon thin film transistor of a pixel portion and a driving circuit portion of a general liquid crystal display device.

2 is a process flowchart showing a manufacturing process of a liquid crystal display device having a conventional top gate type polycrystalline silicon thin film transistor.

3 is a process flowchart illustrating a manufacturing process of a liquid crystal display device having a top gate type polycrystalline silicon thin film transistor according to the present invention;

4 is a view for explaining a fluorine plasma treatment process in the manufacturing process of the liquid crystal display device with a top gate type polycrystalline silicon thin film transistor according to the present invention.

5 is a view for explaining a heat treatment process using H ₂ O vapor in the manufacturing process of the liquid crystal display device with a top gate type polycrystalline silicon thin film transistor according to the present invention.

6 is a process flow diagram illustrating another embodiment of a manufacturing process of a liquid crystal display device having a top gate type polycrystalline silicon thin film transistor according to the present invention;

7 is a view for explaining a nitrogen plasma processing process in another embodiment of the manufacturing process of a liquid crystal display device having a top gate type polycrystalline silicon thin film transistor according to the present invention.

<Explanation of symbols for the main parts of the drawings>

401, 701 ... substrate 402, 702 ... buffer layer

403, 703 ... polycrystalline silicon layer 505 ... gate insulating film

Claims (10)

Forming an amorphous silicon layer on the substrate; Crystallizing and patterning the amorphous silicon layer to form a polycrystalline semiconductor layer; Performing plasma surface treatment on the polycrystalline semiconductor layer; Forming a gate insulating film on the polycrystalline semiconductor layer on which the plasma surface treatment has been performed; H ₂ 0 Performing vapor annealing; H ₂ 0 Forming a gate electrode on the vapor heat-treated gate insulating film; Performing impurity doping on the resultant and forming an LDD region and an n-type impurity layer in the semiconductor layer; Activating and hydrogen doping the LDD region and the n-type impurity layer; And Forming an interlayer insulating film on the resultant and forming a source / drain electrode; Polycrystalline silicon thin film transistor manufacturing method comprising a. The method of claim 1, In the plasma surface treatment of the polycrystalline semiconductor layer, a surface treatment using a fluorine plasma (fluorine plasma) characterized in that the polycrystalline silicon thin film transistor manufacturing method. The method of claim 2, In the generation of the fluorine plasma, plasma chemical vapor deposition equipment (PECVD) using a gas containing NF ₃ , SF ₆ to produce a fluorine plasma, characterized in that the polycrystalline silicon thin film transistor manufacturing method. The method of claim 1, The gate insulating film is a silicon oxide film (SiO ₂ ) characterized in that the polycrystalline silicon thin film transistor manufacturing method. The method of claim 1, H ₂ 0 In performing a vapor annealing, the method of manufacturing a polycrystalline silicon thin film transistor, characterized in that the heat treatment at a temperature of 500 ℃ or less. Forming an amorphous silicon layer on the substrate; Crystallizing and patterning the amorphous silicon layer to form a polycrystalline semiconductor layer; Performing a plasma surface treatment on the polycrystalline semiconductor layer and forming a gate insulating film on the polycrystalline semiconductor layer on which the plasma surface treatment has been performed; Forming a gate electrode on the gate insulating film; Performing impurity doping on the resultant and forming an LDD region and an n-type impurity layer in the semiconductor layer; Activating and hydrogen doping the LDD region and the n-type impurity layer; And Forming an interlayer insulating film on the resultant and forming a source / drain electrode; Polycrystalline silicon thin film transistor manufacturing method comprising a. The method of claim 6, A plasma surface treatment process performed on the polycrystalline semiconductor layer and a process of forming a gate insulating film on the polycrystalline semiconductor layer on which the plasma surface treatment is performed are sequentially performed in the same chamber. . The method of claim 6, In the plasma surface treatment of the polycrystalline semiconductor layer, the surface treatment using a nitrogen plasma is characterized in that the polycrystalline silicon thin film transistor manufacturing method. The method of claim 8, In the generation of the nitrogen plasma, plasma chemical vapor deposition equipment (PECVD) using a gas containing N ₂ O to produce a nitrogen plasma, characterized in that the polycrystalline silicon thin film transistor manufacturing method. The method of claim 6, The gate insulating film is a silicon oxide film (SiO ₂ ) characterized in that the polycrystalline silicon thin film transistor manufacturing method.