KR20050053245A - Method of manufacturing semiconductor device - Google Patents

Abstract

The present invention discloses a method for manufacturing a semiconductor device. Disclosed is a semiconductor substrate comprising a semiconductor substrate having a predetermined underlayer including a contact plug for a capacitor; Forming a first interlayer insulating film made of an oxide film on the underlayer; Forming a bit line on the first interlayer insulating film; Forming a spacer nitride film on the first interlayer insulating film including the bit line; Selectively oxidizing spacer nitride layer portions formed on the bit line and on the first interlayer dielectric layer by performing a preheating process using O 2 and He gas in the HDP CVD process chamber on the substrate resultant; Forming a second interlayer insulating film made of an oxide film on the substrate resultant according to an HDP CVD process; And etching the second interlayer insulating film, the oxidized nitride film portion, and the first interlayer insulating film to form a contact hole exposing a contact plug for a capacitor. According to the present invention, only an oxide layer is formed in a region for forming a storage node contact by performing a preheating process using O ₂ and He gas in a HDP CVD process chamber to selectively oxidize spacer nitride layer portions to a substrate resultant. Therefore, the spacer nitride front surface etching process may not be performed, and the storage node contact etching process may be stabilized.

Description

Manufacturing method of semiconductor device {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of simplifying the process.

In forming the capacitor, the pattern formation area is reduced due to the high integration of the semiconductor device, whereas, as the step height is increased, difficulty in contact between the storage node and the substrate is caused.

In order to solve the process difficulties due to the high step, that is, to secure a contact margin between the storage node and the substrate, a technique for forming a storage node contact (Storage Node Contact) before the formation of the storage node has also become popular. It is a well known fact.

In order to form such a storage node contact, a spacer nitride layer is conventionally formed after the transistor and the bit line are formed to insulate the etching barrier and the storage note contact poly plug. Next, a full surface etching process is performed on the spacer nitride layer to remove the spacer nitride layer in the lower region of the bit line space. Here, the reason for removing the spacer nitride film is that when the storage note contact is formed after the interlayer insulating film is formed in a subsequent process, the oxide film (interlayer insulating film), the spacer nitride film and the oxide film (interlayer insulating film) are formed in the area where the contact is opened. Since the laminate structure is formed, the etching process is increased and the nitride film is difficult to remove.

In addition, when the process is performed in the above manner, the number of process steps increases, such as a bit line etching process, a spacer nitride film deposition process, a spacer nitride front surface etching process, and an interlayer dielectric film deposition process.

Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device, which can be obtained to solve the conventional problems as described above, and to simplify the process of forming a storage node contact.

The present invention for achieving the above object, the step of providing a semiconductor substrate having a predetermined base layer including a contact plug for a capacitor; Forming a first interlayer insulating film made of an oxide film on the underlayer; Forming a bit line on the first interlayer insulating film; Forming a spacer nitride film on the first interlayer insulating film including the bit line; Selectively oxidizing spacer nitride layer portions formed on the bit line and on the first interlayer dielectric layer by performing a preheating process using O 2 and He gas in the HDP CVD process chamber on the substrate resultant; Forming a second interlayer insulating film made of an oxide film on the substrate resultant according to an HDP CVD process; And etching the second interlayer insulating film, the oxidized nitride film portion, and the first interlayer insulating film to form a contact hole exposing a contact plug for a capacitor.

Here, the preheating step is performed with a bias power of 1000 to 2500W for selective oxidation of the spacer nitride film while the flow rate of O2 gas is 100 to 300sccm, the He gas is 100 to 450sccm.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1D are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 1A, a first interlayer insulating film 15 made of an oxide film is formed on a silicon substrate 1 on which a predetermined base layer including a capacitor contact plug is formed, thereby performing a chemical mechanical polish (CMP) process. . Here, reference numeral 3 is a gate oxide film, 5 is a gate electrode, 7 is a hard mask film, 9 is a spacer, 11 is a BPSG film, and 13 is a landing plug poly.

Subsequently, a bit line 17 is formed on the first interlayer insulating layer 15 by a known method of forming a hard mask nitride layer and a tungsten and titanium / titanium nitride layer, which is a bit line conductive material, and etching the bit line 17. The spacer nitride film 19 is formed on the first interlayer insulating film 15 including the?

As shown in FIG. 1B, a preheating process using O ₂ and He gas is performed in the HDP CVD process chamber on the resultant of the substrate 1 to form an upper portion of the bit line 17 and the first interlayer dielectric layer ( The portions of the spacer nitride film 19 formed on the layer 15 are selectively oxidized. Here, the preheating process is carried out with a bias power of 1000 to 2500W for selective oxidation of the spacer nitride film while the flow rate of the O ₂ gas is 100 to 300scmm, the He gas is 100 to 450scmm.

As shown in FIG. 1C, after the preheating process is performed on the resultant of the substrate 1, the spacer nitride film 19 except for the spacer nitride film 19 formed on the sidewall of the bit line 17 is formed of the oxide film 19a. )

As shown in FIG. 1D, a second interlayer insulating film 21 made of an oxide film is formed on the substrate 1 by the HDP CVD process. Next, the second interlayer insulating film 21, the oxidized nitride film portion, and the first interlayer insulating film 15 are etched to form a contact hole 23 exposing a capacitor contact plug.

As described above, since only the oxide layer is formed in the region for forming the storage node contact by performing a preheating process using O ₂ and He gas in the HDP CVD process chamber to selectively oxidize the spacer nitride layer portions to the substrate resultant. It is not necessary to perform the spacer nitride film entire surface etching process, and the storage node contact etching process may be stabilized.

In the above, the present invention has been described with reference to some examples, but the present invention is not limited thereto, and a person of ordinary skill in the art may make many modifications and variations without departing from the spirit of the present invention. I will understand.

As described above, according to the present invention, since the spacer nitride film is formed after the bit line is formed and the spacer nitride film existing in the space region between the bit lines is selectively oxidized through the oxidation process, the spacer nitride film etching process does not need to be performed. As a result, the storage node contact etching process may be stabilized and the reliability of the semiconductor device may be improved.

1A to 1D are cross-sectional views illustrating processes for manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

1 silicon substrate 3 gate oxide film

5 gate electrode 7 hard mask film

9 spacer 11 BPSG film

13: landing plug poly 15: first interlayer insulating film

17: bit line 19: spacer nitride film

21: second interlayer insulating film 23: contact hole

Claims (2)

Providing a semiconductor substrate having a predetermined underlayer including a contact plug for a capacitor; Forming a first interlayer insulating film made of an oxide film on the underlayer; Forming a bit line on the first interlayer insulating film; Forming a spacer nitride film on the first interlayer insulating film including the bit line; Oxidizing the spacer nitride layer portions formed on the bit line and on the first interlayer dielectric layer by performing a preheating process using O 2 and He gas in the HDP CVD process chamber on the substrate resultant; Forming a second interlayer insulating film made of an oxide film on the substrate resultant according to an HDP CVD process; And And etching the second interlayer insulating film, the oxidized nitride film portion, and the first interlayer insulating film to form a contact hole exposing a contact plug for a capacitor. The method of claim 1, wherein the preheating process A method of manufacturing a semiconductor device, characterized in that the bias power is set at 1000 to 2500 W for selective oxidation of a spacer nitride film while the flow rate of O 2 gas is 100 to 300 sccm, and the He gas is 100 to 450 sccm.