KR20050046926A - Thin film transistor array panel - Google Patents

Abstract

     The thin film transistor array panel according to the present invention includes a plurality of storage electrodes electrically connecting neighboring storage electrode lines with branches of an insulating substrate, a plurality of gate lines formed on the insulating substrate, a storage electrode line formed on the insulating substrate, and a storage electrode line; A pixel electrode comprising a plurality of data lines insulated from and intersecting with the gate line, a plurality of thin film transistors connected to the gate lines and the data lines, a protective film covering the thin film transistors, and a pixel electrode formed on the protective film and connected to the thin film transistors. The portion of the edge of the overlapping portion with the sustain electrode or data line has a zigzag or uneven cut surface that is not parallel to the sustain electrode or data line.

Description

     Thin film transistor array panel

     The present invention relates to a thin film transistor array panel, and more particularly, to a thin film transistor array panel for a liquid crystal display device.

     In general, a liquid crystal display device injects a liquid crystal material between an upper display panel on which a common electrode, a color filter, and the like are formed, and a lower display panel on which a thin film transistor and a pixel electrode are formed. By applying a different potential to form an electric field to change the arrangement of the liquid crystal molecules, and through this to control the light transmittance is a device that represents the image.

     In each pixel of the liquid crystal display, a storage capacitor is formed to continuously maintain the liquid crystal capacitance formed between the common electrode and the pixel electrode for a predetermined time. For this purpose, each pixel includes a storage electrode overlapping the pixel electrode. This is arranged.

     However, such a liquid crystal display device has a disadvantage that a narrow viewing angle is important. To overcome these shortcomings, various methods for widening the viewing angle have been developed. In one method, an ultra-high-aperture ratio structure is formed to form the pixel electrode as wide as possible, but in such a high-aperture ratio structure, the data line and the sustain electrode are disposed between the pixel electrodes of adjacent pixels. These are arranged at close distances, and a lateral field is strongly formed between them. Therefore, the liquid crystals positioned at the edges of the pixel electrode are distorted by the lateral electric field, and the alignment direction of the liquid crystal molecules positioned at the edges of the pixel electrode is distorted. As a result, light leakage occurs to form disclination.

     This disclination is more severe in the normally white mode in which a dark state is applied by applying a voltage to the common electrode and the pixel electrode, such as a twisted namatic method, because the voltage difference between the pixel electrode and the data line is very large. As the data signal transmitted through the data line is changed in units of several tens of microseconds, the data signal is diffused to the inside of the pixel and serves as a main cause of deterioration of display characteristics of the liquid crystal display.

     In order to solve this problem, a black matrix for blocking light leaking between pixels is disposed on the upper display panel to block light leakage between pixels, but when the width of the black matrix is designed to be wide, the aperture ratio of the pixel is reduced. And the luminance decreases.

     The present invention for solving the above problems is to provide a thin film transistor array panel that can minimize the influence of the lateral electric field.

     In the present invention for achieving the above object, a thin film transistor array panel has a concave-convex structure at the edge of the pixel electrode, or a conductor having a floating between the pixel electrode and the data line.

     Specifically, it is insulated from the plurality of gate electrodes formed on the insulating substrate, the plurality of gate lines formed on the insulating substrate, the plurality of sustain electrodes and gate lines electrically connecting the adjacent sustain electrode lines to the branches of the sustain electrode lines and the sustain electrode lines. A plurality of thin film transistors connected to a plurality of intersecting data lines, gate lines, and data lines, a passivation layer covering the thin film transistors, a pixel electrode formed on the passivation layer, and connected to the thin film transistors; The portion overlapping the sustain electrode or data line has a zigzag or uneven cut surface not parallel to the sustain electrode or data line.

     The semiconductor device may further include a voltage inducing conductor disposed between neighboring gate lines and spaced apart from the gate line and overlapping an edge of the pixel electrode.

     At this time, it is preferable that the edge of the pixel electrode overlapping the conductor for voltage induction is formed in a straight line.

     The thin film transistor may include a gate electrode formed in a portion or a branch of a gate line, a semiconductor layer overlapping a portion of the gate electrode, a source electrode formed in a portion or a branch of the data line, and at least partially overlapping the semiconductor layer. And a drain electrode overlapping at least a portion thereof and facing the source electrode with respect to the gate electrode.

     The semiconductor device may further include an ohmic contact layer formed between the semiconductor layer and the source electrode and the drain electrode.

     At this time, except for a predetermined region of the semiconductor layer, the data line and the drain electrode preferably have the same planar pattern as the semiconductor layer.

     Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

     In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is said to be "on top" of another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is 'just above' another part, there is no other part in the middle.

     Next, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to the drawings.

     1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II′-II ″ of FIG. 1.

     1 and 2, a thin film transistor array panel according to an exemplary embodiment of the present invention may include a plurality of gate lines 121 and a plurality of storage electrode lines 131 on an insulating substrate 110. Is formed.

     The gate line 121 transmits a gate signal, and a part of each gate line 121 forms a gate electrode 124 of the thin film transistor. The gate electrode 124 is deformed into various shapes to form a gate line. It may also be a protrusion (not shown) of 121.

     The storage electrode lines 131a and 131b are formed in the pixel region defined by the gate line 121 and the data line 171 described later, and are formed above and below the pixel region adjacent to the gate line 121.

     The storage electrode lines 131a and 131b mainly extend in parallel with the gate line 121, and they are electrically connected by the storage electrode 133. The storage electrode 133 is formed on the left and right sides of the pixel area adjacent to the data line 171.

     The storage electrode lines 131a and 131b and the storage electrode 133 receive a predetermined voltage such as a common voltage applied to a common electrode (not shown) of another display panel (not shown). . Since the storage electrode lines 131a and 131b and the storage electrode 133 are electrically connected to each other, a uniform storage capacitor may be formed over the entire thin film transistor array panel even when a predetermined region is disconnected.

     The gate line 121 and the storage electrode lines 131a and 131b may include a conductive film made of an aluminum-based metal such as silver (Ag), silver alloy, aluminum (Al), or aluminum alloy, and other materials in addition to the conductive film. In particular, chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo) and their alloys have good physical, chemical and electrical contact properties with indium tin oxide (ITO) or indium zinc oxide (IZO). : Molybdenum-tungsten (MoW) alloy] can be formed into a multilayer film structure including another conductive film. An example of the combination of the lower layer and the upper layer is chromium / aluminum-neodymium (AlNd) alloy.

     A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the 121, 131a and 131b.

     A plurality of linear semiconductor layers 151 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating layer 140. The linear semiconductor layer 151 mainly extends in the longitudinal direction and has a plurality of extensions 154 extending therefrom to the gate electrode 124.

     The linear semiconductor layer 151 has a portion that is not covered between the source electrode 173 and the drain electrode 175, which will be described later, and the width of the linear semiconductor layer 151 is smaller than the width of the data line 171.

     On top of the semiconductor layers 151 and 154 a plurality of linear and island ohmic contacts 161 and 165 made of a material such as n + hydrogenated amorphous silicon doped with a high concentration of silicide or n-type impurities. Is formed. The linear ohmic contact layer 161 has a plurality of protrusions 163, and the protrusion 163 and the island contact layer 165 are paired and positioned on the protrusion 154 of the semiconductor layer 151.

     The ohmic contacts 161 and 165 exist only between the semiconductor layers 151 and 154 below the data line 171 and the drain electrode 175 thereon, and serve to lower the contact resistance therebetween. The ohmic contacts 161 and 165 have the same planar pattern as the semiconductor layer 151 except for a predetermined region of the semiconductor layer 151. The predetermined region of the semiconductor layer 154 is a channel portion that forms a channel of the thin film transistor.

     The semiconductor layer 151 may increase in width at the portion where the semiconductor layer 151 meets the gate line 121 to enhance insulation between the gate line 121 and the data line 171 (not shown). The portion of the linear semiconductor layer 151 under the data line 171 may not be formed according to the parasitic capacitance between the semiconductor layer 151 and the data line 171.

     Sidewalls of the semiconductor layers 151 and 154 and the ohmic contacts 161 and 165 are formed to be tapered so that the layers formed thereon can be tightly adhered to each other.

     A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the ohmic contacts 161 and 165 and the gate insulating layer 140, respectively.

     The data line 171 is formed on the linear ohmic contact layer 161 and mainly extends in the vertical direction to cross the gate line 121 and transmit a data voltage. The drain electrode 175 is formed on the island resistive contact layer 165.

     A plurality of branches extending from the data line 171 toward the drain electrode 175 forms a source electrode 173. The pair of source electrode 173 and the drain electrode 175 are separated from each other and positioned opposite to the gate electrode 124. The gate electrode 124, the source electrode 173, and the drain electrode 175 form a thin film transistor (TFT) together with the protrusion 154 of the semiconductor layer 151, and the channel of the thin film transistor The protrusion 154 is formed between the source electrode 173 and the drain electrode 175.

     One end of the data line 171 may be wider than the width of the data line 171 to receive a signal transmitted from a data driving circuit (not shown). A portion of the drain electrode 175 connected to the pixel electrode 190 overlaps the storage electrode line 131.

     In this case, the data line 171 and the drain electrode 175 may also include a conductive film made of a silver-based metal or an aluminum-based metal, and in addition to the conductive film, chromium (Cr), titanium (Ti), and tantalum (Ta). ), Molybdenum (Mo), and an alloy such as an alloy may be formed in a multi-layered film structure including.

     The passivation layer 180 is formed on the substrate to cover the data line 171, the drain electrode 175, and the exposed semiconductor layer 154.

     The passivation layer 180 is a-Si: C: O, a-Si: O: F, which is formed of an organic material having excellent planarization characteristics and photosensitivity, and plasma enhanced chemical vapor deposition (PECVD). Low dielectric constant insulating materials such as silicon nitride or inorganic materials.

     The passivation layer 180 may be formed of a low dielectric constant organic material having a dielectric constant of 4.0 or less. In this case, the thickness of the passivation layer 180 is thicker than that of the inorganic material, and thus the pixel electrode 190 and the data line 171 are formed. Since the coupling phenomenon does not occur, the edge of the pixel electrode 190, which will be described later, may overlap the data line 171 to maximize the aperture ratio of the pixel.

     In the passivation layer 180, a plurality of contact holes 182 exposing an end portion of the data line 171 and a plurality of contact holes 185 exposing the drain electrode 175 are formed.

     A plurality of pixel electrodes 190 and a plurality of contact assistants 82 formed of indium tin oxide (ITO) or indium zinc oxide (IZO) are formed on the passivation layer 180.

     The pixel electrode 190 is physically and electrically connected to the drain electrode 175 through the contact hole 185 to receive a data voltage from the drain electrode 175. The pixel electrode 190 to which the data voltage is applied rearranges the liquid crystal molecules between the two electrodes by generating an electric field together with a common electrode (not shown) of another display panel.

     Here, the pixel electrode 190 includes a zigzag or uneven structure and includes a boundary line that is not parallel to the data line and overlaps the storage electrode 133. As the boundary of the pixel electrode 190 has a zigzag shape, an electric field formed between the pixel electrode 190 and the data line 171 is formed at an arbitrary angle with respect to the data line to minimize the occurrence of disclination. Can be.

     That is, even if the disclination is bound to the zigzag end and the data voltage is greatly changed, the disclination does not diffuse to the inside of the pixel. Therefore, since the width of the black matrix of the upper panel facing the thin film transistor array panel is not required to be wide to cover the disclination, the aperture ratio of the pixel increases.

     When the passivation layer 180 is formed of a low dielectric constant organic material, the aperture ratio may be increased by partially overlapping the pixel electrode 190 with the neighboring gate line 121 and the data line 171.

     The contact auxiliary member 82 is connected to one end of the data line 171 through the contact hole 182. When the end portion of the gate line 121 also has a structure for connecting with the driving circuit like the end portion of the data line 171, a gate contact auxiliary member is formed on the passivation layer 180.

     The contact assisting member 82 is to compensate for adhesion to the outside, and is particularly necessary when the contact auxiliary member 82 is mounted on the substrate 110 or a fusible circuit board (not shown) in the form of a chip. If it is made of a thin film transistor or the like directly above, it is not formed.

     Finally, an alignment layer 11 is formed on the pixel electrode 190 and the passivation layer 180. The alignment layer 11 is subjected to a rubbing process for determining the horizontal direction of the liquid crystal molecules.

     Second Embodiment

     3 is a layout view of a thin film transistor array panel according to a second exemplary embodiment of the present invention.

    As shown, most of the structures are the same as in FIGS. 1 and 2. However, unlike the first exemplary embodiment, the thin film transistor array panel according to the second exemplary embodiment includes a conductor for inducing voltage 128, and the conductor for inducing voltage 128 is disposed at the edge of the pixel and thus the pixel electrode. It overlaps with the edge of 190 and a part is exposed outside the boundary line of the pixel electrode.

     In this case, the voltage inducing conductor 128 is positioned between the neighboring gate lines 121 and is separated from the gate line 121 and is floating.

     In this case, an arbitrary voltage is induced in the voltage inducing conductor 128 in accordance with the voltage applied to the pixel electrode 190. Any voltage induced in the voltage inducing conductor 128 satisfies [Equation 1].

V _pixel-com : Voltage between pixel electrode and sustain electrode

C _fbm-pixel : Capacitance between voltage-inducing conductor and pixel electrode

C _pixel-com : capacitance between pixel electrode and sustain electrode

V _fbm-com : Voltage between the voltage inducing conductor and the sustain electrode (voltage applied to the voltage inducing conductor)

That is, according to Equation 1, any voltage induced in the voltage inducing conductor 128 is always less than 1 and depends on the pixel electrode 190. And by adjusting C _fbm-pixel , we can adjust the ratio of C _fbm-com to V _pixel-com . C _fbm-pixel can be adjusted by adjusting their overlapping area and distance, leading to little difference between V _fbm-com and V _pixel-com .

     Therefore, since the potential difference does not occur around the edge of the pixel electrode 190, the liquid crystal alignment located at this portion may be disturbed and distorted, thereby minimizing light leakage at the edge of the pixel, thereby reducing display. The occurrence of cleavage can be minimized. Figure 4a is a simulation picture according to the conventional light leakage generation, Figure 4b is a simulation picture according to the light leakage generation according to the present invention.

     As shown in Figure 4b, it can be seen that the left edge of the light leakage is moved to the right than in the prior art, the area of light leakage is reduced as a whole. Therefore, the width of the black matrix can be reduced, and the aperture ratio of the pixel can be improved to provide a high brightness thin film transistor array panel.

     [Examples 3 and 4]

     The thin film transistor array panel according to the above embodiment may be manufactured by a photolithography process using each thin film as a photoresist pattern as an etching mask, and the thin film transistor array panel may be completed through a manufacturing method according to another embodiment. In this case, the thin film transistor array panel has a structure different from the above embodiment, which will be described in detail with reference to the accompanying drawings.

     5 is a layout view of a thin film transistor array panel according to a third exemplary embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along line VI-VI′-VI ″ of FIG. 5.

     As shown in Figs. 5 and 6, most single layer structures are the same as Figs. That is, the gate line 121 and the storage electrode lines 131a and 131b are formed on the insulating substrate 110. The gate insulating layer 140 is formed to cover the gate line 121 and the storage electrode lines 131a and 131b, and the semiconductor layer 151 and the ohmic contact layers 161 and 165 are formed on the gate insulating layer 140. The data line 175 and the drain electrode 175 are formed on the ohmic contacts 161 and 165, and the passivation layer 180 is formed to cover the 171 and 175 and the passivation layer 180. The pixel electrode 190 connected to the drain electrode 175 is formed thereon.

     However, the data line 171 and the drain electrode 175 have the same planar pattern as the ohmic contacts 161 and 165, and the semiconductor layer 151 has a channel portion between the source electrode 173 and the drain electrode 175. It has the same planar pattern as the ohmic contacts 161 and 165 except that it is connected.

     7, the semiconductor layer 151, the data line 171, and the drain electrode 175 may be formed in a predetermined region in the thin film transistor array panel having the voltage inductive conductor 128, as in the third embodiment. Except for it may be formed to have the same planar pattern.

     7 is a layout view of a thin film transistor array panel according to a fourth exemplary embodiment of the present invention.

     The single layer structure of the fourth embodiment is the same as that of the third embodiment, and further includes a conductor for voltage induction 128.

     In addition, the thin film transistor array panel of the first to fourth embodiments may include a color filter (not shown). That is, the color filter may be formed above the data line or below the pixel electrode.

     Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

     As described above, when the pixel electrode as in the present invention is formed, the electric field between the data lines can be weakened to minimize the occurrence of the disclination.

     In addition, the generation of the disclination is minimized by the voltage induced in the conductor, thereby providing a high quality thin film transistor array panel.

     1 is a layout view of a thin film transistor array panel according to a first exemplary embodiment of the present invention.

     FIG. 2 is a cross-sectional view taken along the line II-II'-II "of FIG. 1,

     3 is a layout view of a thin film transistor array panel according to a second exemplary embodiment of the present invention.

     Figure 4a is a simulation picture according to the conventional light leakage generation,

     Figure 4b is a simulation picture according to the generation of light leakage in accordance with the present invention,

     5 is a layout view of a thin film transistor array panel according to a third exemplary embodiment of the present invention.

     FIG. 6 is a cross-sectional view taken along the line VI-VI′-VI ″ of FIG. 5;

     7 is a layout view of a thin film transistor array panel according to a fourth exemplary embodiment of the present invention.

            ※ Code explanation about main part of drawing ※

     110: insulated substrate 121: gate line

     128: conductor for voltage induction

     131: sustain electrode line 151: semiconductor layer

     171: data line 175: drain electrode

     190: pixel electrode

Claims (6)

     Insulation board,      A plurality of gate lines formed on the insulating substrate,      A plurality of sustain electrodes electrically connecting the sustain electrode lines formed on the insulating substrate and the sustain electrode lines adjacent to the branches of the sustain electrode lines;      A plurality of data lines insulated from and intersecting the gate lines;      A plurality of thin film transistors connected to the gate lines and the data lines, respectively;      A protective film covering the thin film transistor,      A pixel electrode formed on the passivation layer and connected to the thin film transistor;      The portion of the edge of the pixel electrode overlapping the sustain electrode or the data line has a zigzag or uneven cut surface that is not parallel to the sustain electrode or the data line.      In claim 1,      The thin film transistor array panel of claim 1, further comprising a voltage inducing conductor positioned between the gate lines adjacent to each other and spaced apart from the gate line and overlapping an edge of the pixel electrode.      In claim 2,      The thin film transistor array panel of which the edge of the pixel electrode overlapping the voltage inducing conductor is formed in a straight line.      The method of claim 1 or 2,      The thin film transistor may include a gate electrode formed in a portion or branch form of the gate line,      A semiconductor layer partially overlapping the gate electrode;      A source electrode formed in a part or branch of the data line and overlapping at least a part of the semiconductor layer;      And a drain electrode at least partially overlapping the semiconductor layer and facing the source electrode with respect to the gate electrode.      In claim 4,      And a resistive contact layer formed between the semiconductor layer and the source electrode and the drain electrode.      In claim 5,      The thin film transistor array panel having the same planar pattern as the semiconductor layer except for the predetermined region of the semiconductor layer.