KR20050042685A - Method for fabricating field oxide isolation of semiconductor devices - Google Patents
Method for fabricating field oxide isolation of semiconductor devices Download PDFInfo
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- KR20050042685A KR20050042685A KR1020030077735A KR20030077735A KR20050042685A KR 20050042685 A KR20050042685 A KR 20050042685A KR 1020030077735 A KR1020030077735 A KR 1020030077735A KR 20030077735 A KR20030077735 A KR 20030077735A KR 20050042685 A KR20050042685 A KR 20050042685A
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000002955 isolation Methods 0.000 title claims abstract description 12
- 150000004767 nitrides Chemical class 0.000 claims abstract description 34
- 238000005530 etching Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000002245 particle Substances 0.000 claims abstract description 14
- 230000003647 oxidation Effects 0.000 claims abstract description 7
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 3
- 238000001039 wet etching Methods 0.000 claims description 5
- 230000007547 defect Effects 0.000 abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052710 silicon Inorganic materials 0.000 abstract description 12
- 239000010703 silicon Substances 0.000 abstract description 12
- 230000015572 biosynthetic process Effects 0.000 abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 239000013078 crystal Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 210000003323 beak Anatomy 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001000 micrograph Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
본 발명은 반도체 소자의 필드산화막 형성방법에 관한 것으로, 보다 자세하게는 LOCOS(Local Oxidation of Silicon) 공정에 있어서 모우트(moat) 형성시 질화막 제거 후 발생한 파티클(particle)을 필드산화막 형성 전에 에칭을 통하여 제거함으로써 후속공정에서 유발될 수 있는 결함을 방지하는 방법에 관한 것이다.The present invention relates to a method for forming a field oxide film of a semiconductor device, and more particularly, to form particles formed after removal of a nitride film during the formation of a moat in a local oxide of silicon (LOCOS) process through etching before forming a field oxide film. The present invention relates to a method for removing defects which may be caused in a subsequent process by removing them.
본 발명의 반도체 소자의 필드산화막 형성방법은 반도체 기판 상부에 패드 산화막과 질화막을 증착하는 단계; 상기 질화막을 선택적 식각하여 소자분리영역이 오픈되도록 질화막 패턴을 형성하는 단계; 상기 질화막 패턴을 식각 마스크로 상기 패드 산화막을 식각하여 기판을 노출시키는 단계; 상기 노출된 기판에 열산화공정을 실시하여 필드산화막을 형성하는 단계; 및 상기 질화막 패턴을 제거하는 단계를 포함하여 이루어짐에 기술적 특징이 있다.The field oxide film forming method of the semiconductor device of the present invention comprises the steps of depositing a pad oxide film and a nitride film on the semiconductor substrate; Selectively etching the nitride film to form a nitride film pattern to open an isolation region; Etching the pad oxide layer using the nitride layer pattern as an etch mask to expose a substrate; Performing a thermal oxidation process on the exposed substrate to form a field oxide film; And removing the nitride film pattern.
따라서, 본 발명의 반도체 소자의 필드산화막 형성방법은 모우트 형성시 질화막 제거 후 발생한 파티클을 필드산화막 형성 전에 에칭을 통하여 제거함으로써, 상기 파티클에 의해 생성된 홈이 후속공정 진행시 결함으로 작용하는 것을 방지하는 효과가 있다. 더 자세하게는 상기의 홈에 의해 필드산화막 상부에 브릿지가 형성되거나 액티브 영역과의 경계면에 형성되어 누설전류의 원인이 되는 결함을 방지하는 효과가 있다.Therefore, in the method of forming a field oxide film of the semiconductor device of the present invention, the particles generated after the removal of the nitride film during the formation of the mould are removed by etching before the field oxide film is formed, so that the grooves formed by the particles act as defects during the subsequent process. It is effective to prevent. In more detail, a bridge is formed on the field oxide film by the groove, or formed on the interface with the active region, thereby preventing a defect that causes leakage current.
Description
본 발명은 반도체 소자의 필드산화막 형성방법에 관한 것으로, 보다 자세하게는 LOCOS(Local Oxidation of Silicon, 이하 LOCOS라 칭함) 공정에 있어서 모우트(moat) 형성시 질화막 제거 후 발생한 파티클(particle)을 필드산화막 형성 전에 에칭을 통하여 제거함으로써 후속공정에서 유발될 수 있는 결함을 방지하는 방법에 관한 것이다.The present invention relates to a method for forming a field oxide film of a semiconductor device, and more particularly, to a field oxide film in which particles generated after removal of a nitride film during moat formation in a LOCOS process are referred to as LOCOS (LOCOS) process. The present invention relates to a method for preventing defects which may be caused in a subsequent process by removing through etching before forming.
일반적으로 반도체 장치의 제조에 널리 이용되는 LOCOS 방법은 측면산화에 의한 버즈비크(Bird's beak) 현상, 열공정으로 유발되는 버퍼층 응력에 의한 기판 실리콘의 결정 결함 및 채널 저지를 위해 이온 주입된 불순물의 재분포 등의 문제로 반도체 장치의 전기적 특성 향상 및 고접적화 추세에 난점이 되고 있다. 상기 LOCOS 방법의 문제점을 개선하기 위하여 제안된 트렌치를 이용한 소자 분리 방법은, 필드 산화막의 형성에 있어서 상기 LOCOS류와 같이 열산화 공정에 의하지 않으므로, 열산화 공정으로 인해 유발되는 상기 LOCOS류의 단점들을 어느 정도 줄일 수 있다. 그러나, 우수한 소자 분리 특성을 확보하기 위하여 기판에 일정 깊이 이상으로 트렌치를 형성하는 과정에서 기판 실리콘에 결정결함이 유발되며, 트렌치에 절연 물질을 갭필(gap-fill)할 경우 넓은 트렌치 패턴에서는 갭필된 절연 물질의 프로파일(profile)이 불균일하여 불안정한 소자 분리 특성 및 일부의 구조적인 단차를 유발하는 또 다른 문제점을 내포하고 있다. 또한, LOCOS 방식은, 통상 3,000Å 이상의 두께로 필드 산화필을 열성장시키게 되는데, 반도체 기판에 선택적으로 덮여 있는 질화막 하부에 있어서 활성 영역의 경계면 부근에 응력에 의한 결정결함이 발생되어 소자와 소자 사이의 누설전류를 증가시킨다.In general, LOCOS method which is widely used in the manufacture of semiconductor device is a phenomenon of Buzz's beak caused by lateral oxidation, crystal defect of substrate silicon caused by buffer layer stress caused by thermal process, Problems such as distribution have made it difficult to improve the electrical characteristics and high integration of semiconductor devices. The device isolation method using the trench proposed to improve the problem of the LOCOS method is not formed by the thermal oxidation process like the LOCOS in the formation of the field oxide film, and thus the disadvantages of the LOCOS type caused by the thermal oxidation process are eliminated. It can be reduced to some extent. However, in order to secure excellent device isolation characteristics, crystal defects occur in the substrate silicon during trenches formed at a predetermined depth or more, and when gap-filling an insulating material in the trenches, gap gaps are formed in a wide trench pattern. Non-uniform profiles of insulating materials present another problem that leads to unstable device isolation characteristics and some structural steps. In addition, in the LOCOS method, the field oxide is thermally grown to a thickness of 3,000 kPa or more. In the lower part of the nitride film selectively covered with the semiconductor substrate, crystal defects due to stress are generated near the interface between the device and the device. Increase the leakage current.
종래에는, 트랜치 형성에 있어서 실리콘 웨이퍼에 패드 산화막을 증착한 후, 그 위에 다시 질화막을 증착하고, 소자분리영역을 오픈시키기 위하여 사진식각(Photolithography)공정을 통해 포토레지스트(Photoresist)와 질화막을 제거한다. 그러나 상기와 같은 종래의 기술은 질화막 에칭시 발생한 파티클이 상기 질화막 하부의 패드 산화막 표면에 잔존함으로써 필드산화막 형성시 결함의 소스(source)로 작용하여 움푹 패인 형상의 홈(pit)을 만들어 낼 수 있다. 도 1에는 상기의 홈을 보여주는 주사전자현미경(SEM) 사진을 보여주고 있다. 이러한 홈은 후속 게이트 형성 공정에서 폴리실리콘이 채워지게 되어 필드산화막 상부에 브릿지(bridge)를 형성할 수 있으며, 또한 필드영역과 활성(active) 영역의 경계면에 형성될 경우에는 누설전류의 원인이 되기도 한다.Conventionally, in forming a trench, a pad oxide film is deposited on a silicon wafer, a nitride film is then deposited on the silicon wafer, and a photoresist and a nitride film are removed through a photolithography process to open the device isolation region. . However, in the conventional technique as described above, particles generated during etching of the nitride film remain on the surface of the pad oxide film under the nitride film, thereby acting as a source of defects when forming the field oxide film, thereby creating a recessed pit. . Figure 1 shows a scanning electron microscope (SEM) picture showing the groove. These grooves may be filled with polysilicon in a subsequent gate forming process to form a bridge over the field oxide layer, and may also cause leakage current when formed at the interface between the field region and the active region. do.
따라서, 본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 잔존 파티클을 제거하기 위한 패드 산화막 에칭 단계를 추가하여 후속공정시 발생할 수 있는 결함을 방지하는 방법을 제공함에 본 발명의 목적이 있다. Accordingly, an object of the present invention is to solve the problems of the prior art as described above, and to provide a method for preventing a defect that may occur in a subsequent process by adding a pad oxide film etching step for removing residual particles. have.
본 발명의 상기 목적은 반도체 기판 상부에 패드 산화막과 질화막을 증착하는 단계; 상기 질화막을 선택적 식각하여 소자분리영역이 오픈되도록 질화막 패턴을 형성하는 단계; 상기 질화막 패턴을 식각 마스크로 상기 패드 산화막을 식각하여 기판을 노출시키는 단계; 상기 노출된 기판에 열산화공정을 실시하여 필드산화막을 형성하는 단계; 및 상기 질화막 패턴을 제거하는 단계로 이루어진 반도체 소자의 필드산화막 형성방법에 의해 달성된다.The above object of the present invention comprises the steps of depositing a pad oxide film and a nitride film on the semiconductor substrate; Selectively etching the nitride film to form a nitride film pattern to open an isolation region; Etching the pad oxide layer using the nitride layer pattern as an etch mask to expose a substrate; Performing a thermal oxidation process on the exposed substrate to form a field oxide film; And a field oxide film forming method of a semiconductor device comprising the step of removing the nitride film pattern.
본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설명에 의해 보다 명확하게 이해될 것이다.Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.
도 2a 내지 도 2e는 본 발명에 의한 반도체 소자의 필드산화막 제조방법을 단계별로 나타내는 도면들이다.2A to 2E are diagrams illustrating step-by-step methods of manufacturing a field oxide film of a semiconductor device according to the present invention.
먼저 도 2a는 실리콘 기판(20) 상부에 포토레지스트 패턴(23)을 형성하는 방법을 설명하기 위한 단면도이다. 반도체 기판 상부에 약 100 내지 200 Å 두께의 패드 산화막(21)과 약 1500 내지 2000 Å 두께의 질화막(22)을 순차적으로 적층한다. 이후 실리콘 기판을 필드영역과 활성영역으로 분리하기 위한 소자분리영역을 정의하기 위해 포토레지스트에 대한 선택적인 사진식각공정을 진행한다. 상기 사진식각공정에 의하여 식각 마스크로 작용하는 포토레지스트 패턴이 형성된다. 이 때, 포토레지스트 패턴이 제거된 부분을 통하여 필드영역의 실리콘 기판 상부에 형성된 질화막이 노출된다.2A is a cross-sectional view for describing a method of forming the photoresist pattern 23 on the silicon substrate 20. A pad oxide film 21 having a thickness of about 100 to 200 microseconds and a nitride film 22 having a thickness of about 1500 to 2000 microseconds are sequentially stacked on the semiconductor substrate. Thereafter, a selective photolithography process is performed on the photoresist to define an isolation region for separating the silicon substrate into the field region and the active region. By the photolithography process, a photoresist pattern serving as an etching mask is formed. At this time, the nitride film formed on the silicon substrate in the field region is exposed through the portion where the photoresist pattern is removed.
다음, 도 2b는 소자분리영역을 오픈시키기 위한 방법을 설명하기 위한 단면도이다. 상기 포토레지스트 패턴을 식각마스크로 하여 오픈된 질화막을 식각하면 패드 산화막이 노출된다. 이 때 공정이 진행되면서 패드 산화막 표면 상부에 식각된 질화막의 파티클(24)이 떨어지게 된다. 이러한 파티클은 필드산화막 형성시 결함의 소스로 작용하여 움푹 패인 형상의 홈을 만들어 낼 수 있다. 이러한 홈은 후속 게이트 형성공정에서 폴리실리콘이 채워지게 되어 필드산화막 상부에 브릿지를 형성할 수 있으며, 또한 필드영역과 활성영역의 경계면에 형성될 경우에는 누설전류의 원인이 되기도 한다.Next, FIG. 2B is a cross-sectional view for describing a method for opening a device isolation region. The pad oxide layer is exposed by etching the opened nitride layer using the photoresist pattern as an etching mask. At this time, as the process proceeds, particles 24 of the nitride film etched on the pad oxide film surface are dropped. These particles can serve as a source of defects when forming the field oxide film to form grooves having a recessed shape. Such a groove may be filled with polysilicon in a subsequent gate forming process to form a bridge over the field oxide layer, and may also cause leakage current when formed at the interface between the field region and the active region.
다음, 도 2c는 패드 산화막을 습식식각한 결과를 보여주는 단면도이다. 먼저 포토레지스트 패턴을 제거한다. 그 후 상기 질화막 파티클을 제거하기 위해 질화막 패턴을 식각 마스크로 패드 산화막을 습식식각하면 식각용액에 의한 파티클의 계면 이탈과 부유화 유동에 의해 패드 산화막과 함께 잔존 파티클도 동시에 제거된다. Next, FIG. 2C is a cross-sectional view illustrating a result of wet etching a pad oxide layer. First, the photoresist pattern is removed. Thereafter, when the pad oxide layer is wet-etched using the nitride layer pattern as an etch mask to remove the nitride layer particles, the remaining particles are also simultaneously removed along with the pad oxide layer due to the surface separation and floating of the particles by the etching solution.
다음, 도 2d는 필드산화막(25)을 형성하는 방법을 설명하기 위한 단면도이다. 상기 패드 산화막의 식각에 의해 노출된 실리콘 기판과 포토레지스트 패턴에 의해 제거되지 않은 질화막 전면에 열산화 공정을 실시하여 필드산화막을 형성한다. 상기 산화막은 고온의 퍼니스(furnace)에 유입된 산소와 산소와 접촉하는 실리콘 표면이 반응하여 형성된다. 이 때, 산화막 형성이 시작되기 전의 실리콘 표면을 기준으로 상, 하 양방향으로 산화막의 성장이 진행된다. 한편, 활성영역을 덮고 있는 질화막의 상부에는 산화막이 성장하지 않는다. 다만, 산화막은 노출된 실리콘 기판 영역에만 성장되어 필드산화막을 형성한다.Next, FIG. 2D is a cross-sectional view for explaining a method of forming the field oxide film 25. A field oxide film is formed by performing a thermal oxidation process on the entire surface of the silicon substrate exposed by etching the pad oxide film and the entire surface of the nitride film not removed by the photoresist pattern. The oxide film is formed by reaction of oxygen introduced into a furnace at a high temperature with a silicon surface in contact with oxygen. At this time, the oxide film grows in both up and down directions based on the silicon surface before the oxide film formation begins. On the other hand, the oxide film does not grow on the nitride film covering the active region. However, the oxide film is grown only in the exposed silicon substrate region to form a field oxide film.
다음, 도 2e는 최종 소자 분리막이 완성된 결과를 보여주기 위한 단면도이다. 상기 필드산화막을 형성하기 위해 마스크로 사용하였던 질화막 패턴을 습식식각으로 제거하면 소자 분리막 형성이 완성된다.Next, FIG. 2E is a cross-sectional view illustrating a result of completing a final device isolation layer. When the nitride film pattern used as a mask to form the field oxide film is removed by wet etching, the device isolation layer formation is completed.
상세히 설명된 본 발명에 의하여 본 발명의 특징부를 포함하는 변화들 및 변형들이 당해 기술 분야에서 숙련된 보통의 사람들에게 명백히 쉬워질 것임이 자명하다. 본 발명의 그러한 변형들의 범위는 본 발명의 특징부를 포함하는 당해 기술 분야에 숙련된 통상의 지식을 가진 자들의 범위 내에 있으며, 그러한 변형들은 본 발명의 청구항의 범위 내에 있는 것으로 간주된다.It will be apparent that changes and modifications incorporating features of the invention will be readily apparent to those skilled in the art by the invention described in detail. It is intended that the scope of such modifications of the invention be within the scope of those of ordinary skill in the art including the features of the invention, and such modifications are considered to be within the scope of the claims of the invention.
따라서, 본 발명의 반도체 소자의 필드산화막 형성방법은 모우트 형성시 질화막 제거 후 발생한 파티클을 필드산화막 형성 전에 에칭을 통하여 제거함으로써, 상기 파티클에 의해 생성된 홈이 후속공정 진행시 결함으로 작용하는 것을 방지하는 효과가 있다. 더 자세하게는 상기의 홈에 의해 필드산화막 상부에 브릿지가 형성되거나 액티브 영역과의 경계면에 형성되어 누설전류의 원인이 되는 결함을 방지하는 효과가 있다. Therefore, in the method of forming a field oxide film of the semiconductor device of the present invention, the particles generated after the removal of the nitride film during the formation of the mould are removed by etching before the field oxide film is formed, so that the grooves formed by the particles act as defects during the subsequent process. It is effective to prevent. In more detail, a bridge is formed on the field oxide film by the groove, or formed on the interface with the active region, thereby preventing a defect that causes leakage current.
도 1은 종래기술에 의해 형성된 반도체 소자의 결함을 보여주는 현미경 사진.1 is a micrograph showing a defect of a semiconductor device formed by the prior art.
도 2a 내지 도 2e는 본 발명에 의한 반도체 소자의 필드산화막 형성방법의 공정 단면도.2A to 2E are cross-sectional views of a method of forming a field oxide film of a semiconductor device according to the present invention.
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| KR100649872B1 (en) * | 2005-12-29 | 2006-11-27 | 동부일렉트로닉스 주식회사 | Method of fabricating the trench isolation layer in semiconductor device |
| KR20180109429A (en) * | 2017-03-28 | 2018-10-08 | 동우 화인켐 주식회사 | Etchant composition for etching nitride layer and method of forming pattern using the same |
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| KR100649872B1 (en) * | 2005-12-29 | 2006-11-27 | 동부일렉트로닉스 주식회사 | Method of fabricating the trench isolation layer in semiconductor device |
| KR20180109429A (en) * | 2017-03-28 | 2018-10-08 | 동우 화인켐 주식회사 | Etchant composition for etching nitride layer and method of forming pattern using the same |
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