KR20050041432A - Method for fabricating bitline in semiconductor device - Google Patents
Method for fabricating bitline in semiconductor device Download PDFInfo
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- KR20050041432A KR20050041432A KR1020030076603A KR20030076603A KR20050041432A KR 20050041432 A KR20050041432 A KR 20050041432A KR 1020030076603 A KR1020030076603 A KR 1020030076603A KR 20030076603 A KR20030076603 A KR 20030076603A KR 20050041432 A KR20050041432 A KR 20050041432A
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- Prior art keywords
- film
- region
- bit line
- forming
- ferry
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 20
- 238000001312 dry etching Methods 0.000 claims abstract description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000004888 barrier function Effects 0.000 claims abstract description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 7
- 239000010937 tungsten Substances 0.000 claims abstract description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 비트라인 형성방법에 관해 개시한 것으로서, 메인 셀영역과 페리영역이 정의된 반도체기판을 제공하는 단계와, 기판 위에 텅스텐막, 실리콘 질화막 및 SiON막을 차례로 형성하는 단계와, SiON막 위에 비트라인영역을 노출시키는 감광막 패턴을 형성하는 단계와, 감광막 패턴을 마스크로 하여 상기 SiON막을 등방성 건식 식각하여 측면에 슬로프가 형성된 반사방지막을 형성하되, 상기 페리영역이 과도 식각되어 상기 메인 셀영역에 비해 상기 페리영역의 측면에 슬로프가 심하게 형성되는 단계와, 상기 결과의 감광막 패턴 및 반사방지막을 마스크로 하여 상기 실리콘 질화막을 비등방성 건식 식각하여 하드마스크를 형성하는 단계와, 감광막 패턴을 제거하는 단계와, 반사방지막 및 하드마스크를 식각베리어로 이용하여 텅스텐막을 비등방성 건식 식각하여 상기 페리영역의 선폭이 증가된 비트라인을 형성하는 단계를 포함한다.The present invention relates to a method for forming a bit line of a semiconductor device, comprising the steps of: providing a semiconductor substrate having a main cell region and a ferri region defined thereon; forming a tungsten film, a silicon nitride film, and a SiON film on the substrate; Forming a photoresist pattern that exposes the bit line region on the film; and forming an anti-reflection film having a slope formed on a side surface by isotropic dry etching the SiON film using the photoresist pattern as a mask, wherein the ferry region is excessively etched to form the main cell. Forming a hard mask on the side surface of the ferry region in comparison with an area, forming a hard mask by anisotropic dry etching the silicon nitride film using the resulting photoresist pattern and the antireflection film as a mask, and removing the photoresist pattern. And a tungsten film using an anti-reflection film and a hard mask as an etching barrier. By anisotropic dry etching process and forming a bit line of a line width of increase in the ferry area.
따라서, 본 발명은, 비트라인의 반사방지막 형성 시, 페리영역의 측면 프로파일을 메인 셀영역에 비해 슬로프 정도가 심하도록 형성하고, 이를 식각베리어로 이용하여 비트라인을 식각함으로써, 메인 셀영역에서 비트라인의 선폭은 그대로 유지하면서 페리영역에서의 비트라인 선폭만을 기존보다 증가시킬 수 있다. Accordingly, in the present invention, when forming the anti-reflection film of the bit line, the side profile of the ferry region is formed to have a greater slope than that of the main cell region, and the bit line is etched using the etch barrier to form a bit in the main cell region. It is possible to increase the line width of the bit line in the ferry area more than before while maintaining the line width of the line.
Description
본 발명은 반도체소자의 형성방법에 관한 것으로, 보다 구체적으로는 비트라인 형성 시, 메인 셀영역의 선폭은 그대로 유지하거나 축소시키면서 페리영역의 선폭은 증가시킬 수 있는 수 있는 반도체소자의 비트라인 형성방법에 관한 것이다.The present invention relates to a method of forming a semiconductor device, and more particularly, to forming a bit line, a method of forming a bit line of a semiconductor device capable of increasing the line width of a ferry region while maintaining or reducing the line width of the main cell region. It is about.
디바이스가 고집적화됨에 따라, 메인 셀영역에서의 회로선폭과 각종 콘택은 그 크기가 점점 축소되고 있는 실정이다. 그러나, 비트라인에 있어서, 셀영역은 동일하거나 축소되어야 하지만 페리영역의 선폭까지 작아질 경우 이후 금속배선용 콘택과 비트라인 오버랩(overlap) 마진(margin)이 부족하게 되어 콘택이 비트라인 위에서 벗어나 기판까지 연결될 우려가 있다.As devices become more integrated, the circuit line widths and various contacts in the main cell region are decreasing in size. However, in the bit line, if the cell area should be the same or smaller but the line width of the ferry area becomes smaller, then the contact for the metallization and the bit line overlap margin are insufficient so that the contact is removed from the bit line to the substrate. There is a risk of connection.
따라서, 상기 문제점을 해결하고자, 본 발명의 목적은 비트라인 형성 시, 메인 셀영역의 선폭은 그대로 유지하거나 축소시키면서 페리영역의 선폭은 증가시킬 수 있는 수 있는 반도체소자의 비트라인 형성방법을 제공하려는 것이다.Accordingly, an object of the present invention is to provide a method for forming a bit line of a semiconductor device capable of increasing the line width of the ferry region while maintaining or reducing the line width of the main cell region when forming the bit line. will be.
상기 목적을 달성하고자, 본 발명에 따른 반도체 소자의 비트라인 형성방법은 메인 셀영역과 페리영역이 정의된 반도체기판을 제공하는 단계와, 기판 위에 텅스텐막, 실리콘 질화막 및 SiON막을 차례로 형성하는 단계와, SiON막 위에 비트라인영역을 노출시키는 감광막 패턴을 형성하는 단계와, 감광막 패턴을 마스크로 하여 상기 SiON막을 등방성 건식 식각하여 측면에 슬로프가 형성된 반사방지막을 형성하되, 상기 페리영역이 과도 식각되어 상기 메인 셀영역에 비해 상기 페리영역의 측면에 슬로프가 심하게 형성되는 단계와, 상기 결과의 감광막 패턴 및 반사방지막을 마스크로 하여 상기 실리콘 질화막을 비등방성 건식 식각하여 하드마스크를 형성하는 단계와, 감광막 패턴을 제거하는 단계와, 반사방지막 및 하드마스크를 식각베리어로 이용하여 텅스텐막을 비등방성 건식 식각하여 상기 페리영역의 선폭이 증가된 비트라인을 형성하는 단계를 포함한 것을 특징으로 한다.In order to achieve the above object, the method of forming a bit line of a semiconductor device according to the present invention comprises the steps of providing a semiconductor substrate having a main cell region and a ferri region defined, and sequentially forming a tungsten film, a silicon nitride film and a SiON film on the substrate; And forming a photoresist layer pattern exposing the bit line region on the SiON layer, and forming an anti-reflective layer having a slope formed on the side surface by isotropic dry etching the SiON layer using the photoresist pattern as a mask, wherein the ferry region is excessively etched. Forming a hard mask on the side surface of the ferry region in comparison with the main cell region, anisotropic dry etching the silicon nitride layer using the resulting photoresist pattern and the antireflection layer as a mask, and forming a photoresist pattern. Removing the tongue and using an anti-reflection film and a hard mask as an etch barrier Ten film characterized by including a step of forming an anisotropic dry-etching the line width of the ferry area increases in the bit line.
상기 SiON막의 등방성 식각 공정은 20mTorr의 압력과 1200W의 전압을 인가한 상태에서 CHF3,O2,Ar가스를 공급하여 실시하는 것이 바람직하다. 이때, 상기 O2가스는 10sccm 유량으로 공급한다.The isotropic etching of the SiON film is preferably performed by supplying CHF 3, O 2, and Ar gas under a pressure of 20 mTorr and a voltage of 1200 W. At this time, the O 2 gas is supplied at a flow rate of 10 sccm.
상기 실리콘 질화막의 비등방성 건식 식각 공정은 60mTorr의 압력과 1200W의 전압을 인가한 상태에서 CF4,CHF3,O2,Ar가스를 공급하여 실시하는 것이 바람직하다. The anisotropic dry etching process of the silicon nitride film is preferably performed by supplying CF 4, CHF 3, O 2, and Ar gas under a pressure of 60 mTorr and a voltage of 1200 W.
상기 텅스텐막의 비등방성 건식 식각 공정은 60mTorr의 압력과 1200W의 전압을 인가한 상태에서 CF4,CHF3,Ar가스를 공급하여 실시하는 것이 바람직하다.The anisotropic dry etching process of the tungsten film is preferably performed by supplying CF 4, CHF 3, Ar gas under a pressure of 60 mTorr and a voltage of 1200 W.
상기 식각 공정들은 RIE,ICP 및 TCP 중 어느 하나의 챔버를 이용하는 것이 바람직하다.The etching process preferably uses a chamber of any one of RIE, ICP and TCP.
(실시예)(Example)
이하, 첨부된 도면을 참고로 하여 본 발명에 따른 반도체소자의 비트라인 형성방법을 설명하면 다음과 같다.Hereinafter, a method of forming a bit line of a semiconductor device according to the present invention will be described with reference to the accompanying drawings.
도 1a 내지 도 1d는 본 발명에 따른 반도체소자의 비트라인 형성방법을 설명하기 위한 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a bit line of a semiconductor device according to the present invention.
본 발명에 따른 반도체소자의 비트라인 형성방법은, 도 1a에 도시된 바와 같이, 메인 셀영역과 페리영역이 정의된 반도체기판(1)을 제공한다. 이때, 상기 기판(1)에는, 도면에 도시되지 않았지만, 소오스/드레인 및 게이트를 포함한 트랜지스터가 제조되어 있으며, 소오스/드레인영역과 전기적으로 연결되는 도전 플러그가 형성되어 있다.The bit line forming method of a semiconductor device according to the present invention provides a semiconductor substrate 1 in which a main cell region and a ferry region are defined, as shown in FIG. 1A. In this case, although not shown in the drawing, a transistor including a source / drain and a gate is manufactured in the substrate 1, and a conductive plug electrically connected to the source / drain region is formed.
이어, 상기 기판(1) 위에 베리어막 용도의 Ti/TiN막(3), 금속배선 용도의 W막(5), 하드마스크 용도의 실리콘 질화막(7), 반사방지막 용도의 SiON막(9)을 차례로 형성한 다음, 상기 SiON막(9) 위에 감광막을 도포하고 노광 및 현상하여 비트라인영역을 노출시키는 감광막 패턴(20)을 형성한다.Next, on the substrate 1, a Ti / TiN film 3 for barrier films, a W film 5 for metal wiring, a silicon nitride film 7 for hard masks, and a SiON film 9 for antireflection films After forming sequentially, a photoresist film is coated on the SiON film 9, and the photoresist pattern 20 is exposed to expose and develop a bit line region.
그런 다음, 도 1b에 도시된 바와 같이, 상기 감광막 패턴(20)을 마스크로 하여 상기 SiON막을 등방성 건식 식각함으로서, 반사방지막(10)을 형성한다. 이때, 상기 반사방지막 건식 식각 공정 시, 메인 셀영역과 페리영역의 패턴 간의 스페이싱(spacing)의 차이로 인해 메인 셀영역보다 페리영역에서 더 많이 식각되며, 페리영역에서는 실리콘 질화막이 소정 두께 식각된다. 상기 SiON막 등방성 건식 식각 공정 결과, 페리영역은 메인 셀영역에 비해 측면에 더 심한 슬로프가 형성된다.Then, as shown in FIG. 1B, the anti-reflection film 10 is formed by isotropic dry etching the SiON film using the photoresist pattern 20 as a mask. At this time, during the anti-reflection film dry etching process, due to the difference in spacing between the patterns of the main cell region and the ferry region, more etching is performed in the ferry region than in the main cell region, and the silicon nitride layer is etched to a predetermined thickness in the ferry region. As a result of the isotropic dry etching process of the SiON film, a more severe slope is formed on the side of the ferry region than the main cell region.
상기 반사방지막 식각 공정은 20mTorr의 압력과 1200W의 전압을 가하면서 CHF3,O2,Ar가스를 공급하여 실시한다. 여기서, 상기 CHF3가스에서 C(탄소기)는 폴리머 생성을 많게 하기 위한 것이며, 상기 O2가스 공급은 CHF3가스에 의한 과도한 폴리머(polymer) 생성을 억제하기 위한 것으로서, 10sccm 이하의 유량으로 공급한다. The anti-reflection film etching process is performed by supplying CHF 3, O 2, and Ar gas while applying a pressure of 20 mTorr and a voltage of 1200 W. Here, C (carbon group) in the CHF3 gas is to increase the polymer production, the O2 gas supply is for suppressing excessive polymer (CH) generation by the CHF3 gas, it is supplied at a flow rate of 10sccm or less.
이어, 도 1c에 도시된 바와 같이, 상기 감광막을 패턴 및 반사방지막을 마스크로 하여 실리콘 질화막을 비등방성 건식식각함으로서, 하드마스크(8)를 형성한다. 이때, 상기 실리콘 질화막의 비등방성 건식 식각 공정 시, 메인 셀영역에서는 하드마스크(10)의 측면 프로파일이 버티컬(vertical)하게 형성된 반면에 페리영역에서는 측면 프로파일이 슬로프지고 버티컬하게 형성된다. 왜냐하면, 실리콘 질화막의 비등방성 건식 식각 시, 페리영역에서는 측면 프로파일이 슬로프진 반사방지막 및 실리콘 질화막이 식각마스크로서 작용하기 때문이다. Next, as shown in FIG. 1C, the hard mask 8 is formed by anisotropic dry etching of the silicon nitride film using the photosensitive film as a pattern and the antireflection film as a mask. At this time, in the anisotropic dry etching process of the silicon nitride film, the side profile of the hard mask 10 is vertically formed in the main cell region, whereas the side profile is sloped and vertically formed in the ferry region. This is because, in anisotropic dry etching of the silicon nitride film, an antireflection film and a silicon nitride film having a side profile sloped in the ferry region act as an etching mask.
한편, 상기 실리콘 질화막의 비등방성 식각 공정은 60mTorr의 압력과 1200W의 전압을 가하면서 CF4,CHF3,O2,Ar가스를 공급하여 실시한다. Meanwhile, the anisotropic etching process of the silicon nitride film is performed by supplying CF 4, CHF 3, O 2, and Ar gas while applying a pressure of 60 mTorr and a voltage of 1200 W.
그런 다음, 도 1d에 도시된 바와 같이, 감광막 패턴을 제거한다. 이 후, 상기 하드마스크를 식각베리어로 이용하여 W막 및 Ti/TiN막을 비등방성 식각하여 비트라인(b)을 제조한다. 이때, 상기 W막 및 Ti/TiN막을 비등방성 식각 공정은 60mTorr의 압력과 1200W의 전압을 가하면서 CF4,CHF3,Ar가스를 공급하여 실시한다. Then, as shown in Fig. 1D, the photoresist pattern is removed. Thereafter, using the hard mask as an etching barrier, an anisotropic etching of the W film and the Ti / TiN film is performed to prepare the bit line (b). At this time, the anisotropic etching process of the W film and the Ti / TiN film is performed by supplying CF 4, CHF 3, and Ar gas while applying a pressure of 60 mTorr and a voltage of 1200 W.
본 발명에서는 상기 메인 셀영역과 페리영역 간의 스페이싱 차이로 인해 메인 셀영역보다 페리영역에서 식각량이 더 많게 된다. 따라서, SiON막 식각 시, 페리영역에서는 SiON막 하부의 실리콘 질화막이 소정 두께 제거된다. 이때 프로파일을 비교하면, 페리영역이 메인 셀영역에 비해 슬로프가 심하게 형성된다.In the present invention, due to the spacing difference between the main cell region and the ferry region, the amount of etching is increased in the ferry region than in the main cell region. Therefore, during the etching of the SiON film, the silicon nitride film under the SiON film is removed by a predetermined thickness in the ferry region. At this time, if the profile is compared, the ferry region has a severe slope compared to the main cell region.
따라서, 페리영역의 슬로프진 패턴은 이 후의 식각 공정에서 식각 베리어로서 작용하게 됨에 따라, 페리영역은 메인 셀영역에 비해 기존보다도 훨씬 선폭이 증가하게 된다.Therefore, the sloped pattern of the ferry region acts as an etching barrier in the subsequent etching process, so that the ferry region has a much larger line width than the main cell region.
상기 식각 공정들은 RIE,ICP 및 TCP 중 어느 하나의 챔버 내에서 진행된다.The etching processes are performed in a chamber of any one of RIE, ICP and TCP.
통상적으로는 비트라인 형성 시, 페리영역이 메인 셀영역에 비해 식각되는 정도가 크다. 따라서, 본 발명에서는 이러한 점을 이용하여 페리영역의 반사방지막 및 하드마스크의 상부에 걸친 측면 프로파일을 메인 셀영역에서 보다 슬로프 정도가 심하도록 형성하고, 이를 식각베리어로 이용하여 비트라인을 형성함으로써, 페리영역에서의 비트라인 선폭을 기존보다 증가시킨다.In general, when the bit line is formed, the ferry region is more etched than the main cell region. Therefore, in the present invention, the side profile over the top of the hard mask and the anti-reflection film of the ferry region is formed to have a greater slope than that of the main cell region, and the bit line is formed using the etching barrier as an example. The bit line line width in the ferry area is increased.
따라서, 이후의 금속배선 콘택 형성시, 비트라인과의 오버레이 마진이 증가된다.Therefore, in the subsequent metallization contact formation, the overlay margin with the bit line is increased.
이상에서와 같이, 본 발명은 비트라인의 반사방지막 형성 시, 페리영역의 측면 프로파일을 메인 셀영역에 비해 슬로프 정도가 심하도록 형성하고, 이를 식각베리어로 이용하여 비트라인을 식각함으로써, 메인 셀영역에서 비트라인의 선폭은 그대로 유지하면서 페리영역에서의 비트라인 선폭만을 기존보다 증가시킬 수 있다. As described above, the present invention forms the side profile of the ferry region so that the slope is greater than the main cell region when forming the anti-reflection film of the bit line, by etching the bit line using the etching barrier, the main cell region In this case, the line width of the bit line can be increased while maintaining the bit line line width in the ferry region.
따라서, 본 발명에서는 이후의 공정에서 페리영역의 금속배선용 콘택과 비트라인의 오버레이 마진을 증가시켜 금속 배선 콘택이 기판까지 형성되는 것을 방지하는 이점이 있다.Therefore, in the present invention, there is an advantage that the metal wiring contact is prevented from being formed to the substrate by increasing the overlay margin of the metal wiring contact and the bit line in the ferry region.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다. In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
도 1a 내지 도 1d는 본 발명에 따른 반도체소자의 비트라인 형성방법을 설명하기 위한 공정단면도.1A to 1D are cross-sectional views illustrating a method of forming a bit line of a semiconductor device in accordance with the present invention.
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| KR100571629B1 (en) * | 2004-08-31 | 2006-04-17 | 주식회사 하이닉스반도체 | Method for manufacturing in semiconductor device |
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| KR100571629B1 (en) * | 2004-08-31 | 2006-04-17 | 주식회사 하이닉스반도체 | Method for manufacturing in semiconductor device |
| US7338906B2 (en) | 2004-08-31 | 2008-03-04 | Hynix Semiconductor, Inc. | Method for fabricating semiconductor device |
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