KR20050040557A - Driving method and apparatus of plasma display panel - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel and a plasma driving apparatus. In particular, in the driving method of the plasma display panel, during the sustain period, when the first sustain discharge pulse voltage is applied to the scan electrode or the sustain electrode, the third voltage is increased from the first voltage to the second voltage, and then the third voltage higher than the second voltage. Is applied to maintain the second voltage. Thereafter, a fourth voltage lower than the third voltage is applied, and the voltage is lowered from the fourth voltage to the fifth voltage. In this way, electromagnetic interference (EMI) can be reduced.

Description

Method and apparatus for driving plasma display panel {DRIVING METHOD AND APPARATUS OF PLASMA DISPLAY PANEL}

The present invention relates to a method of driving a plasma display panel and a plasma display device.

Recently, PDPs have been in the spotlight as flat panel display devices due to their high brightness, high luminous efficiency, and wide viewing angles, compared to other display devices.

A plasma display panel is a flat panel display device that displays characters or images using plasma generated by gas discharge, and tens to millions or more of pixels are arranged in a matrix form according to their size. First, the structure of the plasma display panel will be described with reference to FIGS. 1 and 2.

1 is a partial perspective view of a plasma display panel, and FIG. 2 shows an electrode arrangement diagram of the plasma display panel.

As shown in FIG. 1, the plasma display panel includes two glass substrates 1 and 6 facing each other apart. On the glass substrate 1, the scan electrode 4 and the sustain electrode 5 are formed in pairs and in parallel, and the scan electrode 4 and the sustain electrode 5 are covered with the dielectric layer 2 and the protective film 3. have. A plurality of address electrodes 8 are formed on the glass substrate 6, and the address electrodes 8 are covered with the insulator layer 7. The address electrode 8 and the partition 9 are formed on the insulator layer 7 between the address electrodes 8. In addition, the phosphor 10 is formed on the surface of the insulator layer 7 and on both sides of the partition wall 9. The glass substrates 1 and 6 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 4, the address electrode 8, the sustain electrode 5, and the address electrode 8 are orthogonal to each other. The discharge space 11 at the intersection of the address electrode 8 and the paired scan electrode 4 and the sustain electrode 5 forms a discharge cell 12.

As shown in FIG. 2, the electrode of the plasma display panel has a matrix structure of n × m. The plurality of address electrodes A ₁ -A _m are arranged in the vertical direction, and the plurality of scan electrodes Y ₁ -Y _n and the storage electrodes X ₁ -X _n are arranged in pairs in the horizontal direction.

The plasma display panel is driven by dividing one frame into a plurality of subfields, and gray scales are expressed by a combination of subfields. In general, each subfield includes a reset period, an address period, and a sustain period. The reset period serves to erase the wall charges formed by the previous sustain discharge and to set up the wall charges in order to stably perform the next address discharge. The address period is a period in which a wall charge is accumulated in a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on in the panel. The sustain period is a period in which sustain discharge is performed to actually display an image in the addressed cells.

In general, in order to implement a high-efficiency plasma display panel, the ratio of xenon (Xe) in the discharge gas is improved to increase luminous efficiency and luminance. In order to increase the luminous efficiency and luminance, the ratio of xenon is increased, whereby the driving voltage rises and thus the discharge voltage rises. In other words, as the ratio of xenon increases, a higher sustain discharge voltage is required for stable sustain discharge.

In order to stably perform sustain discharge in the related art, after the address period, at the beginning of the sustain period, the voltage of one or more sustain discharge pulses is made higher than the voltage of the pulses of other sustain discharges to reliably implement the sustain discharge in the sustain period following the address discharge. To make it possible. Such drive waveforms are disclosed in Japanese Patent Laid-Open No. 2000-305510 or Japanese Patent Laid-Open No. 2002-258795.

However, when the hard switching is performed to increase the sustain discharge pulse voltage at the beginning of the sustain period as in the prior art, as the ratio of xenon increases, a large amount of current suddenly flows. Electromagnetic interference is increased by the increase of the current, and as a result, the sustain discharge becomes unstable and there is a problem that normal display cannot be performed.

The technical problem to be solved by the present invention is to solve the above problems, and the plasma display panel driving method and plasma to increase the driving voltage margin and reduce the EMI to drive the high efficiency plasma panel in the sustain period An object of the present invention is to provide a display device.

In order to achieve the above object, the present invention applies the first sustain discharge pulse of the sustain period to the scan electrode in the form of a step.

According to one aspect of the present invention, a reset period, an address period, and a sustain period include a first period in which a sustain period alternately applies a normal sustain discharge pulse voltage to the first electrode and the second electrode and a normal sustain discharge pulse voltage. A method of driving a plasma display panel including a second section for applying a first sustain discharge pulse voltage greater than a voltage level of is provided. In the driving method, applying a first sustain discharge pulse voltage may include applying a first voltage higher than a voltage level of the normal sustain discharge pulse voltage to the first electrode and maintaining the first voltage for a predetermined period of time. Applying one voltage waveform; Applying a second voltage waveform to the first electrode from a first voltage to a second voltage lower than a first voltage; And applying a third voltage waveform to the first electrode from the second voltage to the third voltage. At this time, the second voltage may be equal to the voltage level of the normal sustain discharge pulse voltage.

In addition, the applying of the third voltage waveform may use the power recovery circuit to lower the voltage from the second voltage to the third voltage, and the slope of the third voltage waveform may be gentler than the slope of the second voltage waveform. have.

According to another feature of the present invention, a reset period, an address period, and a sustain period include a first period in which a sustain period alternately applies a normal sustain discharge pulse voltage to the first electrode and the second electrode and a normal sustain discharge pulse voltage. A method of driving a plasma display panel including a second section for applying a first sustain discharge pulse voltage greater than a voltage level of is provided. In the driving method, the applying of the first sustain discharge pulse voltage may include applying a first voltage waveform to the first electrode to increase from a first voltage to a second voltage; Applying a third voltage higher than the voltage level of the normal sustain discharge pulse from the second voltage to the first electrode and applying a second voltage waveform holding the third voltage; Applying a third voltage waveform to the first electrode from a third voltage to a fourth voltage lower than the third voltage; And applying a fourth voltage waveform to the first electrode to drop from the fourth voltage to the fifth voltage. In this case, the first voltage and the fourth voltage may be equal to the voltage level of the normal sustain discharge pulse voltage, and the applying of the first voltage waveform and the applying of the fourth voltage waveform may be performed using a power recovery circuit. It may be increased from the first voltage to the second voltage or lowered from the fourth voltage to the fifth voltage.

In addition, the slope of the first voltage waveform may be gentler than the slope of the second voltage waveform, and the slope of the fourth voltage waveform may be gentler than the slope of the third voltage waveform.

The first electrode may be a scan electrode. Further, the first sustain discharge pulse voltage may be the first sustain discharge pulse voltage applied to the first electrode in the sustain period, and the width of the first sustain discharge pulse voltage is equal to the normal sustain discharge pulse voltage applied to the sustain period. It can be longer than the width.

According to still another aspect of the present invention, there is provided a driving apparatus of a plasma display panel for applying a normal sustain discharge pulse voltage to a first electrode and a second electrode and a panel capacitor formed between the first electrode and the second electrode. . The driving device includes a first transistor and a second transistor connected in series between the first voltage and the second voltage; A third transistor electrically connected between the contacts of the first and second transistors and the panel capacitor; A fourth transistor electrically connected between the panel capacitor and a third voltage higher than the first voltage; And an inductor having one end connected to a contact point of the first transistor and the second transistor, the energy power recovery circuit applying a rising or falling voltage to the panel capacitor using the inductor.

At this time, the first voltage is a normal sustain discharge pulse voltage applied to the first electrode and the second electrode in the sustain period.

The display device may further include a capacitor having one end connected to a contact point of the first transistor and the second transistor and the other end connected to a fifth voltage, and further comprising a fifth transistor electrically connected between the fifth voltage and the panel capacitor. And a diode connected between the other end of the capacitor and the fifth voltage.

A method of driving a plasma display panel according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First, with reference to the accompanying drawings will be described in detail to be easily carried out by those of ordinary skill in the art with respect to embodiments of the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In describing the present invention, when it is determined that the detailed description of the related known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description is omitted.

3 is a diagram illustrating a plasma display panel according to an exemplary embodiment of the present invention.

As shown in FIG. 3, a plasma display panel according to an exemplary embodiment of the present invention includes a plasma panel 100, a controller 200, an address driver 300, a sustain electrode driver 400, and a scan electrode driver 500. do.

The plasma panel 100 includes a plurality of address electrodes A1 to Am arranged in a column direction, a plurality of sustain electrodes X1 to Xn arranged in a zigzag direction in a row direction, and a scan electrode Y1 to Yn. .

The controller 200 receives an image signal from the outside and outputs an address driving control signal, a sustain electrode (X electrode) driving control signal, and a scan electrode (Y electrode) driving control signal.

The address driver 300 receives an address driving control signal from the controller 200 and applies a display data signal for selecting a discharge cell to be displayed to each address electrode.

The sustain electrode driver 400 receives the sustain electrode X driving control signal from the controller 200 and applies a driving voltage to the sustain (X) electrode.

The scan electrode driver 500 receives the scan electrode Y driving control signal from the controller 200 and applies a driving voltage to the scan Y electrode.

According to the exemplary embodiment of the present invention, when the scan electrode driver 500 applies the first sustain discharge pulse voltage to the scan electrode in the sustain period, the scan electrode driver 500 applies the sustain discharge pulse voltage at a rising portion of the first sustain discharge pulse voltage. After application, the voltage is raised from the sustain discharge pulse voltage to a voltage higher than the sustain discharge pulse voltage in a step form. Thereafter, the scan electrode driver 500 descends the sustain discharge pulse voltage to a sustain discharge pulse voltage from a voltage higher than the sustain discharge pulse voltage in the falling portion of the first sustain discharge pulse voltage. In addition, the sustain electrode driver 400 may similarly apply the first sustain discharge pulse applied to the sustain electrode X during the sustain period in the same manner as the scan electrode driver 500.

4 is a driving waveform diagram of a plasma display panel according to a first embodiment of the present invention.

Each of the subfields in the driving waveform according to a first embodiment of the present invention includes a reset period (P _r), an address period (P _a), and a sustain period (P _s). The reset period P _r includes an erase period, a rising ramp period and a falling ramp period.

The erase period of the reset period P _r is a period for erasing charges formed by sustain discharge in the sustain period of the previous subfield. The rising ramp period is a period in which wall charges are formed in the scan electrode Y, the sustain electrode X, and the address electrode A, and the falling ramp period erases some of the wall charges formed in the rising lamp period to facilitate address discharge. It is a period. An address period (P _a) is a period for selecting a discharge cell to cause sustain discharge in a sustain period of the plurality of discharge cells. Sustain period (P _s) is a period for maintaining discharge in the discharge cells selected by applying a sustain pulse in turn to the scan electrode (Y) and the sustain electrode (X) during the address period (P _a).

In the plasma display panel, a scan / hold driving circuit for applying a driving voltage to the scan electrode Y and the sustain electrode Y in each of the periods P _r , P _a , and P _s , and a driving voltage to the address electrode A, respectively. An address driving circuit for applying a is connected to form one display device.

4, in the rising ramp period P _r2 of the reset period P _r , the voltage gradually rises from the voltage V _s toward the voltage V _set while maintaining the address electrode A and the sustain electrode X at 0V. The ramp voltage is applied to the scan electrode (Y). While this voltage rises, the first weak reset discharge occurs in each of the discharge cells from the scan electrode Y to the address electrode A and the sustain electrode X, respectively. As a result, negative wall charges are accumulated in the scan electrode Y, and positive wall charges are accumulated in the address electrode A and the sustain electrode X at the same time.

Here, the wall charge refers to a charge that is formed on the wall of the discharge cell (eg, the dielectric layer) close to each electrode and accumulates in the electrode. This wall charge is not actually in contact with the electrode itself, but here the wall charge is described as "formed", "accumulated" or "stacked" on the electrode. In addition, a wall voltage refers to the potential difference formed in the wall of a discharge cell by wall charge.

Subsequently, in the falling ramp period P _r3 , a ramp voltage that gradually falls from the V _s voltage to the -V _nf voltage is applied to the scan electrode Y while the sustain electrode X is maintained at the voltage V _b1 . While this ramp voltage falls, the second weak reset discharge occurs again in all the discharge cells. As a result, the negative wall charges of the scan electrode Y decrease and the positive wall charges of the sustain electrode X and the address electrode A decrease.

And an address period (P _a) in the other scan electrode (Y) by a V _sch voltage applied to a state lower than the voltage -V -V _{scl nf} voltage sequentially to the scan electrode (Y) during the sustain the scan electrodes (Y) Choose. And V _scl is the negative voltage applied to the address voltage (V _a) to the address electrode (A) to form a discharge cell to be selected among the discharge cells formed by applying the scan electrode (Y). Then, the voltage applied to the address electrodes (A) (V _a) and the wall voltage due to the wall charges formed on the difference and the address electrode (A) and scan electrodes (Y) of the voltage (V _n) applied to the scan electrode (Y) This causes address discharge. In addition, when the V _sch voltage is applied to the scan electrode Y, a V _b2 voltage higher than the V _b1 voltage is applied to the sustain electrode X.

Here, an address period (P _a) when further lowered beyond the predetermined range of voltage (-V _scl) to be applied to the scan electrode (Y) in, a problem that erroneous discharge occurs between the scan electrode (Y) and the sustain electrode (X) This happens. That is, an address period (P _a) difference (DELTA _{V = | -V scl -V nf |} ) of the voltage (V _b2) of applying a voltage (-V _scl) and the sustain electrodes to be applied to the scan electrode (Y) in the When the discharge start voltage (V _f ) is exceeded, a discharge may occur in a place other than the discharge cell to be selected, thereby causing an erroneous discharge. Therefore, in order to properly discharge the discharge cells to be selected, the values of the voltage Ve applied to the sustain electrode X and the voltage applied to the scan electrode Y in the address period must be appropriately adjusted.

Next, in the sustain period P _s , a sustain pulse (hereinafter referred to as a sustain discharge pulse) is sequentially applied to the scan electrode Y and the sustain electrode X in sequence. The sustain discharge pulse is a pulse that causes the voltage difference between the scan electrode Y and the sustain electrode X to alternately become a V _s voltage and a -V _s voltage. The V _s voltage is lower than the discharge start voltage between the scan electrode Y and the sustain electrode X. If the address period (P _a), the wall voltage between the scan electrode (Y) and the sustain electrode (X) by the address discharge are formed on the scan electrode by the wall voltage and V _s the voltage (Y) and the sustain electrode (X) Discharge occurs at.

According to the present invention, there is disclosed a method capable of reliably implementing sustain discharge in a sustain period even if the driving voltage increases with increasing ratio of xenon.

The first keep sustaining the discharge pulse voltage to each electrode in Fig. According to the first embodiment of the present invention as shown in 4, sustain periods sustain periods (P _s) which is located immediately after the scan pulse in the address period (P _a) ( X is applied to the scan electrode (Y). At this time, the voltage V _fs of the first sustain discharge pulse applied to the scan electrode Y is higher than the voltage V _s of the remaining sustain discharge pulses applied to the scan electrode Y. The V _s voltage is applied to the rear end of the first sustain discharge pulse to which the V _fs voltage is applied. That is, the first sustain discharge pulse voltage applied to the scan electrode Y is applied with the voltage V _fs higher than the voltage V _s , and then the voltage V _s is applied without directly lowering the voltage to the reference voltage (0 V). 0V). Thus, by configuring the first sustain discharge pulse into two stages of the voltage V _{fs and the} voltage V _s , the current flowing in the falling portion of the first sustain discharge pulse can be reduced, thereby suppressing EMI. In the sustain period applied alternately to the scan electrode Y and the sustain electrode X, the voltage of the first sustain discharge pulse applied to the scan electrode Y is set higher than that of the remaining sustain discharge pulses. Strong discharge can be generated. Therefore, after the first sustain discharge pulse is applied, many wall charges are accumulated in the scan electrode Y and the sustain electrode X. FIG. As a result, subsequent discharge discharges can be more easily implemented.

Here, V _fs may be set to a value between V _s and V _smax . The V _smax voltage is a voltage at which erroneous discharge starts when V _fs is increased.

5 is a diagram illustrating an example of a circuit diagram used to apply a driving waveform according to FIG. 4. The following describes only the driving operation in the sustain period according to the present invention, and the circuit configuration is simplified and expressed only by the driving circuit in the sustain period. 6 is a switching timing diagram in the circuit diagram of FIG. 5 for the waveform according to FIG. 4.

According to the scan electrode driver 500 according to the first embodiment of the present invention, the sustain discharge voltage, the voltage V _s, and which is a transistor (Ys, Yg) is connected in series between the ground voltage, the transistor (Ys, Yg) The transistor Ypp is connected to the contact point of the transistor and the scan electrode Y of the panel capacitor Cp. Here, the panel capacitor Cp equivalently represents the capacitance component between the sustain electrode X and the scan electrode Y. FIG. For convenience, only the scan electrode Y is shown.

The first terminal of the inductor L1 is connected to the contact between the transistors Ys and Yg. The ground voltage and the first terminal of the capacitor _Cerc for the power recovery circuit are connected, and between the transistor Yr and the diode between the second terminal of the capacitor _Cerc for the power recovery circuit and the first terminal of the inductor L1. The transistor D1 is connected in series, and the transistor Yf and the diode D2 are connected in parallel between the second terminal of the capacitor _Cerc for the power recovery circuit and the first terminal of the inductor L1. Here, the transistor Yf and the diode D2 are connected in series with each other.

In addition, the first terminal of the capacitor Cset is connected to the contact between the transistors Ys and Yg connected to the second terminal of the inductor L1, and the voltage Vset− is connected to the contact between the transistors Ys and Yg. The diode D is connected between Vs) and the second terminal k of the capacitor Cset. A transistor Yrr for applying a rising ramp voltage to the scan electrode Y is connected in parallel between a first terminal of the panel capacitor Cp and a second terminal of the capacitor Cset, and is connected between the transistors Ypp and Yrr. The transistor Yfs is connected in series between the contact of and the voltage Vfs.

The waveform of the first sustain discharge pulse of the sustain period according to the first embodiment of the present invention will be described in detail with reference to the circuit diagram thus constructed and the switching diagram of FIG. 6. Here, it is assumed that the capacitor Cec is charged with the voltage V _s / 2.

According to the first embodiment of the present invention, in the first sustain discharge pulse at which the sustain period starts, first, when applying the voltage V _{fs at the} voltage of 0 V, only the transistor Yfs is turned on and all the remaining transistors are turned off. Then, V _fs voltage is supplied to the scan electrode Y of the panel capacitor Cp through the same path as that of mode 1 (transistor Yfs).

Then, when generating a two-stage pulse at the rear end of the waveform in which the V _fs voltage is applied to the V _s voltage to suppress the EMI, the transistors Ys and Ypp are turned on and all the remaining transistors are turned off. Then, the V _s voltage lower than the V _fs voltage is supplied to the scan electrode Y of the panel capacitor Cp through the same path as Mode 2 (transistor Ys-capacitor Cset-Ypp).

Next, when lowering from the V _s voltage to the 0 V voltage, only the transistors Yf and Ypp are turned on and all the remaining transistors are turned off. Then, the transistors Yf and Ypp are turned on and only the transistors Yg and Ypp are turned on while all other transistors are turned off. Then, the voltage V _s supplied in the mode 2 through a path such as mode 3 (transistor (Ypp) -inductor (L1) -transistor (Yf) -capacitor for power recovery circuit (Cerc)) then becomes inductor L1 and power. Resonance is generated by the recovery circuit capacitor Cec, and the voltage of the scan electrode of the panel capacitor Cp maintains 0V through the same path as that of mode 4 (transistor Yg-transistor Ypp).

In this way, the first sustain discharge pulse having two stages at the rear end of the pulse is applied to the scan electrode Y through the mode 1 and the mode 4.

Thereafter, a normal sustain discharge pulse is applied. First, when applying the voltage from 0V to V _s , the transistors Yr and Ypp are kept turned on and all the other transistors are turned off. Then, the scanning electrode Y of the panel capacitor Cp through a path such as mode 5 (capacitor Cerc-transistor Yr-diode D1-inductor L1-transistor Ypp) for power recovery circuit. Supply the voltage to V _s . At this time, the voltage V _s may be supplied without power consumption by using resonance between the power recovery circuit capacitor Cec and the inductor L1.

Then, only transistors Ys and Ypp are turned on, and all other transistors are turned off. This maintains the V _s voltage that was supplied in mode 5 via the same path as mode 6 (transistor (Ys) -capacitor (Cset) -transistor (Ypp)).

Thereafter, when lowering the voltage 0V from the voltage V _s, the same operation as that of the mode 3, and mode 4 is lowered to the voltage 0V to the scan electrode (Y) of the panel capacitor (Cp).

As described above, according to the sustain driving method of the first embodiment of the present invention, the first sustain discharge pulse voltage applied to the scan electrode Y during the sustain period is applied higher than the remaining sustain discharge pulse voltage using hard switching. In addition, the falling portion of the first sustain discharge pulse is not immediately lowered as in the prior art, and a two-stage pulse is generated when the voltage falls from V _fs voltage to V _s voltage. Therefore, the first sustain discharge can be generated strongly and the EMI can be further suppressed.

In the first embodiment of the present invention, as shown in FIG. 4, the hard switching is used for the rising portion, which is the front end portion of the first sustain discharge pulse applied to the scan electrode Y in the sustain period P _s , and the rear end portion is divided into two stages. Modifications have suppressed EMI, but can be different. Hereinafter, this embodiment will be described with reference to FIG. 7.

7 is a driving waveform diagram of a plasma display panel according to a second embodiment of the present invention. Here, the driving operation in the reset period and the address period is the same as in Fig. 4, and will be omitted.

As shown in FIG. 7, in the rising period of the front end portion of the first sustain discharge pulse applied to the scan electrode Y in the sustain period P _s , the voltage is raised to the voltage V _s using an ERC circuit, and then the V _s voltage and V _The V _fs voltage, which is higher than the _s voltage, is configured in two stages, and finally the V _fs voltage is applied to the scan electrode Y. Then, the rear end of the first sustain discharge pulse is the same as in FIG.

In this way, the currents in the rising and falling portions of the first sustain discharge pulse applied to the scan electrode Y in the sustain period P _s can be reduced, thus significantly reducing the EMI. The voltage difference between the first sustain discharge pulse and the sustain electrode can be increased to increase the potential difference between the scan electrode Y and the sustain electrode X, thereby improving the transition of the sustain discharge from the address discharge. Can be surely generated.

Hereinafter, the sustain driving method according to the second embodiment of the present invention will be described with reference to the circuit diagram of FIG. 5 and the switching diagram of FIG. 8.

8 is a switching timing diagram in the circuit diagram of FIG. 5 for the waveform according to the present invention. Here, it is assumed that the capacitor Cec is charged with the voltage V _s / 2.

According to the second embodiment of the present invention, by using a power recovery circuit (ERC) and supplies the sustain pulse voltage V _s of the voltage applied to the first time without power consumption.

According to the second embodiment of the present invention, the transistors Yr and Ypp are turned on and the other transistors are turned off when the first sustain discharge pulse, which starts the sustain period, is first applied from a voltage of 0 V to V _s . . Then, the scan electrode Y of the panel capacitor Cp through the same path as the mode 1 '(capacitor Cerc-transistor Yr-diode D1-inductor L1-transistor Ypp). Supply the voltage to V _s . That is, the voltage of this case is that the generation by the resonance capacitor (Crec) and an inductor (L1) by using a power recovery circuit panel capacitor (Cp) is increased without the consumption of power by the voltage V _s.

Next, when the voltage is further increased from the V _s voltage to the V _fs voltage, the transistor Yfs is turned on with the transistors Yr and Ypp turned on. Then, the voltage V _fs is supplied to the scan electrode Y of the panel capacitor Cp through the same path as the mode 2 '(transistor Yfs).

Thereafter, the driving voltage according to the waveform of the rear end of the first sustain discharge pulse voltage is the same as in the modes 2 to 4 as described above.

After the first sustain discharge pulse voltage, the waveform according to the normal sustain discharge pulse voltage is applied to mode 5 and 6 in the rising part and the modes 3 and 4 are repeated in the falling part as described above.

As described above, according to the sustain driving method of the first embodiment of the present invention, the first sustain discharge pulse voltage applied to the scan electrode Y during the sustain period is applied higher than the remaining sustain discharge pulse voltage, and the first sustain operation is performed. a rising portion of the discharge pulse supplied to V _s voltage without power consumption by using the ERC then allowed to rise to V _fs voltage, without directly lowered, as in the first falling bubunreul conventional second sustain discharge pulses, V _s voltage from V _fs voltage To generate a two-stage pulse. Therefore, the first sustain discharge can be generated strongly, and the rising and falling portions of the first sustain discharge pulse are configured in two stages to reduce the current flowing during the transistor switching. As a result, EMI can be suppressed due to the reduced current.

Hereinafter, the effects of the first and second embodiments of the present invention will be described in detail with reference to FIGS. 9A and 9B.

FIG. 9A is a graph illustrating driving voltage margin by a first general sustain discharge pulse, and FIG. 9B is a graph illustrating driving voltage margin by a first sustain discharge pulse according to an exemplary embodiment of the present invention.

In FIG. 9A, as a general sustain discharge pulse voltage, when the V _fs voltage and the V _s voltage are at the same level, the driving voltage margin actually measured is shown. In addition, in 9b, when the V _fs voltage is 20V higher than the V _s voltage according to the first and second embodiments of the present invention, the driving voltage margin actually measured is shown.

Here, the Y axis represents an address voltage (V _a) shows the X-axis is the sustain discharge voltage (V _s).

9A and 9B, when the driving waveforms as in the embodiment of the present invention are used, the driving voltage margin can be extended to the low voltage side of the sustain discharge voltage V _s .

In addition, by using the rising and falling portions of the first sustain discharge pulse in two stages, the current flowing during the switching of the transistor can be reduced, and the EMI can be reduced by reducing the current.

In the first and second embodiments of the present invention, the first sustain discharge pulse applied to the scan electrode Y in the sustain period is illustrated and described. Alternatively, the first sustain discharge pulse composed of multiple stages is applied to the sustain electrode X. May be authorized.

In the first and second embodiments of the present invention, the rising and falling portions of the first sustain discharge pulse of the sustain period are generated as two stage pulses, but the present invention is not limited thereto. That is, a multi-stage pulse may be generated.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, the driving voltage margin can be expanded to stably generate sustain discharge in the plasma display panel of high efficiency, and the EMI can be effectively suppressed.

1 is a partial perspective view of a typical plasma display panel.

2 is an electrode array diagram of a general plasma display panel.

3 is a diagram illustrating a plasma display panel according to an exemplary embodiment of the present invention.

4 is a driving waveform diagram of a plasma display panel according to a first embodiment of the present invention.

5 is a diagram illustrating an example of a circuit diagram used to apply a driving waveform according to FIG. 4.

6 is a switching timing diagram in the circuit diagram of FIG. 5 for the waveform according to FIG. 4.

7 is a driving waveform diagram of a plasma display panel according to a second embodiment of the present invention.

8 is a switching timing diagram in the circuit diagram of FIG. 5 for the waveform according to the present invention.

9A is a graph illustrating driving voltage margins due to a conventional general first sustain discharge pulse.

9B is a graph illustrating driving voltage margin by a first sustain discharge pulse according to an embodiment of the present invention.

Claims (18)

A first sustain period including a reset period, an address period, and a sustain period, wherein the sustain period is greater than a voltage level of the first period and the normal sustain discharge pulse voltage which alternately apply a normal sustain discharge pulse voltage to the first electrode and the second electrode; In the method of driving a plasma display panel including a second period for applying a discharge pulse voltage, Applying the first sustain discharge pulse voltage, Applying a first voltage waveform higher than a voltage level of the normal sustain discharge pulse voltage to the first electrode and applying a first voltage waveform for maintaining the first voltage for a predetermined period of time; Applying a second voltage waveform to the first electrode from a first voltage to a second voltage lower than a first voltage; And Applying a third voltage waveform to the first electrode to drop from the second voltage to a third voltage; Method of driving a plasma display panel comprising a. The method of claim 1, And the second voltage is equal to the voltage level of the normal sustain discharge pulse voltage. The method of claim 1, The step of applying the third voltage waveform is a method of driving a plasma display panel, characterized in that to drop from the second voltage to the third voltage using a power recovery circuit. The method of claim 1, And the slope of the third voltage waveform is gentler than the slope of the second voltage waveform. A first sustain period including a reset period, an address period, and a sustain period, wherein the sustain period is greater than a voltage level of the first period and the normal sustain discharge pulse voltage which alternately apply a normal sustain discharge pulse voltage to the first electrode and the second electrode; In the method of driving a plasma display panel including a second period for applying a discharge pulse voltage, Applying the first sustain discharge pulse voltage, Applying a first voltage waveform to the first electrode to increase from a first voltage to a second voltage; Applying a third voltage higher than the voltage level of the normal sustain discharge pulse from the second voltage to the first electrode and applying a second voltage waveform holding the third voltage; Applying a third voltage waveform to the first electrode from a third voltage to a fourth voltage lower than the third voltage; And Applying a fourth voltage waveform to the first electrode from the fourth voltage to the fifth voltage; Method of driving a plasma display panel comprising a. The method of claim 5, And the first voltage and the fourth voltage are the same as the voltage level of the normal sustain discharge pulse voltage. The method of claim 5, The applying of the first voltage waveform and the applying of the fourth voltage waveform may be performed by using a power recovery circuit to increase from the first voltage to the second voltage or from the fourth voltage to the fifth voltage. Driving method of plasma display panel. The method of claim 5, And the slope of the first voltage waveform is gentler than the slope of the second voltage waveform. The method of claim 5, And the slope of the fourth voltage waveform is gentler than the slope of the third voltage waveform. The method according to claim 1 or 5, And the first electrode is a scan electrode. The method according to claim 1 or 5, And the first sustain discharge pulse voltage is a first sustain discharge pulse voltage applied to the first electrode in the sustain period. The method according to claim 1 or 5, And a width of the first sustain discharge pulse voltage is longer than a width of a normal sustain discharge pulse voltage applied in the sustain period. In the driving apparatus of the plasma display panel for applying a normal sustain discharge pulse voltage to the first electrode and the second electrode, and the panel capacitor formed between the first electrode and the second electrode, A first transistor and a second transistor connected in series between the first voltage and the second voltage; A third transistor electrically connected between the contacts of the first and second transistors and the panel capacitor; A fourth transistor electrically connected between the panel capacitor and a third voltage higher than the first voltage; And An energy power recovery circuit including an inductor having one end connected to a contact point of the first transistor and the second transistor, and applying a voltage rising or falling to the panel capacitor using the inductor. Driving device for a plasma display panel comprising a. The method of claim 13, And the first voltage is a normal sustain discharge pulse voltage applied to the first electrode and the second electrode during the sustain period. The method of claim 13, A capacitor having one end connected to a contact point of the first transistor and a second transistor and the other end connected to a fifth voltage The driving apparatus of the plasma display panel further comprising. The method of claim 15, A fifth transistor electrically connected between the fifth voltage and the panel capacitor The driving apparatus of the plasma display panel further comprising. The method of claim 15, A diode connected between the other end of the capacitor and the fifth voltage The driving apparatus of the plasma display panel further comprising. The method of claim 13, And the second voltage and the fourth voltage are ground voltages.