KR20050040015A - Method of manufacturing image sensor having fuse box - Google Patents
Method of manufacturing image sensor having fuse box Download PDFInfo
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- KR20050040015A KR20050040015A KR1020030075117A KR20030075117A KR20050040015A KR 20050040015 A KR20050040015 A KR 20050040015A KR 1020030075117 A KR1020030075117 A KR 1020030075117A KR 20030075117 A KR20030075117 A KR 20030075117A KR 20050040015 A KR20050040015 A KR 20050040015A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 65
- 238000005530 etching Methods 0.000 claims abstract description 15
- 238000002161 passivation Methods 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 230000007547 defect Effects 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 101100123053 Arabidopsis thaliana GSH1 gene Proteins 0.000 description 2
- 101100298888 Arabidopsis thaliana PAD2 gene Proteins 0.000 description 2
- 101150092599 Padi2 gene Proteins 0.000 description 2
- 102100035735 Protein-arginine deiminase type-2 Human genes 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 101000590281 Homo sapiens 26S proteasome non-ATPase regulatory subunit 14 Proteins 0.000 description 1
- 101001114059 Homo sapiens Protein-arginine deiminase type-1 Proteins 0.000 description 1
- 102100023222 Protein-arginine deiminase type-1 Human genes 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
- H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electromagnetism (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
본 발명은 패드오픈 공정시 패드영역의 배선 손상을 방지하면서 퓨즈영역 잔존 산화막 두께의 균일성을 확보하여 와이어 본딩 불량 및 퓨즈 절단에러 등을 효과적으로 방지할 수 있는 이미지센서의 제조방법을 제공한다.The present invention provides a method of manufacturing an image sensor that can effectively prevent wire bonding defects and fuse cutting errors by ensuring uniformity of the remaining oxide film thickness while preventing wiring damage of the pad area during the pad opening process.
본 발명은 패드영역과 퓨즈영역이 정의되고 상부에 절연막이 형성된 반도체 기판을 준비하는 단계; 패드영역의 절연막 상에 금속배선을 형성함과 동시에 퓨즈영역의 절연막 상에 금속 퓨즈를 형성하는 단계; 기판 전면 상에 패시배이션막을 형성하는 단계; 금속배선 및 금속 퓨즈 상에 소정 두께가 잔존하도록 패시배이션막을 제 1 식각하는 단계; 및 금속배선의 일부가 오픈되도록 패시배이션막을 제 2 식각하는 단계를 포함하는 이미지센서의 제조방법에 의해 달성될 수 있다. The present invention provides a method for manufacturing a semiconductor substrate including a pad region and a fuse region, and an insulating film formed thereon; Forming a metal fuse on the insulating film of the pad region and simultaneously forming a metal fuse on the insulating film of the fuse region; Forming a passivation film on the entire surface of the substrate; First etching the passivation film so that a predetermined thickness remains on the metal wiring and the metal fuse; And a second etching of the passivation film so that a part of the metal wiring is opened.
Description
본 발명은 이미지센서(image sensor)의 제조방법에 관한 것으로, 특히 퓨즈박스(fuse box)를 구비한 이미지센서의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing an image sensor, and more particularly, to a method of manufacturing an image sensor having a fuse box.
일반적으로, 이미지센서는 광학영상(optical image)을 전기적 신호로 변환시키는 반도체 소자로서, 빛을 감지하는 광감지 부분과 감지된 빛을 전기적 신호로 처리하여 데이터화하는 로직회로 부분으로 구성되어 있으며, CMOS(Complementary Metal Oxide Semiconductor) 이미지센서의 경우에는 CMOS 기술을 이용하여 화소 수만큼 MOS 트랜지스터를 만들고 이것을 이용하여 차례차례 출력을 검출하는 스위칭 방식을 채용한다. 칼라 이미지를 구현하기 위한 이미지센서는 광감지 부분 상에 레드(Red; R), 그린(Green; G), 블루(Blue; B)의 3가지 칼라필터로 이루어진 칼라필터 어레이(Color Filter Array; CFA)가 구비된다.In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal. The image sensor is composed of an optical sensing part that senses light and a logic circuit part that processes the sensed light into an electrical signal to make data. (Complementary Metal Oxide Semiconductor) In the case of image sensor, CMOS technology is used to make MOS transistors by the number of pixels, and the switching method is used to detect the output sequentially. An image sensor for realizing a color image includes a color filter array (CFA) consisting of three color filters, red (R), green (G), and blue (B), on a light sensing portion. ) Is provided.
또한, 고집적화에 따라 디자인룰이 서브 마이크론(sub micron)급 이하로 감소되면서 다층 금속배선이 적용되고, 화소수 증가에 의해 제조공정상의 문제로 발생되는 불량화소(defect pixel)를 리페어(repair)하기 위한 퓨즈박스(fuse box)가 구비된다. In addition, due to high integration, design rules are reduced to sub-micron level or less, and multilayer metallization is applied, and repairing defective pixels caused by manufacturing process problems due to an increase in the number of pixels. A fuse box is provided.
도 1a 및 도 1b는 퓨즈박스를 구비한 종래 이미지센서의 제조방법을 설명하기 위한 단면도이다.1A and 1B are cross-sectional views illustrating a method of manufacturing a conventional image sensor having a fuse box.
도 1a에 도시된 바와 같이, 퓨즈영역 및 패드영역이 정의되고, 퓨즈영역의 필드산화막(11) 상에는 폴리실리콘 퓨즈(12)가 형성되고, 절연막(13)의 개재하에 패드영역에는 서로 콘택된 제 1 내지 제 3 금속배선(14, 15, 16)의 다층 금속배선(100)이 형성되어 있는 반도체 기판(10) 상에 패시배이션(passivation) 산화막(17)을 형성한다. 그 다음, 폴리실리콘 퓨즈(12) 및 금속배선(100)을 노출시키는 통상의 패드 오픈 마스크(200)를 이용하여 폴리실리콘 퓨즈(12) 및 금속배선(100) 상의 산화막(17)을 식각하여, 도 1b에 도시된 바와 같이, 제 3 금속배선(16)의 일부를 오픈시켜 이후 패드(PAD1)로서 작용하도록 하고, 폴리실리콘 퓨즈(12) 상에는 산화막(15)을 소정 두께만큼 잔존시킨다.As shown in FIG. 1A, a fuse region and a pad region are defined, a polysilicon fuse 12 is formed on the field oxide film 11 of the fuse region, and the pad region is contacted with each other in the pad region through the insulating layer 13. A passivation oxide film 17 is formed on the semiconductor substrate 10 on which the multilayer metal wirings 100 of the first to third metal wirings 14, 15, and 16 are formed. Next, the oxide film 17 on the polysilicon fuse 12 and the metal wiring 100 is etched using the conventional pad open mask 200 exposing the polysilicon fuse 12 and the metal wiring 100. As shown in FIG. 1B, a part of the third metal wiring 16 is opened to serve as the pad PAD1, and the oxide film 15 is left on the polysilicon fuse 12 by a predetermined thickness.
이때, 패드영역에서는 제 3 금속배선(16)의 손상이 없도록 ARC(Anti Reflective Coating)층(미도시)까지만 식각이 수행되어야 하고, 퓨즈영역에서는 이후 레이저(laser) 리페어시 퓨즈 절단에러(cutting error)를 방지하기 위해 산화막 (17)이 적정두께, 예컨대 3000Å 정도의 두께로 잔존하여야 한다.In this case, etching may be performed only up to an anti-reflective coating (ARC) layer (not shown) in the pad region so as not to damage the third metal wiring 16, and in the fuse region, a fuse cutting error during laser repair. ), The oxide film 17 should remain at an appropriate thickness, for example, about 3000 mm3.
그러나, 제 3 금속배선(16)과 폴리실리콘 퓨즈(12) 사이의 큰 단차로 인하여 식각 시 패드영역의 제 3 금속배선(16)은 심하게 손상을 받게 되고 퓨즈영역의 잔존 산화막 두께의 균일성(uniformity)을 확보하기가 어려워서, 후속 패키지 시에는 와이어 본딩(wire bonding) 불량을 유발하고 레이저 리페어 시에는 퓨즈 절단에러를 유발함으로써, 결국 소자의 수율 및 신뢰성을 저하시키게 된다. However, due to the large step between the third metal wiring 16 and the polysilicon fuse 12, the third metal wiring 16 of the pad region is severely damaged during etching and the uniformity of the remaining oxide film thickness of the fuse region ( Uniformity is difficult to secure, resulting in poor wire bonding in subsequent packages and fuse breaks in laser repair, resulting in lower device yield and reliability.
본 발명은 종래의 문제점을 해결하기 위하여 제안된 것으로, 패드오픈 공정시 패드영역의 배선 손상을 방지하면서 퓨즈영역 잔존 산화막 두께의 균일성을 확보하여 와이어 본딩 불량 및 퓨즈 절단에러 등을 효과적으로 방지할 수 있는 이미지센서의 제조방법을 제공하는데 그 목적이 있다. The present invention has been proposed to solve the conventional problems, and it is possible to effectively prevent wire bonding defects and fuse cutting errors by ensuring uniformity of the remaining oxide layer thickness while preventing wiring damage of the pad region during the pad opening process. It is an object of the present invention to provide a method for manufacturing an image sensor.
상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 상기의 본 발명의 목적은 패드영역과 퓨즈영역이 정의되고 상부에 절연막이 형성된 반도체 기판을 준비하는 단계; 패드영역의 절연막 상에 금속배선을 형성함과 동시에 퓨즈영역의 절연막 상에 금속퓨즈를 형성하는 단계; 기판 전면 상에 패시배이션막을 형성하는 단계; 금속배선 및 금속 퓨즈 상에 소정 두께가 잔존하도록 패시배이션막을 제 1 식각하는 단계; 및 금속배선의 일부가 오픈되도록 패시배이션막을 제 2 식각하는 단계를 포함하는 이미지센서의 제조방법에 의해 달성될 수 있다.According to an aspect of the present invention for achieving the above technical problem, an object of the present invention comprises the steps of preparing a semiconductor substrate having a pad region and a fuse region defined and an insulating film formed thereon; Forming a metal fuse on the insulating film of the pad region and simultaneously forming a metal fuse on the insulating film of the fuse region; Forming a passivation film on the entire surface of the substrate; First etching the passivation film so that a predetermined thickness remains on the metal wiring and the metal fuse; And a second etching of the passivation film so that a part of the metal wiring is opened.
여기서, 제 1 식각은 상기 금속배선 및 금속퓨즈를 노출시키는 제 1 패드 오픈 마스크를 이용하여 패시배이션막이 3000Å 정도 잔존하도록 수행하고, 제 2 식각은 금속배선 만을 노출시키는 제 2 패드 오픈 마스크를 이용하여 수행한다.Here, the first etching is performed such that a passivation layer remains about 3000 Å using the first pad open mask exposing the metal wiring and the metal fuse, and the second etching uses a second pad open mask exposing only the metal wiring. Do it.
또한, 금속배선은 제 1 내지 제 3 금속배선이 순차적으로 콘택된 다층 금속배선으로 이루어지고, 금속 퓨즈는 상기 제 1 내지 제 3 금속배선 중 하나의 배선 형성시 동시에 형성한다.In addition, the metal wiring is made of a multilayer metal wiring in which the first to third metal wirings are sequentially contacted, and the metal fuses are formed simultaneously when the wiring of one of the first to third metal wirings is formed.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
도 1a 및 도 1b는 본 발명의 실시예에 따른 이미지센서의 제조방법을 설명하기 위한 단면도이다.1A and 1B are cross-sectional views illustrating a method of manufacturing an image sensor according to an exemplary embodiment of the present invention.
도 1a에 도시된 바와 같이, 퓨즈영역 및 패드영역이 정의되고 필드산화막 (21)이 형성된 반도체 기판(20) 상에 절연막(22)을 형성한 다음, 절연막(22) 상에 금속막을 증착하고 패터닝하여 패드영역에 제 1 금속배선(23A)을 형성함과 동시에 퓨즈영역에 금속 퓨즈(23B)를 형성한다. 즉, 제 1 금속배선(23A)과 퓨즈(23B)를 동시에 형성하기 때문에 이들 사이의 단차가 최소화될 수 있다. 그 후, 제 1 금속배선(23A)의 일부분, 예컨대 에지 부분 상부에 제 1 금속배선(23A)과 순차적으로 콘택하는 제 2 및 제 3 금속배선(24, 25)을 형성하여 다층의 금속배선(300)을 형성하고, 기판 전면 상에 패시배이션 산화막(26)을 형성한다.As shown in FIG. 1A, an insulating film 22 is formed on a semiconductor substrate 20 on which a fuse region and a pad region are defined and a field oxide film 21 is formed, and then a metal film is deposited and patterned on the insulating film 22. Thus, the first metal wiring 23A is formed in the pad region and the metal fuse 23B is formed in the fuse region. That is, since the first metal wiring 23A and the fuse 23B are formed at the same time, the step difference between them can be minimized. Thereafter, second and third metal wires 24 and 25 sequentially contacting the first metal wire 23A are formed on a portion of the first metal wire 23A, for example, the edge portion, thereby forming a multi-layered metal wire ( 300 is formed, and a passivation oxide film 26 is formed on the entire substrate.
그 다음, 제 1 금속배선(23A) 및 금속 퓨즈(23B)를 노출시키는 제 1 패드 오픈 마스크(400A)를 이용하여 제 1 금속배선(23A) 및 금속 퓨즈(23B) 상의 산화막 (26)을 제 1 식각하여, 도 2b에 도시된 바와 같이, 제 1 금속배선(23A) 및 금속 퓨즈(23B) 상에 적정 두께, 예컨대 3000Å 정도의 산화막(26)을 잔존시킨다.Next, the oxide film 26 on the first metal wiring 23A and the metal fuse 23B is removed by using the first pad open mask 400A exposing the first metal wiring 23A and the metal fuse 23B. After etching, as shown in FIG. 2B, the oxide film 26 having an appropriate thickness, for example, about 3000 kPa remains on the first metal wiring 23A and the metal fuse 23B.
그 후, 제 1 금속배선(23A)만을 노출시키는 제 2 패드 오픈 마스크(400B)를 이용하여 제 1 금속배선(23A) 상의 잔존 산화막(26)을 제 2 식각하여, 도 2c에 도시된 바와 같이, 제 1 금속배선(23B)의 다른 부분, 예컨대 중앙부분을 오픈시켜 이후 패드(PAD2)로서 작용하도록 한다.Thereafter, the remaining oxide film 26 on the first metal wiring 23A is second-etched using the second pad open mask 400B exposing only the first metal wiring 23A, as shown in FIG. 2C. The other part of the first metal wire 23B, for example, the center part, is opened to serve as the pad PAD2.
상기 실시예에 의하면, 배선과 퓨즈를 동시에 형성하여 이들 사이의 단차를 최소화시키고, 퓨즈 및 배선을 노출시키는 제 1 패드 오픈 마스크를 이용하여 퓨즈 및 배선 상에 적정 두께의 산화막이 잔존하도록 산화막을 제 1 식각한 후, 배선만을 노출시키는 제 2 패드 오픈 마스크를 이용하여 배선 상의 잔존 산화막을 제 2 식각하여 패드를 오픈시킴으로써, 배선 손상을 방지하면서 동시에 퓨즈 상에 적정 산화막 두께를 균일하게 확보할 수 있게 된다. 이에 따라, 패키지시 와이어 본딩 불량을 방지할 수 있고 레이저 리페이시 퓨즈 절단에러를 방지할 수 있으므로, 소자의 수율 및 신뢰성을 향상시킬 수 있게 된다.According to the above embodiment, the oxide film is formed so that an oxide film having an appropriate thickness remains on the fuse and the wiring by using a first pad open mask that simultaneously forms the wiring and the fuse to minimize the step between them and exposes the fuse and the wiring. After etching, the remaining oxide film on the wiring is etched second by using a second pad open mask that exposes only the wiring to open the pad, thereby preventing damage to the wiring and at the same time ensuring an appropriate thickness of the oxide film on the fuse. do. As a result, poor wire bonding at the time of packaging can be prevented, and laser fuse fuse cutting errors can be prevented, thereby improving yield and reliability of the device.
한편, 상기 실시예에서는 퓨즈를 제 1 금속배선 형성시 동시에 형성하고 제 1 금속배선을 패드로서 오픈시켰지만, 제 2 금속배선 또는 제 3 금속배선 형성시 퓨즈를 동시에 형성하고 이를 패드로서 오픈시킬 수도 있다.Meanwhile, in the above embodiment, the fuse is simultaneously formed when the first metal wiring is formed and the first metal wiring is opened as a pad, but the fuse may be simultaneously formed when the second metal wiring or the third metal wiring is formed and opened as a pad. .
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다. The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
전술한 본 발명은 패드오픈 공정시 패드영역의 배선 손상을 방지하면서 퓨즈영역 잔존 산화막 두께의 균일성을 확보하여 와이어 본딩 불량 및 퓨즈 절단에러 등을 효과적으로 방지할 수 있으므로, 소자의 수율 및 신뢰성을 향상시킬 수 있다. The present invention described above can prevent wire damage of the fuse region and uniformity of the remaining oxide layer thickness while preventing wiring damage of the pad region during the pad opening process, thereby effectively preventing wire bonding defects and fuse cutting errors, thereby improving the yield and reliability of the device. You can.
도 1a 및 도 1b는 종래의 이미지센서의 제조방법을 설명하기 위한 단면도.1A and 1B are cross-sectional views for explaining a method of manufacturing a conventional image sensor.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 이미지센서의 제조방법을 설명하기 위한 단면도.2A to 2C are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention.
※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing
20 : 반도체 기판 21 : 필드산화막20 semiconductor substrate 21 field oxide film
22 : 절연막 23A : 제 1 금속배선22: insulating film 23A: first metal wiring
23B : 금속퓨즈 24 : 제 2 금속배선23B: metal fuse 24: second metal wiring
25 : 제 3 금속배선 26 : 패시배이션막25: third metal wiring 26: passivation film
PAD2 : 패드 300 : 금속배선PAD2: Pad 300: Metal Wiring
400A : 제 1 패드 오픈 마스크400A: First Pad Open Mask
400B : 제 2 패드 오픈 마스크 400B: Second Pad Open Mask
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030075117A KR20050040015A (en) | 2003-10-27 | 2003-10-27 | Method of manufacturing image sensor having fuse box |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030075117A KR20050040015A (en) | 2003-10-27 | 2003-10-27 | Method of manufacturing image sensor having fuse box |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20050040015A true KR20050040015A (en) | 2005-05-03 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1020030075117A KR20050040015A (en) | 2003-10-27 | 2003-10-27 | Method of manufacturing image sensor having fuse box |
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| Country | Link |
|---|---|
| KR (1) | KR20050040015A (en) |
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2003
- 2003-10-27 KR KR1020030075117A patent/KR20050040015A/en not_active Application Discontinuation
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