KR20050031592A - A substrate for lcd and method for fabricating of the same - Google Patents

Abstract

An array substrate for an IPS(In-Plane Switching) LCD(Liquid Crystal Display) and a method of manufacturing the array substrate are provided to improve a viewing angle by omitting an over-coating layer. A plurality of gate wiring(102) are extended to one direction on a substrate and spaced horizontally to each other. Common wiring(106) is located at each spaced region of the gate wiring. A plurality of data wiring(114) vertically cross the gate wiring so as to define a plurality of pixel regions. A thin film transistor(T) is located at a point where the gate wiring and the data wiring cross with each other. A passivation layer is formed all over the substrate where the thin film transistor, the gate wiring and the data wiring are formed. A black matrix(124) is located at an upper part of the passivation layer that corresponds to the thin film transistor, the gate wiring and the data wiring. A color filter is patterned and thereby the black matrix, the first open part(B1) and the second open part(B2) are formed. A pixel electrode(128a,128b) is contacted to a drain electrode(120) exposed toward the first open part. A common electrode(130a,130b) is contacted to the common wiring through the second open part.

Description

Array substrate for transverse electric field type liquid crystal display device and its manufacturing method {A substrate for LCD and method for fabricating of the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a transverse electric field type liquid crystal display device having a color filter formed in an array substrate and having an electrode ground hole free structure, and a manufacturing method thereof.

In general, a liquid crystal display device displays an image by using optical anisotropy and birefringence characteristics of liquid crystal molecules. When an electric field is applied, the alignment of liquid crystals is changed, and the characteristics of light transmission vary according to the arrangement direction of the changed liquid crystals.

In general, a liquid crystal display device is formed by arranging two substrates on which the field generating electrodes are formed so that the surfaces on which the two electrodes are formed face each other, injecting a liquid crystal material between the two substrates, and then applying a voltage to the two electrodes. By moving the liquid crystal molecules by an electric field, the device expresses an image by the transmittance of light that varies accordingly.

1 is a view schematically showing a general liquid crystal display device.

As shown, a general color liquid crystal display 11 includes a color filter 7 and a color filter 7 including a black matrix 6 formed between a sub color filter 8 and each sub color filter 8. The upper substrate 5 having the common electrode 18 deposited thereon, the pixel region P, and the pixel electrode 17 and the switching element T formed in the pixel region, and the pixel region P The liquid crystal 14 is filled between the lower substrate 22 and the upper substrate 5 and the lower substrate 22 on which array wiring is formed.

The lower substrate 22 is also referred to as an array substrate, and the thin film transistor T, which is a switching element, is positioned in a matrix type, and the gate wiring 13 crosses the plurality of thin film transistors TFT. ) And data wirings 15 are formed.

In this case, the pixel area P is an area defined by the gate wiring 13 and the data wiring 15 intersecting. A transparent pixel electrode 17 is formed on the pixel area P as described above.

The pixel electrode 17 uses a transparent conductive metal having a relatively high transmittance of light, such as indium-tin-oxide (ITO).

A storage capacitor C connected in parallel with the pixel electrode 17 is formed on the gate wiring 13, and a part of the gate wiring 13 is used as the first electrode of the storage capacitor C, and a second As the electrode, an island-like metal layer 30 formed of the same material as the source and drain electrodes is used.

In this case, the island-shaped metal layer 30 is configured to be in contact with the pixel electrode 17 to receive a signal of the pixel electrode.

As described above, when the upper color filter substrate 5 and the lower array substrate 22 are bonded to each other to produce a liquid crystal panel, light leakage defects due to the bonding error between the color filter substrate 5 and the array substrate 22 may be reduced. It is very likely to occur.

Therefore, as shown in FIG. 2, a liquid crystal display device including a color filter and a black matrix on an array substrate at a time has been proposed.

FIG. 2 is a plan view schematically illustrating a configuration of an array substrate for a liquid crystal display device having a color filter on TFT (COT) structure according to the related art.

As shown, a gate wiring 54 is formed on the substrate G1 in one direction and includes a gate pad 58 at one end thereof, and extends perpendicularly to the gate wiring 54 and at one end thereof. The data line 66 including the data pad 68 is constructed.

The region defined by the intersection of the data line 66 and the gate line 54 is called a pixel area P. FIG.

The thin film transistor T including the gate electrode 52, the semiconductor layer 60, the source electrode 62, and the drain electrode 64 is formed at the intersection of the gate line 54 and the data line 66. .

In the above-described configuration of the thin film transistor T, the gate electrode 52 is connected to the gate line 54, and the source electrode 62 is connected to the data line 66.

In the pixel region P, a transparent pixel electrode 76 extending to the gate line 54 that passes through the upper portion of the pixel region P while contacting the drain electrode 64 is formed. On the upper portion of the data pad 68, island-shaped transparent gate pad electrodes 78 and data pad electrodes 80 which are in contact with them are formed.

A storage capacitor C is formed on a portion of the gate line 54 passing through the pixel area P, and a portion of the gate line 54 is formed as the first electrode of the storage capacitor C (point hatching area). And an island-shaped metal layer 67 formed between the gate wiring 54 and an insulating film (not shown) and configured to be in contact with an extension of the pixel electrode 76 as a second electrode. do.

In order to form the COT structure described above, the black matrix BM is formed corresponding to the thin film transistor T, and the color filters 72a, 72b, red, green, and red are formed in the plurality of pixel regions P. 72c) is constructed sequentially.

Hereinafter, a structure of a liquid crystal display device including an array substrate having a COT structure planarly configured as described above with reference to FIG. 3 will be described.

FIG. 3 is a cross-sectional view of a conventional COT structure liquid crystal display panel shown by cutting II-II of FIG. 2 and referring to the same.

As shown in the drawing, in the conventional vertical field type COT structure liquid crystal display device L, the first substrate G1 and the second substrate G2 are configured to be spaced a predetermined distance apart, and the array is formed on the first substrate G1. The wirings 54 and 66, the switching element T, and the pixel electrode 76 are formed on one surface of the second substrate G2 facing the first substrate G1. 76, together with a transparent common electrode 92 forming a potential difference is constructed.

The configuration of the first substrate G1 will be described in detail. The first substrate G1 includes a switching area S, a pixel area P, a storage area C, and a pad part D. FIG.

One side of the pixel region P and the other side perpendicular to the pixel region P are formed by vertically intersecting a gate line 54 and a data line 66. A thin film transistor is disposed in a switching area that is an intersection point of the two lines 54 and 66. (T) is comprised.

The thin film transistor T includes a gate electrode 52, a semiconductor layer 60, a source electrode 62, and a drain electrode 64.

At one end of the gate line 54 and the data line 66, a gate pad (not shown) and a data pad 68 are formed corresponding to the pad portion D. FIG.

A portion of the gate wiring 54 passing through a portion of the pixel region P is used as the first electrode in the storage region C, and the source and drain electrodes 62 and 64 are disposed on the gate wiring 54. A storage capacitor configured to second electrode the island-shaped metal layer 67 formed in the same manner is constructed.

An inorganic insulating layer 70 formed on the front surface of the substrate G1 including the gate line 54 and the data line 66, and formed of one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ). This is made up.

The inorganic insulating film 70 is patterned to primarily form the drain electrode 64, the metal layer 67 on the gate wiring 54, a gate pad (not shown), and a data pad (not shown). The first, second, and third contact holes CH1, CH2, and CH3 exposing the first and second contact holes are formed.

The red, green, and blue color filters 72a, 72b (not shown) are sequentially formed on the inorganic insulating layer 70 to correspond to each pixel P.

Next, a black matrix BM is formed corresponding to the thin film transistor T.

An over coating layer 74 coated with a transparent organic insulating material to planarize the substrate G1 on the substrate G1 on which the color filters 72a and 72b and the black matrix BM are formed. The overcoating layer 74 includes fourth, fifth and sixth contact holes CH4 and CH5 that are wider than the first, second and third contact holes CH1, CH2 and CH3. , CH6).

A transparent pixel electrode 76 in contact with the drain electrode 64 exposed through the fourth contact hole CH4 is formed in the pixel region P, and the pixel electrode 76 is positioned on the gate line 54. It extends to the island-shaped metal layer 67 and is configured to contact it through the fifth contact hole CH5.

Subsequently, a data pad electrode 80 is formed on the data pad 68 to contact the data pad through the sixth contact hole CH6. Although not shown, the gate pad (not shown) may also be configured to contact an island-shaped transparent gate pad electrode (not shown) through a contact hole (not shown).

As shown in the drawing, a common electrode 92 transparent to the entire surface of the substrate G2 is formed on one surface of the first substrate G1 configured as described above and the second substrate G2 bonded through the sealant 96. .

A spacer SP is disposed between the first and second substrates G1 and G2 to maintain a gap between the two substrates. After the two substrates G1 and G2 are bonded together, an upper portion is formed. A process of cutting a portion of the substrate G2 to expose the gate pad electrode (not shown) and the data pad electrode 80 is performed.

The COT structured liquid crystal display device manufactured as described above has excellent characteristics such as transmittance and aperture ratio in a vertical electric field system that drives the liquid crystal by an electric field applied between the common electrode and the pixel electrode.

However, the liquid crystal drive by the electric field applied up-down has a disadvantage that the viewing angle characteristics are not excellent.

In addition, by forming a thick overcoat layer on the color filter and the black matrix, the inclination of the contact hole formed by etching the overcoat layer is greatly increased by the thickness of the overcoat layer, so that the area of the contact hole may encroach the opening area.

The present invention has been proposed to solve the above problems, and proposes an array substrate for a transverse electric field type liquid crystal display device having a COT structure and a method of manufacturing the same in order to improve the viewing angle. , An " overcoat layer ") is not formed.

That is, by eliminating the overcoating layer, by forming a contact hole in the overcoating layer, it is possible to reduce the disclination region generated by the contact hole, thereby improving the aperture ratio.

Therefore, the present invention proposes an array substrate for a COT structure transverse electric field liquid crystal display device that does not require an overcoating layer, and aims to manufacture a transverse electric field liquid crystal display device having a high opening ratio and improved viewing angle characteristics in a simple process. do.

An array substrate for a transverse electric field type liquid crystal display device according to a first aspect of the present invention for achieving the above object is A plurality of gate lines extending in one direction on the substrate and spaced apart from each other in parallel; A common wiring positioned in each of the separation regions of the plurality of gate wirings; A plurality of data lines defining a plurality of pixel regions by crossing the plurality of gate lines perpendicularly; A thin film transistor positioned at an intersection point of the gate line and the data line; A passivation layer formed on an entire surface of the substrate on which the thin film transistor, the gate wiring and the data wiring are formed; A black matrix on the passivation layer corresponding to the thin film transistor, the gate wiring, and the data wiring; Corresponding to the plurality of pixel areas, red, green, and blue are sequentially formed, and corners have a corner of "??". Or a color filter patterned in an "L" shape to form a first opening and a second opening of the black matrix and the "??"shape; A pixel electrode in contact with the drain electrode exposed by the first open part; and a common electrode spaced in parallel with the pixel electrode and in contact with the common wiring through the second open part.

The thin film transistor is spaced apart in parallel with the gate electrode connected to the gate wiring, the semiconductor layer positioned above the gate wiring, the source electrode connected with the data wiring, and the source electrode, and extends over the common wiring. And a drain electrode formed.

A storage capacitor is further configured, wherein the extended drain electrode is a first electrode, and a lower common wiring overlapping the drain electrode is a second electrode.

The pixel electrode includes a horizontal portion in contact with the pixel electrode and a plurality of vertical portions extending vertically from the horizontal portion to the pixel region, and the common electrode includes the horizontal portion and the horizontal portion in contact with the common wiring. Extend vertically to be spaced apart in parallel to the vertical portion of the pixel electrode.

The common wiring has a plurality of rectangular closed loops connected between the spaced regions of the gate wiring so as to be configured in a direction parallel to the gate wiring.

The common wiring is formed of a rectangular closed loop corresponding to the pixel region.

A gate pad is formed at one end of the gate line, a data pad is formed at one end of the data line, and an extension portion of the semiconductor layer extending from the semiconductor layer to the lower portion of the data line and the data pad is further configured.

The protective layer corresponding to the first and second open portions, the gate pad and the data pad may be completely removed or partially removed.

Columnar column spacers may be further configured to correspond to the first opening part and the second opening part, and the column spacers may be configured to be distracting to correspond to the pixel area.

In this case, the first open portion or the second open portion in which the column spacer is not configured is filled with the same material as the column spacer.

The semiconductor layer and the extension portion of the semiconductor layer may be formed by being exposed to the periphery of the source and drain electrodes, the data line, and the data pad.

According to an aspect of the present invention, there is provided a method of fabricating an array substrate for a transverse electric field type liquid crystal display device, including a plurality of gate wires extending in one direction and spaced in parallel with each other, and located in a spaced area between the gate wires and closed in a rectangular shape. A first mask process step of forming a common wiring having a plurality of loop shapes connected to each other in a direction parallel to the gate wiring; Forming a gate insulating film on the gate wiring and the common wiring; A second mask process step of forming a semiconductor layer on an upper portion of the gate insulating layer, the gate wiring corresponding to a portion of the upper portion; A third mask process of forming a data line defining a plurality of pixel regions including the quadrangular closed loops perpendicularly intersecting the gate line, a source electrode connected to the data line, and a drain electrode spaced apart from the source electrode; Steps; Forming a protective film on an entire surface of the substrate on which the source and drain electrodes and the data wiring are formed; A fourth mask process step of forming a black matrix corresponding to the source and drain electrodes, the gate wiring, and the data wiring; Red, green, and blue are sequentially formed in correspondence with the pixel area, and corners are patterned in a shape of "a" or "b" to form the black matrix, the first open part and the second open part of the "ㅁ" shape. A fifth mask process step of forming a filter;

Using the black matrix and the color filter as an etch stop layer, etching a lower passivation layer to expose a lower drain electrode and a common wiring through the first open part and the second open part; A sixth mask process step of forming a pixel electrode in contact with the drain electrode exposed to the first open part and a common electrode spaced apart from the pixel electrode in parallel, and in contact with the common wiring through the second open part; Include.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

First Embodiment

A first embodiment of the present invention is characterized by suggesting a structure of an array substrate for a transverse electric field type liquid crystal display device having a COT structure and a method of manufacturing the same.

4 is an enlarged plan view illustrating a part of an array substrate for a transverse electric field type liquid crystal display device having a C0T (color filter on TFT) structure according to the present invention.

As shown, the gate wiring 102 extending in one direction on the substrate 100 and including the gate pad 104 at one end thereof, and extending in a direction perpendicular to the gate wiring 102, The data line 114 including the data pad 116 is formed at the end.

A region defined by the intersection of the gate wiring 102 and the data wiring 114 is called a pixel region P. The pixel region P has a common closed loop shape around the pixel region P. The wiring 106 is formed.

At this time, the common wiring 106 formed in each pixel region P is connected to each other.

At the intersection of the gate wiring 102 and the data wiring 114, the gate electrode 102 (a part of the gate wiring is used, the same number is used), the semiconductor layer 110, the source electrode 118, and the drain electrode 120 are disposed. A thin film transistor T is formed, and an extension part 112 extending from the semiconductor layer 110 is formed under the data line 114 to cause the extension part 112 to have a data line 114. And enhance the adhesive properties of the data pad 116.

In this case, the drain electrode 120 extends in a bar shape overlapping with each other on a part of the common wiring 106 positioned in close proximity to the gate wiring 102.

As described above, the lattice-like black matrix 124 is formed on the substrate 100 including the gate wiring 102, the data wiring 114, and the thin film transistor T.

Red, green, and blue color filters 126a, 126b (not shown) are sequentially formed in the pixel region P exposed between the black matrices 124. In this case, the color filters 126a and 126b are formed in a quadrangular shape. The color filters 126a are formed by patterning two corners A1 and A2 corresponding to one diagonal direction in a “b” or “a” shape. The first open portion B1 and the second open portion B2 having a shape of “” are formed to meet the two vertical sides of the black matrix 124.

The lower common line 106 is exposed through the second open part B2, and a part of the extended drain electrode 120 is exposed through the first open part B1.

The common electrodes 130a and 130b and the pixel electrodes 128a and 128b are formed on the color filters 126a and 126b, and the common electrodes 130a and 130b are configured to form the second open part B2. A horizontal portion 130a in contact with the common wiring 106 and a plurality of vertical portions 130b extending vertically from the horizontal portion 130a, wherein the pixel electrodes 128a and 128b are formed in the first opening portion. a horizontal portion 128a contacting a portion of the drain electrode 120 extending through (b1) and a plurality of vertical portions 128b extending from the horizontal portion 128a between the common electrode 130b and spaced in parallel therewith. It is composed.

The first open part B1 and the second open part B2 form columnar spacers SP for maintaining a gap of the liquid crystal panel.

With the above configuration, it is possible to configure the color filter on thin film transistor type transverse electric field type color filter according to the present invention.

As described above, the common electrode 130a and 130b and the pixel electrode 128a and 128b may be connected to the common wiring 106 as described above. In order to contact the drain electrode 120, a contact hole free structure having no separate contact hole is introduced.

In the above-described configuration, a common voltage is applied to the common electrodes 130a and 130b by grounding the common electrodes 130a and 130b and the common wiring 106 for each pixel.

However, in addition to the above-described configuration, the common electrodes 130a and 130b and the common wiring 106 are not connected to each pixel P. Instead, the common electrodes 130a and 130b and the common wiring are formed outside the array substrate. It is also possible to configure the 106 directly.

In this case, the common electrodes 130a and 130b may be configured to be connected to both common electrodes positioned in neighboring pixels.

Therefore, if the above-described configuration is applied, there is an advantage in that it is not necessary to form a second open part for connecting the common electrode and the common wiring to each pixel P.

5A to 5G, 6A to 6G, 7A to 7F, and 8A to 8F, an array substrate for a transverse electric field type liquid crystal display device having a COT structure according to a first embodiment of the present invention. It describes a method for producing.

5A to 5G are process plan views according to the process sequence according to the first embodiment of the present invention, and FIGS. 6A to 6G, 7A to 7F, and 8A to 8F are angles of FIGS. 5A to 5G. The top view is a cross-sectional view taken along the line IV-IV, V-V, VI-VI. In this case, FIG. 7 is a cross-sectional view of the gate pad portion and FIG. 8 is a cross-sectional view of the data pad portion.

5A, 6A, 7A, and 8A, aluminum (Al), aluminum alloy (AlNd), tungsten (W), chromium (Cr), titanium (Ti), and the like on the insulating substrate 100 One or more metals selected from the group of conductive metals including conductive metals such as tantalum (Ta) and molybdenum (Mo) are deposited and patterned in a first mask process to extend the gate pad 104 in one direction and at one end thereof. A plurality of gate wirings 102 are formed.

At the same time, a plurality of quadrangular shapes are formed between the plurality of gate lines 102 to form a common line 106 having a structure connected in a direction parallel to the gate lines 102.

One selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) on the entire surface of the substrate 100 on which the gate wiring 102, the gate pad 104, and the common wiring 106 are formed. Is deposited to form a gate insulating film 108.

5B, 6B, 7B, and 8B, pure amorphous silicon (a-Si: H) and amorphous silicon (n + a) containing impurities are formed on the entire surface of the substrate 100 on which the gate insulating layer 108 is formed. -Si: H) is deposited and patterned by a second mask process to form a semiconductor layer 110 including an active layer 110a and an ohmic contact layer 110b on a portion of the gate wiring 102. At the same time, the semiconductor layer 110 forms an extension 112 of the semiconductor layer extending in a direction perpendicular to the gate wiring 102.

In this case, the gate wiring 102 of the portion overlapping the semiconductor layer 110 functions as a gate electrode.

As shown in FIGS. 5C, 6C, 7C, and 8C, aluminum (Al) and aluminum alloy (AlNd) are formed on the entire surface of the substrate 100 on which the semiconductor layer 110 and the extension part 112 of the semiconductor layer are formed. ), By depositing one or more metals selected from the group of conductive metals including tungsten (W), chromium (Cr), titanium (Ti), tantalum (Ta) and molybdenum (Mo) and patterning a third mask process, A data line 114 extending over the extension portion of the semiconductor layer in a planar overlapping manner and including a data pad 116 at one end thereof, and a semiconductor layer over the gate line 102 in the data line 114. A source electrode 118 extending over the 110 and a drain electrode 120 spaced apart from each other by a predetermined interval and extending in a direction parallel to the gate wiring 102 are formed.

In this case, the data line 120 is positioned between a plurality of quadrangles in the configuration of the common wiring 106 previously formed, and the drain electrode 120 is formed to overlap one side of the quadrangle.

Therefore, a portion where the drain electrode 120 and the common wiring 106 overlap each other forms a storage region C (point hatching region) in which storage capacitance is generated.

Subsequently, the ohmic contact layer 110b exposed between the source and drain electrodes 118 and 120 is removed to expose the lower active layer 110a.

As shown in FIGS. 5D, 6D, 7D, and 8D, silicon nitride (SiN _X ) and silicon oxide ( One selected from the group of inorganic insulating materials including SiO ₂ ) is deposited to form a passivation layer 122.

The passivation layer 122 is configured to protect the previously exposed active layer 110b. Furthermore, the passivation layer 122 serves to prevent the surface of the active layer 110b from coming into contact with the organic layer formed thereafter.

This is because the active layer 110b and the organic layer have poor interface characteristics, so that a trap level for trapping electrons is generated. This phenomenon causes deterioration of operating characteristics of the thin film transistor.

Subsequently, an opaque organic insulating material is coated on the entire surface of the substrate 100 on which the passivation layer 122 is formed, and is patterned by a fourth mask process to form an upper portion corresponding to the gate wiring 102 and the data wiring 114. The lattice-shaped black matrix 124 is formed.

In this case, the organic material forming the black matrix 124 should be a material having an optical density of 3 or more, and at the same time, preferably have a high resistance value of 10 ¹³ Ω / cm 2 or more.

Only having the high resistance value as described above can prevent the delay of the signal flowing through the data and gate wiring 114,102.

As shown in FIGS. 5E, 6E, 7E, and 8E, a plurality of regions exposed between the lattice black matrices 124, that is, the plurality of pixel regions P, are red through a fifth mask process. And green and blue color filters 126a, 126b (not shown) are sequentially formed in any order.

At this time, each of the color filters 126a, 126b (not shown) by patterning the corners (A1, A2) of the diagonal direction in which the source and drain electrodes 118, 120 are not located in a "b" or "b" shape, this shape The corners of the color filter and the vertical two sides of the black matrix 124 meet to form a first open portion B1 and a second open portion B2 exposing the lower passivation layer 122 in the form of "ㅁ".

In more detail, the first open part B1 is positioned to correspond to one end of the extended drain electrode 120, and the second open part B2 is disposed in a direction opposite to the drain electrode 120. The common wiring 106 is positioned corresponding to a part of the common wiring 106.

Subsequently, the black matrix 124 and the color filters 126a and 126b (not shown) are used as anti-etching films to remove the protective film (and gate insulating film) 122 of the portions exposed to the open portions B1 and B2. The process of exposing a part of the drain electrode 120 corresponding to the first open part B1 and exposing a part of the lower common wiring 106 through the second open part B2 is performed.

In this case, the first embodiment of the present invention is characterized by not using a mask in the process of exposing the lower drain electrode 120 and the common wiring 106 through the first and second open portions B1 and B2. Will not.

Therefore, as shown in FIGS. 7E and 8E, the process proceeds to the shape in which both the gate pad 104 and the data pad 116 are exposed.

 5F, 6F, and 7F, the indium tin oxide (ITO) and the indium zinc oxide are formed on the entire surface of the substrate 100 on which the color filters 126a and 126b are formed. And depositing a selected one of a group of transparent conductive metal materials including (IZO) and patterning it by a fifth mask process so that the transparent pixel electrodes 128a and 128b contact the exposed drain electrode 120 and the exposed common electrode. Transparent common electrodes 130a and 130b in contact with the wiring 106 are formed.

The shape of the pixel electrodes 128a and 128b and the common electrodes 130a and 130b will be described in detail. The pixel electrodes 128a and 128b may include a horizontal portion 128a in contact with the drain electrode 120 and a horizontal portion. A plurality of vertical portions 128b extending from the 128a to the pixel region P, and the common electrodes 130a and 130b may include a horizontal portion 130a in contact with the common wiring 106 and a horizontal portion. A plurality of vertical portions 130b extended vertically to the pixel region P at 30a and spaced in parallel with the pixel electrode 128b are formed.

The pixel electrodes 128a and 128b and the common electrodes 130a and 130b are formed, and the island-shaped gate pad electrodes 132 contacting the exposed gate pads 102, the data pads 116, and the like. An island-shaped data pad electrode 134 is formed in contact.

As shown in FIGS. 5G and 6G, a transparent organic insulating material is coated on the entire surface of the substrate 100 on which the pixel electrodes 128a and 128b and the common electrodes 130a and 130b are formed, and then a seventh mask process is performed. In addition, the columnar spacers CS are formed to correspond to the first opening part B1 and the second opening part B2.

The spacer CS may serve to maintain a gap between the two substrates when the first substrate manufactured as described above and the second substrate are bonded, although not illustrated.

Unlike the conventional example, the aforementioned process has an advantage of ensuring an opening ratio because no overcoating layer is used on the color filter.

This will be described with reference to FIG. 9.

9 is an enlarged cross-sectional view illustrating the shape of the contact hole CH when the overcoating layer is used.

In more detail through the drawings, when the over-coating layer (OC) is used on the color filter CF, the color filter layer of the COT structure is located on the top of the thin film transistor (not shown) to use the over-coating layer If so, the total organic film thickness is 3-4 μm (ie, color filter 1.5-2.0 μm, overcoating layer> 1.5 μm).

However, in order to expose the drain electrode and the common wiring exposed in correspondence with the open portion 1 and the open portion 2 through the overcoat layer OC, a contact hole CH must be formed in the overcoat layer. During formation, the foreground area DC due to the organic layer stepped inclinations K1 and K2 becomes very large.

Therefore, when forming the contact hole CH, the area of the drain electrode and the region of the common wiring overlapping the drain electrode should be increased to cover the foreground area DC.

Therefore, as in the case of the present invention described above, if the overcoating layer is not used in the COT structure, the foreground area is relatively small, which is very advantageous for the aperture ratio.

Through the above process, the array substrate for the color filter on thin film transistor type transverse electric field type liquid crystal display device according to the present invention can be formed.

Second Embodiment

In the above-described first embodiment, the process of forming the first open part and the second open part is performed by removing the lower insulating layer using the black matrix and the color filter as an etch stop layer. A process of forming the open part 1 and the open part 2 through the photo mask process will be described.

On the other hand, with reference to 10a to 10e, 11a to 11d and 12a to 12d, the manufacturing process of the array substrate for a transverse electric field type liquid crystal display device of the COT structure according to the second embodiment of the present invention will be described. .

10A to 10E, 11A to 11D, and 12A to 12D are cut along the lines IV-IV, V-V, and VI-VI of FIG. 4, and are shown in a process sequence according to a second embodiment of the present invention. One process cross section. (This process is the same from the process of the first embodiment to the process of forming the color filter, so it will be omitted and the subsequent process will be described.)

10A, 11A, and 12A, a thin film transistor T including a gate electrode 202, a semiconductor layer 210, a source electrode 218, and a drain electrode 220 on a substrate 200. ), And the gate line 202 and the data line 214 are formed by crossing the thin film transistor T therebetween.

In this case, a gate pad 212 and a data pad 216 are formed at one end of the gate line 202 and the data line 214, respectively.

As described above, an opaque organic insulating material is coated on the entire surface of the substrate 200 on which the thin film transistor T, the gate wirings, and the data wirings 202 and 214 are formed, and then patterned to form the thin film transistor T and the data wiring ( A grid-like black matrix 224 is formed corresponding to the 214 and the gate wiring 202.

The color filters 226a (not shown, not shown) of the red, green, and red colors are formed through a fifth mask process corresponding to the plurality of regions exposed between the grid-shaped black matrixes 224, that is, the plurality of pixel regions P. FIG. Formed sequentially in any order.

At this time, each of the color filters 226a (not shown, not shown) is patterned with a diagonal edge (A1, A2 in FIG. 4) in which the source and drain electrodes 218 and 220 are not positioned to be "a" or "b". The first open part B1 and the second open part B2 exposing the color filter edges of the shape and the two vertical sides of the black matrix 224 to expose the lower passivation layer 122 in the shape of "ㅁ". Form.

In more detail, the first open part B1 is positioned to correspond to one end of the extended drain electrode 220, and the second open part B2 is disposed in a direction opposite to the drain electrode 220. The common wiring 206 is positioned corresponding to a part of the common wiring 206.

Next, as shown, a photoresist (pohto-resist) is applied to the entire surface of the substrate 200 on which the black matrix 224 and the color filter 226a (not shown, not shown) is formed to form the photosensitive layer 228. To form.

In this case, the photoresist will be described with an example of having a positive characteristic.

The mask M including the transmissive part F1 and the blocking part F2 is positioned on the spaced upper portion of the substrate 200 on which the photosensitive layer 228 is formed.

The portion corresponding to the transmissive portion F1 is a portion corresponding to the first open portion B1 and the second open portion B2, and the gate pad 204 and the data pad 216.

As shown in FIGS. 10B, 11B, and 12B, when the light is irradiated to the upper portion of the mask M, the process of exposing the lower photosensitive layer 228 and developing the exposed photosensitive layer is performed. The photosensitive layer corresponding to the transmissive portion F1 of the mask (M of FIGS. 10A, 11A, and 12A) is removed to expose the lower passivation layer 222.

Next, a process of removing the exposed protective film 222 is performed.

10C, 11C, and 12C, the portion where the protective layer 222 is removed may expose the first contact hole CH1 exposing the lower drain electrode 220 and the lower common wiring 106. The second contact hole CH2, the third contact hole CH3 exposing the gate pad 204, and the fourth contact hole CH4 exposing the data pad 216 are formed.

Next, as shown in the plan view of FIG. 10D1 and in FIGS. 10D2, 11D, and 12D, the substrate on which the first, second, third, and fourth contact holes CH1, CH2, CH3, and CH4 are formed ( A pixel electrode contacting the drain electrode 220 by depositing and patterning one selected from a group of transparent conductive metals including indium tin oxide (ITO) and indium zinc oxide (IZ0) on the front surface of the substrate 200. Common electrodes 232a and 232b in contact with 230a and 230b and the common wiring 206, gate pad electrodes 234 in contact with the gate pad 204, and data in contact with the data pad 216. The pad electrode 236 is formed.

In this case, the pixel electrodes 230a and 230b may include a horizontal portion 230a in contact with the drain electrode 220 and a plurality of vertical portions 230b extending from the horizontal portion to the pixel region P. The common electrodes 232a and 232b also have a horizontal portion 232a in contact with the common wiring 206 and a vertical portion 232b extending from the horizontal portion 232a to the pixel electrode 230b and spaced in parallel therewith. It consists of.

Next, as shown in FIG. 10E, a transparent organic insulating material is coated on the entire surface of the substrate 200 on which the common electrodes 232a and 232b, the pixel electrodes 230a and 230b, and the like are formed, and then patterned. The columnar column spacer CS is formed to correspond to the first open part B1 and the second open part B2.

Through the above-described process, an array substrate for a transverse electric field type liquid crystal display device having a COT structure according to a second embodiment of the present invention can be manufactured.

Third Embodiment

    The third embodiment of the present invention is characterized by simplifying the entire mask process using an exposure process using diffraction exposure (or half tone mask) during the exposure process, and thus, an array substrate for a transverse electric field type liquid crystal display device having a COT structure. It characterized in that to form.

13A to 13F, 14A to 14E, and 15A to 15E are cut along the IV-IV, V-V, VI-VI of FIG. 4 of the present invention, and the process sequence according to the third embodiment of the present invention. The process cross-sectional view shown in accordance with FIG.

As shown in FIGS. 13A, 14A, and 15A, aluminum (Al), aluminum alloy (AlNd), tungsten (W), chromium (Cr), titanium (Ti), and tantalum (Ta) are formed on the insulating substrate 300. ), One or more metals selected from the group of conductive metals including conductive metals such as molybdenum (Mo) are deposited and patterned in a first mask process so as to include a gate pad 304 extending in one direction and at one end thereof. A plurality of gate lines 302 spaced apart in parallel by a predetermined interval are formed.

At the same time, a plurality of quadrangular shapes are formed between the plurality of gate lines 302 to form a common line 306 having a structure connected in a direction parallel to the gate lines 302.

One selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) on the entire surface of the substrate 300 on which the gate wiring 302, the gate pad 304, and the common wiring 306 are formed. Is deposited to form a gate insulating film 308.

Successively, the amorphous silicon layer 310 in which pure amorphous silicon (a-Si: H) is deposited on the gate insulating layer 308, and the amorphous silicon (n + a-Si: H) containing impurities are deposited. An impurity amorphous silicon layer 312 is formed.

Next, aluminum (Al), aluminum alloy (AlNd), tungsten (W), chromium (Cr), titanium (Ti), tantalum (Ta), and molybdenum (Mo) on the entire surface of the substrate 300 on which the impurity amorphous silicon is formed. The conductive metal layer 314 is formed by depositing one or more metals selected from the group of conductive metals including the (C).

Hereinafter, FIGS. 13B1 to 13B5, 14B1 to 14B5, and 15B1 to 15B5 show a second mask process.

As shown in FIGS. 13B1, 14B1, and 15B1, the substrate 300 on which the gate insulating layer 308, the pure amorphous silicon layer 310, the impurity amorphous silicon layer 312, and the conductive metal layer 314 are formed. A photoresist (positive characteristic) is applied to the entire surface of the C) to form the photosensitive layer 316.

Subsequently, a mask M including the transmissive part F1, the blocking part F2, and the transflective part F3 is positioned on the spaced upper portion of the substrate 300 on which the photosensitive layer 316 is formed.

In this case, the transflective portion F3 of the mask M corresponds to the upper portion corresponding to the gate electrode 302 so as to correspond to the center of the gate electrode 302, and the cutoff portion is disposed around the transflective portion F3. Let (F2) correspond.

In addition, the blocking part F2 may correspond to the shape extending in a direction perpendicular to the gate line 302.

In this case, the transflective portion F3 has a function of lowering the light intensity to 1/2 or less compared to the transmissive portion F1. For this purpose, the transflective portion F3 has a slit shape or translucent shape. It can be formed into a film.

Next, a process of exposing and developing the lower photosensitive layer 316 by irradiating light from the upper portion of the mask M is performed.

As shown in FIGS. 13B2, 14B2, and 15B2, when the process of developing the photosensitive layer is performed, a portion corresponding to the blocking portion of the mask remains, and the rest is removed by the developer.

Accordingly, a first photosensitive layer pattern 318a is left on the gate electrode 302, and a second photosensitive layer pattern 318b extending in a direction perpendicular to the gate wiring 302 remains in the gate pad part. The lower conductive metal layer 314 is exposed between the first and second photosensitive layers 318a and 318b.

The first photosensitive layer pattern 318a is formed to have a different height by partially removing a portion corresponding to the transflective portion of the mask.

As shown in FIGS. 13B3, 14B3, and 15B3, when the metal layers exposed to the lower portions of the first photosensitive layer pattern and the second photosensitive layer patterns 318a and 318b are removed, the first photosensitive layer 318a is removed. The first metal pattern 320a and the second metal pattern 320b remain under the second photosensitive layer 318b.

In this case, the second metal pattern 320b also has a shape extending from the first metal pattern 320a in a direction perpendicular to the gate wiring 302 by the second photosensitive layer 318b.

Subsequently, as shown in FIGS. 13B1, 14B1 and 15B1, a process of dry etching the lower impurity amorphous silicon layer and the pure amorphous silicon layer exposed between the first and second metal patterns 320a and 320b is performed. .

Next, an ashing process is performed to completely remove the low height portion of the first photosensitive layer 318a, and the lower first metal pattern corresponding to the low height portion of the photosensitive layer 318a. The process of exposing 320a is performed.

During the above-described ashing process, the heights of the first and second photosensitive layers 318a and 318b are lowered as a whole, and portions corresponding to the periphery L of the first and second metal patterns 320a and 320b are formed. The lower first and second metal patterns 320a and 320b are exposed to be removed.

Next, as illustrated in FIGS. 13B5, 14B5, and 15B5, the first and second metal patterns 320a and 320b exposed between the first and second photosensitive layers 318a and 318b are once again removed. Proceed with the process.

 When the first and second metal patterns exposed between the photosensitive layers are removed, a source electrode 320 and a drain electrode 322 spaced apart to correspond to an upper portion of the gate electrode 302 are formed, and the source electrode ( A data line 324 is formed at 320 and extends in a direction perpendicular to the gate line 302 and includes a data pad 326 at one end thereof.

At the same time, a first active pattern 328 capable of dividing its functions into an active layer 328a and an ohmic contact layer 328b is disposed below the source and drain electrodes 320 and 322, and the data line and the first active pattern. Second active patterns 330 extending below the data pads 324 and 326 are formed.

The second active pattern 330 serves to enhance the adhesive property of the data line 324 formed thereon.

In this case, the drain electrode 320 extends in a direction parallel to the gate line 302, and overlaps the lower common line 306.

Accordingly, the storage capacitor C having the common wiring 306 as the first electrode and the drain electrode 322 overlapping the second electrode is formed.

After the source and drain electrodes 320 and 322 are formed, an impurity amorphous silicon layer exposed between the source and drain electrodes 320 and 322 is removed to expose the lower active layer 328a.

In the above, the process of simultaneously forming the active pattern 328, the source and drain electrodes 320 and 322, and the data line 324 through the second mask process has been described.

13C, 14C, and 15C, silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) are formed on the entire surface of the substrate 300 on which the source and drain electrodes 320 and 322 and the data line 324 are formed. A passivation layer 332 is formed by depositing one selected from the group of inorganic insulating materials including).

The passivation layer 332 is configured to protect the previously exposed active layer 328a, and further serves to prevent the surface of the active layer 328a from coming into contact with an organic layer formed thereafter.

This is because the active layer and the organic film have poor interface characteristics, so that a trap level for trapping electrons is generated, and this phenomenon causes deterioration of operating characteristics of the thin film transistor.

Subsequently, an opaque organic insulating material is coated on the entire surface of the substrate 300 on which the passivation layer 332 is formed, and is patterned by a third mask process to form an upper portion corresponding to the gate line 302 and the data line 316. The lattice-shaped black matrix 334 is formed.

In this case, the organic material forming the black matrix 334 should be a material having an optical density of 3 or more, and at the same time, preferably have a fixed term value of 10 ¹³ Ω / cm 2 or more.

Only having the high resistance value as described above can prevent the delay of the signal flowing through the data and the gate wiring (324, 302).

As shown in FIGS. 13D, 14D, and 15D, a plurality of regions, ie, a plurality of pixel regions P, exposed between the lattice-shaped black matrices 334 are formed through a fifth mask process. Red color filters 326a (not shown and not shown) are sequentially formed in any order.

At this time, each of the color filters 336a (not shown, not shown) pattern the diagonal edges (A1, A2 of FIG. 4) in which the source and drain electrodes 320 and 322 are not located in a "a" or "b" shape. Thus, the first open part B1 and the second open part B2 exposing the lower surface of the protective film 332 in the shape of "ㅁ", where the edges of the shape of the color filter and the vertical two sides of the black matrix 334 meet. To form.

In more detail, the first open part B1 is positioned corresponding to one end of the extended drain electrode 322, and the second open part B2 is disposed in a direction opposite to the drain electrode 322. The common wiring 306 is positioned corresponding to a part of the common wiring 306.

In succession, the black matrix 334 and the color filters 336a and 336b (not shown) are used as anti-etching films to remove the protective film (and gate insulating film) 332 of the portions exposed to the open portions B1 and B2. The process of exposing a part of the drain electrode 322 corresponding to the first open part B1 and exposing a part of the lower common wiring 306 through the second open part B2 is performed. In this case, as shown in FIGS. 14D and 15D, the process proceeds to the shape in which both the gate pad 304 and the data pad 326 are exposed.

As shown in FIGS. 13E, 14E, and 15E, indium tin oxide (ITO) and indium zinc oxide (ITO) are formed on the entire surface of the substrate 300 on which the color filter 336a (not shown) is formed. Depositing and patterning a selected one of a group of transparent conductive metal materials including IZO to contact the exposed common wiring 306 with the transparent pixel electrodes 338a and 338b in contact with the exposed drain electrode 322. Transparent common electrodes 340a and 340b are formed.

When the shapes of the pixel electrodes 338a and 338b and the common electrodes 340a and 340b are described in detail, the pixel electrodes 338a and 338b may include a horizontal portion 338a contacting the drain electrode 322 and a horizontal portion. A plurality of vertical portions 338b extending from 338a to the pixel region P, and the common electrodes 340a and 340b are horizontal portions 340a contacting the common wiring 306 and horizontal portions. In FIG. 340b, the plurality of vertical portions 340b extend vertically into the pixel region P and are spaced in parallel with the pixel electrode 338b.

The pixel electrodes 338a and 338b and the common electrodes 340a and 340b are formed, and the island-shaped gate pad electrodes 342 contacting the exposed gate pads 304, the data pads 316, and the like. An island-shaped data pad electrode 346 in contact with each other is formed.

As shown in FIG. 13F, a transparent organic insulating material is coated on the entire surface of the substrate 100 on which the pixel electrodes 338a and 338b and the common electrodes 340a and 340b are formed, and then a seventh mask process is performed. The columnar spacers CS are formed corresponding to the first open portions B1 and the second open portions B2.

The spacer CS may serve to maintain a gap between the two substrates when the first substrate manufactured as described above and the second substrate are bonded, although not illustrated.

Through the above-described process, an array substrate for a liquid crystal display device according to a third embodiment of the present invention can be manufactured.

In the above-described process, in the process of removing the protective film (and lower gate insulating film) 332 exposed to the lower portions of the first and second open portions B1 and B2, the color filter 336a and the black matrix ( Although dry etching is performed using 334 as an etch stop layer, a photo mask process may be performed when the protective layer is removed, as in the fourth embodiment.

Fourth Embodiment

A feature of the fourth embodiment of the present invention is characterized in that in the manufacturing process of the third embodiment, the photo process is used in the process of removing the protective film exposed by the first and second open portions.

16A through 16E, 17A through 17D, and 18A through 18D are cross-sectional views illustrating a process sequence according to a fourth embodiment of the present invention.

As shown in FIGS. 16A, 17A, and 18A, as described in the third embodiment, the gate electrode 400 and the active pattern on the substrate 400 are processed through the first mask process and the second mask process. A thin film transistor T composed of a source electrode 420 and a drain electrode 422 is formed and intersects the thin film transistor T with the gate wiring 402 and the data wiring 424 interposed therebetween. To form.

In this case, a gate pad 404 and a data pad 426 are formed at one end of the gate line 402 and the data line 424, respectively.

As described above, an opaque organic insulating material is coated on the entire surface of the substrate 400 on which the thin film transistor T, the data lines and the gate lines 424 and 402 are formed, and then patterned to form the thin film transistor T and the data line. A lattice-like black matrix 434 is formed corresponding to the 424 and the gate wiring 402.

The red, green, and red color filters 436a (not shown) are sequentially formed in a random order through a process corresponding to the plurality of regions exposed between the grid-shaped black matrices 434, that is, the plurality of pixel regions P. do.

At this time, each of the color filters 436a pattern the diagonal edges (A1 and A2 of FIG. 4) in which the source and drain electrodes 420 and 422 are not located, in a "b" or "b" shape, thereby forming a shape. The corners of the color filter and the vertical two sides of the black matrix 124 meet to form a first open part B1 and a second open part B2 exposing the lower passivation layer 122 in a shape of “”.

In more detail, the first open part B1 is positioned to correspond to one end of the extended drain electrode 422, and the second open part B2 is disposed in a direction opposite to the drain electrode 422. It is positioned corresponding to a part of the common wiring 406.

Next, as illustrated, a photoresist is applied to the entire surface of the substrate 400 on which the black matrix 434 and the color filter 436a are formed to form a photosensitive layer 438.

In this case, the photoresist will be described with an example of having a positive characteristic.

The mask M including the transmissive part F1 and the blocking part F2 is positioned on the spaced upper portion of the substrate 400 on which the photosensitive layer 438 is formed.

The portion corresponding to the transmissive portion F2 is a portion corresponding to the first open portion B1, the second open portion B2, the gate pad 402, and the data pad 426.

As shown in FIGS. 16B, 17B, and 18B, when the light is irradiated to the upper portion of the mask to expose the lower photosensitive layer and the exposed photosensitive layer is developed, the transmissive portion of the mask corresponds to the transmissive portion. The photosensitive layer is removed to expose the lower passivation layer 432.

Next, a process of removing the exposed protective film 432 is performed.

As shown in FIGS. 16C, 17C, and 18C, the portion where the passivation layer 432 is removed may include the first contact hole CH1 exposing the lower drain electrode 422 and the lower common wiring 406. The second contact hole CH2 that is exposed, the third contact hole CH3 that exposes the gate pad 402, and the fourth contact hole CH4 that exposes the data pad 426 are formed.

Next, as shown in the plan view of FIG. 16D1 and in FIG. 16D2, indium is formed on the entire surface of the substrate 400 on which the first, second, third, and fourth contact holes CH1, CH2, CH3, and CH4 are formed. Depositing and patterning one selected from a group of transparent conductive metals including tin-oxide (ITO) and indium-zinc-oxide (IZ0) to contact the drain electrode 422 and the pixel electrodes 440a and 440b. The common electrodes 442a and 442b in contact with the common wiring 406, the gate pad electrode 446 in contact with the gate pad 404, and the data pad electrode 448 in contact with the data pad 426. Form.

In this case, the pixel electrodes 440a and 440b may include a horizontal portion 440a contacting the drain electrode 422 and a plurality of vertical portions 440b extending from the horizontal portion 440a to the pixel region P. The common electrodes 442a and 442b also have a horizontal portion 442a in contact with the common wiring 406, and a vertical portion extending from the horizontal portion 442a to the pixel electrode 440b and extending in parallel thereto. 442b.

16D-1 is slightly different from the plan view according to the first embodiment of the present invention described above.

That is, when the diffraction exposure (or halftone mask process) of the third embodiment described above is performed, the lower active layers 428a and 430 are exposed to the outside of the source and drain electrodes 420 and 422 and the data line 426. Becomes

Next, as illustrated in FIG. 16E, a transparent organic insulating material is coated on the entire surface of the substrate 400 on which the common electrodes 442a and 442b and the pixel electrodes 440a and 440b are formed, and then patterned. The columnar column spacer CS is formed to correspond to the first open part B1 and the second open part B2.

Through the above-described process, the array substrate for the transverse electric field type liquid crystal display device having the COT structure according to the fourth embodiment of the present invention can be manufactured.

As described above, column spacers were formed at the end of the process in the first to fourth embodiments.

However, when the density of the column spacer formed with respect to the first substrate is excessive, when the first substrate and the second substrate are bonded to each other, the first substrate and the second substrate may not be precisely aligned.

This is caused by friction between the column spacer configured with excessive density and the second substrate.

Therefore, a method of lowering the density of the column spacers and at the same time, planarizing the silver of the contact hole portion (the first open portion or the second open portion) in which the column spacer is not formed will be described through the fifth embodiment.

Fifth Embodiment

The fifth embodiment according to the present invention is characterized by providing a structure and a manufacturing method thereof in which a portion of the column spacer is not flattened while lowering the density of the column spacer.

19A to 19B are cross-sectional views showing the columnar spacer manufacturing process according to the fifth embodiment of the present invention in a revolving order.

As shown in FIG. 19A, the thin film transistor T and the thin film transistor T vertically cross each other to form a gate wiring 502 and a data wiring 514.

A common wiring 506 having a rectangular closed loop shape is formed in the pixel region P defined by the gate wiring 502 and the data wiring 514 crossing each other.

The passivation layer 522 is formed on the entire surface of the substrate 500 on which the thin film transistor T, the gates and the data lines 502 and 514 are formed, and the black matrix 524 and the color filter 526a are formed on the passivation layer 522. Form.

A horizontal portion 528a and a horizontal portion 528a contacting the drain electrode 518 on an upper portion of the color filter 526a of the pixel region P defined by the intersection of the gate wiring 502 and the data wiring 514. ), Pixel electrodes 528a and 528b including a plurality of vertical portions 528b extending vertically to the pixel region P, a horizontal portion 530a and the horizontal portion contacting the common wiring 506. Common electrodes 530a and 530b including vertical portions 530b extending vertically spaced apart from each other in parallel between pixel electrodes 528b at 530a are formed.

Next, an insulating photoacrylic (having negative characteristics) is applied to the entire surface of the substrate 500 on which the common electrodes 530a and 530b and the pixel electrodes 538a and 538b are formed to form the preceding spacer layer 526. .

The mask M including the transmissive part F1, the blocking part F2, and the semi-transmissive part F3 is positioned on the spaced upper portion of the substrate 500 on which the preceding spacer layer 526 is formed.

As mentioned above, since the preceding spacer layer 518 has negative characteristics, that is, an unexposed portion is developed, the transmissive part F1 of the mask M has the common wiring 506 and the common electrode 524a. The transmissive portion F1 is positioned at a portion H2 in contact with each other or in a portion H2 at which the drain electrode 512 and the pixel electrode 528a are in contact with each other. The transflective portion F3 is positioned to correspond to the portion that will not be positioned, and the blocking portion F2 is positioned in the remaining region.

The upper portion of the mask M configured as described above is irradiated with light to expose the lower preceding spacer layer, and the development process using the developer is continuously performed.

As a result, as shown in FIG. 19B, a columnar spacer CS is formed in a portion corresponding to the transmissive portion F1 of the mask M, and only a part of the portion corresponding to the transflective portion is developed from above. As a result, the contact portion H1 remains in a shape to fill the step.

If the contact portion H2 of the portion H2 where the spacer CS is not formed is left stepped, the initial alignment direction of the liquid crystal positioned in the contact portion will be different from that of the pixel region, and thus a voltage is applied. In addition, the normal arrangement characteristic of the liquid crystal cannot be obtained.

As a result, this part becomes a leaky light leakage area, which will cause a drop in image quality.

Therefore, as described above, it is important to flatten the step of the contact portion H2 where the spacer CS is not formed.

When the density of the spacer is reduced by the above process, there is an advantage in that the bonding failure can be prevented in the process of bonding the two substrates.

As described above, the transverse electric field type liquid crystal display device having the COT structure according to the present invention can be manufactured through the first to fifth embodiments.

The transverse electric field type liquid crystal display device having the COT structure according to the present invention has the following effects.

First, by using the transverse electric field method, it is possible to secure a wider viewing angle than the vertical electric field type liquid crystal display device.

Second, by introducing a color filter on TFT (COT) structure in the transverse electric field type liquid crystal display device, by not forming the color filter on a separate upper substrate, an alignment margin is compared with a process of forming the color filter on the upper side. There is no need to add), so the aperture ratio can be improved and the process can be simplified.

Third, since the color filter and the overcoating layer are not used as compared with the conventional structure, the stepped slope of the contact hole connecting the component layer positioned on the upper portion of the color filter layer and the component layer disposed on the lower portion of the color filter layer does not have to be large. The area where the foreground occurs (disclination) becomes small. Therefore, there is an effect of further improving the aperture ratio.

Fourth, there is an effect of simplifying the process by using a half-turn mask process of the process of forming the array substrate.

Fifth, by forming a spacer holding the gap of the liquid crystal panel on the lower substrate, there is no need for a bonding margin than when the spacer is formed on the upper substrate, and the spacer is not formed at the same time by using diffraction exposure to lower the density of the spacer. Since the process of filling the non-contact portion can be performed at the same time, there is an effect of simplifying the process and preventing deterioration of image quality.

1 is a cross-sectional view schematically showing a configuration of a general liquid crystal display device;

2 is an enlarged plan view illustrating an enlarged portion of an array substrate for a liquid crystal display device having a COT structure;

3 is a cross-sectional view of a vertical field type liquid crystal display panel of a conventional COT structure cut along II-II of FIG.

4 is an enlarged plan view of a portion of an array substrate for a transverse electric field type liquid crystal display device having a COT structure according to the present invention;

5A to 5G are process plan views showing a method of manufacturing an array substrate for a COT structure transverse electric field type liquid crystal display device according to a process sequence, and FIGS. 6A to 6G are IV-IV of each plan view of FIGS. 5A to 5G. Process section cut along

7A to 7F and 8A to 8F are cross-sectional views taken along the lines V-V and VI-VI of FIGS. 5A to 5F, respectively.

9 is an enlarged cross-sectional view illustrating the shape of a contact hole when the overcoating layer is formed,

10A to 10E, 11A to 11D, and 12A to 12D are cut along the lines IV-IV, V-V, and VI-VI of FIG. 4, and are shown in a process sequence according to a second embodiment of the present invention. Is a process cross section,

13A to 13F, 14A to 14E, and 15A to 15E are cut along the IV-IV, V-V, VI-VI of FIG. 4 of the present invention, and the process sequence according to the third embodiment of the present invention. It is the process cross section shown according to

16A through 16E, 17A through 17D, and 18A through 18D are cross-sectional views illustrating a process sequence according to a fourth embodiment of the present invention.

19A through 19B are cross-sectional views illustrating a process sequence according to a fifth embodiment of the present invention.

<Brief description of the main parts of the drawings>

100: substrate 102: gate wiring (gate electrode)

104: gate pad 106: common wiring

110 semiconductor layer 114 data wiring

116: data pad 118: source electrode

120 drain electrode 124 black matrix

126a and 126b color filters 128a and 128b pixel electrodes

130a and 130b: common electrode CS: column spacer

Claims (53)

A plurality of gate lines extending in one direction on the substrate and spaced apart from each other in parallel; A common wiring positioned in each of the separation regions of the plurality of gate wirings; A plurality of data lines defining a plurality of pixel regions by crossing the plurality of gate lines perpendicularly; A thin film transistor positioned at an intersection point of the gate line and the data line; A passivation layer formed on an entire surface of the substrate on which the thin film transistor, the gate wiring and the data wiring are formed; A black matrix on the passivation layer corresponding to the thin film transistor, the gate wiring, and the data wiring; Corresponding to the plurality of pixel regions, red, green, and blue are sequentially formed, and corners are patterned in a shape of "a" or "b" so that the black matrix, the first open part and the second open part of the "ㅁ" shape are formed. A color filter constituting; A pixel electrode in contact with the drain electrode exposed by the first opening; A common electrode spaced apart from and parallel to the pixel electrode and in contact with the common wiring through the second opening part Array substrate for a transverse electric field type liquid crystal display device comprising a. The method of claim 1, The thin film transistor may include a gate electrode connected to the gate wiring, a semiconductor layer positioned on the gate wiring, a source electrode connected to the data wiring, and spaced in parallel with the source electrode to extend over the common wiring. An array substrate for a transverse electric field type liquid crystal display device including a drain electrode. The method of claim 2, And a storage capacitor having the extended drain electrode as a first electrode and a lower common wiring overlapping the drain electrode as a second electrode. The method of claim 1, The pixel electrode includes a horizontal portion in contact with the pixel electrode and a plurality of vertical portions extending vertically from the horizontal portion to the pixel region, and the common electrode includes the horizontal portion and the horizontal portion in contact with the common wiring. And an array substrate for a transverse electric field type liquid crystal display device which is vertically extended to be spaced apart from the vertical portion of the pixel electrode. The method of claim 1, And a plurality of quadrangular closed loops connected between the common wirings in a spaced area between the gate wirings so that the common wirings are arranged in a direction parallel to the gate wirings. The method of claim 5, wherein And wherein the common wiring is one rectangular closed loop corresponding to the pixel region. The method of claim 1, And a gate pad at one end of the gate line, and a data pad at one end of the data line. The method according to any one of claims 2 to 7, And an extension portion of the semiconductor layer formed below the data line and the data pad in the semiconductor layer. The method according to any one of claims 1 to 8, And a protective layer corresponding to the first and second openings, the gate pad and the data pad is removed. The method of claim 9, An array substrate for a transverse electric field type liquid crystal display device further comprising columnar column spacers corresponding to the first opening portion and the second opening portion. The method of claim 10, The column spacer is configured to be distracted corresponding to the pixel area, wherein the first open portion or the second open portion, in which the column spacer is not formed, is filled with the same material as that of the column spacer. The method according to any one of claims 1 to 8, A portion of the passivation layer corresponding to the first opening portion, the second opening portion, the gate pad, and the data pad may not be completely removed, and a portion of the passivation layer may be removed to partially expose the lower drain electrode, the common wiring, the gate pad, and the data pad. An array substrate for a transverse electric field type liquid crystal display device. The method of claim 12, An array substrate for a transverse electric field type liquid crystal display device further comprising columnar column spacers corresponding to the first opening portion and the second opening portion. The method of claim 13, The column spacer is configured to be distracted corresponding to the pixel area, wherein the first open portion or the second open portion, in which the column spacer is not formed, is filled with the same material as that of the column spacer. The method of claim 1, And the black matrix has an optical density of 3 or more and a resistance value of 10 ¹³ Ω / cm 2 or more. The method according to any one of claims 1 to 8, And an extension portion of the semiconductor layer and the semiconductor layer is exposed to the periphery of the source and drain electrodes, the data line, and the data pad. The method of claim 16, And a protective layer corresponding to the first and second openings, the gate pad and the data pad is removed. The method of claim 17, An array substrate for a transverse electric field type liquid crystal display device further comprising columnar column spacers corresponding to the first opening portion and the second opening portion. The method of claim 18, The column spacer is configured to be distracted corresponding to the pixel area, wherein the first open portion or the second open portion, in which the column spacer is not formed, is filled with the same material as that of the column spacer. The method of claim 16, A portion of the passivation layer corresponding to the first opening portion, the second opening portion, the gate pad, and the data pad may not be completely removed, and a portion of the passivation layer may be removed to partially expose the lower drain electrode, the common wiring, the gate pad, and the data pad. An array substrate for a transverse electric field type liquid crystal display device. The method of claim 20, An array substrate for a transverse electric field type liquid crystal display device further comprising columnar column spacers corresponding to the first opening portion and the second opening portion. The method of claim 21, And the column spacers are scattered in correspondence to the pixel region, and the first or second open portion in which the column spacer is not formed is filled with the same material as the column spacer. The method of claim 1, And the common electrode is connected to the common wiring at an outer side of the substrate, not through the second opening. The method of claim 23, And the common electrode is connected to a common electrode configured to be adjacent to each other. A plurality of gate wires extending in one direction on the substrate and spaced in parallel to each other, and common wires disposed in a spaced area of the gate wires and connected to a plurality of rectangular closed loop shapes in a direction parallel to the gate wires. Forming a first mask process step; Forming a gate insulating film on the gate wiring and the common wiring; A second mask process step of forming a semiconductor layer on an upper portion of the gate insulating layer, the gate wiring corresponding to a portion of the upper portion; A third mask process of forming a data line defining a plurality of pixel regions including the quadrangular closed loops perpendicularly intersecting the gate line, a source electrode connected to the data line, and a drain electrode spaced apart from the source electrode; Steps; Forming a protective film on an entire surface of the substrate on which the source and drain electrodes and the data wiring are formed; A fourth mask process step of forming a black matrix corresponding to the source and drain electrodes, the gate wiring, and the data wiring; Red, green, and blue are sequentially formed in correspondence with the pixel area, and corners are patterned in a shape of "B" or "L" to form a first open part and a second open part of the black matrix, the "ㅁ" shape. A fifth mask process step of forming a filter; Using the black matrix and the color filter as an etch stop layer, etching a lower passivation layer to expose a lower drain electrode and a common wiring through the first open part and the second open part; A sixth mask process step of forming a pixel electrode in contact with the drain electrode exposed to the first open part and a common electrode spaced apart from the pixel electrode in parallel, and in contact with the common wiring through the second open part; Array substrate manufacturing method for a transverse electric field type liquid crystal display device comprising a. The method of claim 25,  And a storage capacitor further comprising the extended drain electrode as a first electrode and a lower common wiring overlapping the drain electrode as a second electrode. The method of claim 25, The pixel electrode includes a horizontal portion in contact with the pixel electrode and a plurality of vertical portions extending vertically from the horizontal portion to the pixel region, and the common electrode includes the horizontal portion and the horizontal portion in contact with the common wiring. 12. A method of fabricating an array substrate for a transverse electric field type liquid crystal display device which is vertically extended to be spaced apart from the vertical portion of the pixel electrode. The method of claim 25, And a plurality of quadrangular closed loops connected between the common wirings in a spaced area between the gate wirings so that the common wirings are arranged in a direction parallel to the gate wirings. The method of claim 28, And wherein the common wiring is one rectangular closed loop corresponding to the pixel region. The method of claim 25, A gate pad is formed at one end of the gate wiring, and a data pad is further formed at one end of the data wiring. The method according to any one of claims 25 to 30, And an extension portion of the semiconductor layer further formed below the data line and the data pad in the semiconductor layer. The method of claim 31, wherein The method of manufacturing an array substrate for a transverse electric field type liquid crystal display device, wherein all of the first and second opening portions, and the protective layer corresponding to the gate pad and the data pad are removed. The method of claim 32, A method for manufacturing an array substrate for a transverse electric field type liquid crystal display device further comprising columnar column spacers corresponding to the first opening portion and the second opening portion. The method of claim 33, wherein The column spacer is formed to be distracted corresponding to the pixel region, and the first or second open portion in which the column spacer is not formed is filled with the same material as that of the column spacer. . The method according to any one of claims 25 to 30, A passivation layer corresponding to the first opening portion, the second opening portion, the gate pad, and the data pad may not be completely removed, and a portion of the passivation layer may be removed to expose a lower drain electrode, a part of the common wiring, the gate pad, and the data pad. An array substrate manufacturing method for a transverse electric field type liquid crystal display device further comprising the step. 36. The method of claim 35 wherein And forming a columnar column spacer corresponding to the first opening portion and the second opening portion. The method of claim 36, The column spacer is formed to be distracted corresponding to the pixel region, and the first or second open portion in which the column spacer is not formed is filled with the same material as that of the column spacer. . The method of claim 25, The black matrix has an optical density of 3 or more and a resistance value of 10 ¹³ Ω / cm 2 or more. A plurality of gate wires extending in one direction on the substrate and spaced in parallel to each other, and common wires disposed in a spaced area of the gate wires and connected to a plurality of rectangular closed loop shapes in a direction parallel to the gate wires. Forming a first mask process step; Forming a gate insulating film on the gate wiring and the common wiring; A semiconductor layer on the gate insulating layer corresponding to a portion of the gate wiring, a source and drain electrode spaced apart from the semiconductor layer, and a pixel region connected to the source electrode and perpendicularly intersecting with the gate wiring to define a pixel region. A second mask process step of forming data wirings; Forming a protective film on an entire surface of the substrate on which the source and drain electrodes and the data wiring are formed; A third mask process step of forming a black matrix corresponding to the source and drain electrodes, the gate wiring, and the data wiring; Red, green, and blue are sequentially formed in correspondence with the pixel area, and corners are patterned in a shape of "B" or "L" to form a first open part and a second open part of the black matrix, the "ㅁ" shape. A fourth mask process step of forming a filter; Using the black matrix and the color filter as an etch stop layer, etching a lower passivation layer to expose a lower drain electrode and a common wiring through the first open part and the second open part; A fifth mask process step of forming a pixel electrode in contact with the drain electrode exposed to the first open part and a common electrode spaced apart from the pixel electrode in parallel, and in contact with the common wiring through the second open part; Array substrate manufacturing method for a transverse electric field type liquid crystal display device comprising a. The method of claim 39, The second mask process step, Sequentially stacking a pure amorphous silicon layer, an impurity amorphous silicon layer, a conductive metal layer, and a photosensitive layer on the gate insulating film; Positioning a mask including a transmissive part, a blocking part, and a transflective part on a spaced upper portion of the substrate on which the photosensitive layer is formed; The light is irradiated from the upper part of the mask to expose and develop the lower photoresist layer, and is connected to the first photoresist layer pattern having a different height and a first photoresist layer pattern on a portion of the gate wiring. Forming a second photosensitive layer pattern formed in a direction perpendicular to the direction; The conductive metal layer exposed to the lower portion of the first photosensitive layer pattern and the second photosensitive layer pattern is etched to form a first metal pattern below the first photosensitive layer pattern and a second below the second photosensitive layer pattern. Forming a metal pattern; The impurity amorphous silicon layer exposed below the first and second photosensitive layer patterns and the pure amorphous silicon layer below are etched to form a semiconductor layer under the first metal layer and a semiconductor layer under the second metal pattern. Forming an extension of the; Performing an ashing process of cutting the first photosensitive pattern and the second photosensitive pattern to expose a lower first metal pattern by removing a portion having a low height of the first photosensitive layer; Removing the exposed metal pattern and removing the first and second photosensitive layers to form a source electrode and a drain electrode spaced apart from each other on the first active pattern, and a data line connected to the source electrode; An array substrate manufacturing method for a transverse electric field type liquid crystal display device comprising the step. The method of claim 39,  And a storage capacitor further comprising the extended drain electrode as a first electrode and a lower common wiring overlapping the drain electrode as a second electrode. The method of claim 39, The pixel electrode includes a horizontal portion in contact with the pixel electrode and a plurality of vertical portions extending vertically from the horizontal portion to the pixel region, and the common electrode includes the horizontal portion and the horizontal portion in contact with the common wiring. 12. A method of fabricating an array substrate for a transverse electric field type liquid crystal display device which is vertically extended to be spaced apart from the vertical portion of the pixel electrode. The method of claim 39, A gate pad is formed at one end of the gate wiring, and a data pad is further formed at one end of the data wiring. The method according to any one of claims 39 to 43, And an extension portion of the semiconductor layer and the semiconductor layer is exposed to the periphery of the source and drain electrodes, the data line, and the data pad. The method of claim 44, The method of manufacturing an array substrate for a transverse electric field type liquid crystal display device, wherein all of the first and second opening portions, and the protective layer corresponding to the gate pad and the data pad are removed. The method of claim 45, A method for manufacturing an array substrate for a transverse electric field type liquid crystal display device, in which columnar column spacers are further formed corresponding to the first and second openings. The method of claim 46, The column spacer is formed to be distracted corresponding to the pixel region, and the first or second open portion in which the column spacer is not formed is filled with the same material as that of the column spacer. . The method according to any one of claims 39 to 43, A passivation layer corresponding to the first opening portion, the second opening portion, the gate pad, and the data pad may not be completely removed, and a portion of the passivation layer may be removed to expose a lower drain electrode, a part of the common wiring, the gate pad, and the data pad. An array substrate manufacturing method for a transverse electric field type liquid crystal display device further comprising the step. 49. The method of claim 48 wherein And forming a columnar column spacer corresponding to the first opening portion and the second opening portion. The method of claim 49, The column spacer is formed to be distracted corresponding to the pixel region, and the first or second open portion in which the column spacer is not formed is filled with the same material as that of the column spacer. . The method of claim 39, The black matrix has an optical density of 3 or more and a resistance value of 10 ¹³ Ω / cm 2 or more. A plurality of gate lines extending in one direction on the substrate and spaced apart from each other in parallel; A common wiring positioned in each of the separation regions of the plurality of gate wirings; A plurality of data lines defining a plurality of pixel regions by crossing the plurality of gate lines perpendicularly; A thin film transistor positioned at an intersection point of the gate line and the data line; A passivation layer formed on an entire surface of the substrate on which the thin film transistor, the gate wiring and the data wiring are formed; A black matrix on the passivation layer corresponding to the thin film transistor, the gate wiring, and the data wiring; Corresponding to the plurality of pixel regions, red, green, and blue are sequentially formed, and corners are patterned in a shape of "B" or "L", and the first and second open parts of the black matrix, the "W" shape, and the second open part are formed. A color filter constituting; A pixel electrode in contact with the drain electrode exposed by the first open portion; and a common electrode spaced apart from the pixel electrode in parallel with the pixel electrode and in contact with the common wiring through the second open portion. In the forming of the column spacers corresponding to the first or second openings, Forming a spacer preceding layer by applying a photosensitive transparent organic material to the entire surface of the substrate on which the pixel electrode and the common electrode are formed; Positioning a mask including a transmissive part, a transflective part, and a blocking part on an upper part of the substrate spaced apart from the substrate on which the spacer preceding layer is formed; The upper part of the mask is irradiated with light, and the lower part exposes and develops a spacer preceding layer, thereby forming a columnar spacer in the first or second open part, and a second open part or first in which no spacer is formed. A method of manufacturing a spacer of an array substrate for a transverse electric field type liquid crystal display device comprising the step of filling an open portion. The method of claim 52, wherein A method of manufacturing a spacer of an array substrate for a transverse electric field type liquid crystal display device, wherein the second open portion or the first open portion in which the column spacer is not formed is a region corresponding to the transflective portion of the mask.