KR101422198B1 - Method of fabricating color filter on TFT type array substrate for In-plane switching mode liquid crystal display device - Google Patents

Abstract

The present invention provides a method of manufacturing a semiconductor device, comprising: forming a gate wiring extending in one direction on a substrate; Forming an island-shaped active layer corresponding to a switching region in which a thin film transistor on the gate wiring is to be formed over the gate insulating film, and forming an impurity amorphous silicon pattern on the common wiring over the common wiring; Wow; Forming a color filter layer in an area other than the switching area; Forming a first protective layer over the color filter layer; Forming first and second metal layers on the entire surface of the substrate to expose the impurity amorphous silicon pattern on the first passivation layer; Layer structure in which the first and second metal layers are patterned to define a pixel region intersecting with the gate wiring over the first protective layer, and a plurality of double-layer structures alternately spaced apart from each other in the pixel region And forming a plurality of central common electrodes connected to the common wiring, the method comprising: forming source and drain electrodes spaced apart from each other in a bilayer structure in the switching region and an ohmic contact layer spaced apart from the source and drain electrodes; Forming a second passivation layer covering the exposed active layer between the source and drain electrodes; And forming a plurality of pixel electrodes and a central common electrode having a single layer structure between the second protective layers by removing the upper layer of the pixel electrodes and the central common electrode of the double layer structure, Of the present invention.

COT, transverse electric field, semiconductor pattern, way noise, off-current

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of fabricating an array substrate for a liquid crystal display

The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing an array substrate for a COT-structured transverse electric field type liquid crystal display device.

Recently, liquid crystal display devices have been attracting attention as next generation advanced display devices with low power consumption, good portability, and high value-added.

Among these liquid crystal display devices, an active matrix type liquid crystal display device having a thin film transistor, which is a switching device capable of controlling voltage on / off for each pixel, It is attracting attention.

In general, a liquid crystal display device forms an array substrate and a color filter substrate through an array substrate manufacturing process for forming thin film transistors and pixel electrodes, and a color filter substrate manufacturing process for forming color filters and common electrodes, And a liquid crystal cell interposed therebetween.

1, which is an exploded perspective view of a general liquid crystal display device, the array substrate 10 and the color filter substrate 20 are bonded to each other with a liquid crystal layer 30 interposed therebetween The lower array substrate 10 includes a plurality of gate wirings 14 and data wirings 16 that are longitudinally and laterally arranged on the upper surface of a transparent substrate 12 to define a plurality of pixel regions P A thin film transistor T is provided at the intersection of these two wirings 14 and 16 and is connected in a one-to-one correspondence with the pixel electrode 18 provided in each pixel region P.

The upper portion of the color filter substrate 20 facing the array substrate 10 is electrically connected to the rear surface of the transparent substrate 22 through the gate wiring 14, the data wiring 16, the thin film transistor T, Shaped black matrix 25 for framing each pixel region P so as to cover the respective pixel regions P in the pixel region P. The red (R), green A color filter layer 26 including color filter patterns 26a, 26b and 26c of blue (G) and blue (B) colors is formed on the front surface of the color filter layer 26, A common electrode 28 is provided.

The liquid crystal display device having the above-described configuration has disadvantages in that the liquid crystal is driven by the vertical electric field generated by the upper and lower electrodes, resulting in poor viewing angle characteristics. Therefore, a transverse electric field type liquid crystal display device having excellent viewing angle characteristics is proposed, in which a common electrode formed on the color filter substrate is formed on the array substrate to overcome the above disadvantages.

On the other hand, in the transverse electric field type liquid crystal display device, in the upper color filter substrate corresponding to the array substrate, the first color filter substrate surrounds each pixel region, that is, the first line corresponding to the data line and the gate line of the array substrate and the thin film transistor The first black matrix is formed to have a width that is the sum of the actual width and the error range in consideration of the adhesion error when the array substrate and the color filter substrate are attached to each other. Therefore, in the transverse electric field type liquid crystal display device having such a configuration, the coalescence error of the black matrix must be taken into consideration, and the width of the black matrix must be larger than the actual designed value.

Therefore, in order to solve such a problem, a color filter on TFT (hereinafter referred to as COT) structure lateral electric field type liquid crystal display device has been recently proposed which is formed on an array substrate up to a color filter layer.

2 is a cross-sectional view of one pixel region including a thin film transistor which is a switching element of a conventional COT-structured transverse electric field liquid crystal display device.

As shown in the drawing, gate lines and data lines (not shown) are formed to define a pixel region P intersecting with each other. A common line 55 is formed in the same layer as the gate line (not shown) Respectively. A gate electrode 58, a gate insulating film 60, an active layer 63a, and a gate insulating film 60 are connected to these two wirings (not shown) in the vicinity of a point crossing the gate and the data wiring A thin film transistor Tr composed of the semiconductor layer 63 including the ohmic contact layer 63b spaced apart from each other and the source and drain electrodes 72 and 74 is formed.

A first passivation layer 77 is formed on the thin film transistor Tr and is sequentially formed on the first passivation layer 77 corresponding to each pixel region P, (80a, 80b, 80c). A second passivation layer 85 is formed on the color filter layer 80 and the second passivation layer 85 and the color filter layer 80 and the first protection layer 85 are formed on the second passivation layer 85, The layer 77 is removed to expose the drain electrode 74 and a plurality of pixel electrodes 87 are formed at a predetermined interval in contact with the drain electrode 74 through the formed drain contact hole 83, A plurality of common electrodes 89 are formed alternately and spaced apart from the plurality of pixel electrodes 87. At this time, the common electrodes 89 are removed by removing the common wiring 55, the second passivation layer 85, the color filter layer 80, the first passivation layer 77 and the gate insulating layer 60 And are electrically connected through a plurality of common contact holes (not shown) exposing a part of the common wiring 55.

In the case of the array substrate 51 for a COT-structured transverse electric field type liquid crystal display having the above-described structure, eight mask processes are generally performed. At this time, after the pure amorphous silicon layer, the impurity amorphous silicon layer, and the metal layer are sequentially laminated and the photoresist is applied, the source and drain electrodes 72 and 74 and the active layer 63a are formed by ohmic The semiconductor layer 63 composed of the contact layer 63b is formed by a single mask process to form the undesired structure and the source region 63a exposed between the source and drain electrodes 72 and 74 facing each other, And the active layer 63a of the portion indicated by A in the outer edge of both ends of the drain electrodes 72 and 74 is exposed.

At this time, when the active layer 63a exposed to the outside of the ends of the source and drain electrodes 72 and 74 is driven by a liquid crystal display device (not shown) completed using the array substrate 51 having such a structure, And is excited by light incident from the outside to affect the switching of the thin film transistor Tr to lower the _off-off characteristic. Further, due to the nature of the manufacturing process, The first semiconductor pattern 64a made of the same material as the first semiconductor layer 64a has a problem of generating a wavy noise that causes unevenness on the screen.

In order to solve the above problems, the present invention prevents the active layer from being exposed to the outside of the ends of the source and drain electrodes, thereby preventing the off current property from being degraded by the photocurrent and further preventing the semiconductor pattern So as to prevent wavy noise.

Another object of the present invention is to improve the aperture ratio by forming a color filter layer on an array substrate, thereby reducing the margin due to the adhesion error.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display, comprising: forming a gate line extending in one direction on a substrate; Forming an island-shaped active layer corresponding to a switching region in which a thin film transistor on the gate wiring is to be formed over the gate insulating film, and forming an impurity amorphous silicon pattern on the common wiring over the common wiring; Wow; Forming a color filter layer in an area other than the switching area; Forming a first protective layer over the color filter layer; Forming first and second metal layers on the entire surface of the substrate to expose the impurity amorphous silicon pattern on the first passivation layer; Layer structure in which the first and second metal layers are patterned to define a pixel region intersecting with the gate wiring over the first protective layer, and a plurality of double-layer structures alternately spaced apart from each other in the pixel region And forming a plurality of central common electrodes connected to the common wiring, the method comprising: forming source and drain electrodes spaced apart from each other in a bilayer structure in the switching region and an ohmic contact layer spaced apart from the source and drain electrodes; Forming a second passivation layer covering the exposed active layer between the source and drain electrodes; And removing the upper layer of the pixel electrode and the central common electrode of the double layer structure and forming a plurality of pixel electrodes and the central common electrode of a single layer structure between the second protective layers.

The step of forming the common wiring with the gate wiring may include a step of forming a first common connection pattern which branches from the common wiring and which connects an outermost common electrode located at an outermost position of the pixel region and an end of the outermost common electrode Wherein the forming of the first passivation layer includes forming a plurality of common contact holes exposing the first common connection pattern. The forming of the plurality of pixel electrodes and the central common electrode of the double layer structure may include connecting one end of the plurality of central common electrodes of the double-layer structure to each other through the first common connection pattern and the plurality of common contact holes A second common connection pattern of a double layer structure in contact with the first common connection pattern, a second common connection pattern of a double layer structure in contact with the second common connection pattern and overlapping the outermost common electrode, It is characterized by further forming a connection pattern.

The step of forming the double-layered data line, the plurality of pixel electrodes of a bilayer structure, the plurality of central common electrodes of a bilayer structure, the source and drain electrodes of a bilayer structure, and the ohmic contact layer, A first photoresist pattern having a first thickness corresponding to the source and drain electrodes and the data line is formed on the second metal layer and a second photoresist pattern having a second thickness corresponding to the pixel electrodes and the central common electrode of the double- Forming a thick second photoresist pattern; Removing the second and first metal layers exposed outside the first and second photoresist patterns; And removing the exposed impurity amorphous silicon pattern by removing the second and first metal layers. At this time, the step of forming the second passivation layer may include a step of ashing to remove the first photoresist pattern; Forming an inorganic insulating layer over the entire surface of the newly exposed double-layered data line and source and drain electrodes by removing the first photoresist pattern; Exposing the substrate on which the inorganic insulating layer is formed to a stripping liquid to perform a lift-off process for removing the inorganic insulating layer formed on the upper and side surfaces of the second photoresist pattern; Wherein the step of forming the plurality of pixel electrodes and the central common electrode simultaneously etches the second metal layer and the inorganic insulating layer and the etching rate of the second metal layer is faster than the etching rate of the inorganic insulating layer. And the upper layer of the pixel electrode and the central common electrode of the double-layer structure are removed. The second protective layer covers the data line and the source and drain electrodes and is formed in a region between the plurality of pixel electrodes of the single layer structure and the central common electrode.

And forming a plurality of patterned spacers on the second protective layer, the patterned spacers being spaced apart from each other by a distance corresponding to the data lines.

The forming of the common wiring with the gate wiring may include forming a gate pad electrode connected to one end of the gate wiring and a data pad electrode so that the data wiring is in contact with one end of the data pad electrode . The forming of the first passivation layer may include forming a gate pad contact hole exposing the gate pad electrode and a data pad contact hole exposing the data pad electrode. The step of forming the plurality of pixel electrodes and the central common electrode of the single layer structure may include a single layered gate pad electrode having a single layer contact with the gate pad electrode through the gate pad contact hole, Forming an auxiliary data pad electrode having a single layer structure in contact with the data pad electrode through the contact hole.

The pixel connection pattern of the double-layer structure is formed so as to overlap with the common wiring, so that the common wiring and the pixel connection pattern of the double-layer structure overlap each other via the gate insulating film to form a storage capacitor, Layered pixel electrode and the central common electrode are formed by removing the upper layer of the pixel connection pattern of the double layer structure to form a pixel connection pattern of a single layer structure.

A plurality of central common electrodes and an outermost common electrode of the single layer structure and a plurality of pixel electrodes of the single layer structure are formed to have a symmetrically bent structure with respect to a central portion of the pixel region Feature.

The active layer is formed to have a smaller size than the gate wiring and to have the gate wiring exposed around the active layer.

The COT-structured transverse electric-field-type liquid crystal display device according to the embodiment of the present invention has an effect of preventing the deterioration of the off-current characteristic due to the generation of the photocurrent due to the active layer exposed to the outside of the source and drain electrodes, There is an effect that it is possible to prevent image quality defects such as wavy noise due to the structure having no semiconductor pattern to be formed.

In addition, the common electrode and the pixel electrode are formed on one substrate to perform transverse electric field driving, thereby improving the viewing angle.

Further, the color filter layers are formed on the array substrate so that the respective color filter patterns are located at the boundaries of the respective pixel regions, thereby improving the aperture ratio by reducing the margin due to the adhesion error.

Hereinafter, preferred embodiments according to the present invention will be described with reference to the drawings.

In this case, in the COT-structured transverse electric field type liquid crystal display device according to the present invention, the characteristic part is on the array substrate including both the thin film transistor and the color filter layer, and the array substrate will be mainly described.

FIG. 3 is a plan view of one pixel region of an array substrate of a COT-structured transverse electric field type liquid crystal display device according to an embodiment of the present invention, and FIG. 4 is a sectional view of a portion cut along the line IV- And FIGS. 5 and 6 are sectional views of a gate pad portion and a data pad portion of an array substrate of a COT-structured transverse electric field type liquid crystal display device according to an embodiment of the present invention, respectively.

3, the array substrate 101 for a COT-structured transverse electric field type liquid crystal display according to the present invention includes a transparent isolator plate 101, A gate wiring 105 and a data wiring 152 are formed defining the pixel region P. [ The common wiring 109 is formed so as to be spaced apart from the gate wiring 105 and branched at the common wiring 109 so that the outermost common electrode 114 is provided on both sides of the pixel region P The outermost common electrode 114 is formed by a first auxiliary common connection pattern 115 whose one ends are arranged in parallel with the common wiring 109 It is connected. Although not shown in the drawing, the ends of the gate and data lines 105 and 152 extend to the gate and data pad portions (not shown), respectively, to form a gate and a data pad electrode (not shown), respectively.

A gate electrode 111, a gate insulating film (not shown), and an active layer 124 (not shown) are connected to the two wirings 105 and 152 near the intersection of the gate wiring 105 and the data wiring 152 And a thin film transistor Tr which is a switching element composed of a semiconductor layer (not shown) composed of an ohmic contact layer (not shown) and source and drain electrodes 154 and 156 is formed. The thin film transistor Tr is characterized in that the gate wiring 105 is formed on the gate wiring 105 by forming the gate electrode 111 itself. The drain electrode 156 of the thin film transistor Tr extends to a portion where the common wiring 109 is formed in the pixel region P so that a part thereof overlaps with the common wiring 109, And the source electrode 154 is formed by being branched in the data line 152. [

A plurality of central common electrodes 179 are alternately formed in the center of the pixel region P and the same material as the plurality of central common electrodes 179 is formed on both sides of the data lines 152 And the auxiliary common electrode 180 is formed. At this time, the auxiliary common electrode 180 and the central common electrode 179 are connected to each other by a second auxiliary common connection pattern 181 formed by overlapping the first auxiliary common connection pattern 115 with the same material, And the first auxiliary common connection pattern 115 and the second auxiliary common connection pattern 181 are electrically connected to each other by a plurality of common contact holes 148.

A plurality of pixel electrodes 178 are formed alternately and in parallel with the plurality of central common electrodes 179 between the auxiliary common electrodes 180 in the pixel region P, The electrodes 178 are all electrically connected by the pixel connection pattern 177. The pixel connection pattern 177 overlaps the common wiring 109 and is electrically connected to the drain electrode 156 extended to the common wiring 109. On the other hand, the common wiring 109 and the pixel connection pattern 177 overlapping each other constitute a storage capacitor StgC and constitute a first storage electrode and a second storage electrode, respectively.

A color filter layer (not shown) including red, green, and blue color filter patterns is formed in each pixel region P of the substrate 101 having the above-described structure. At this time, the color filter layer (not shown) corresponds to each pixel region P so that red, green, and blue color filter patterns (not shown) are sequentially and repeatedly associated. The color filter layer (not shown) is not formed in a region where the thin film transistor Tr is formed.

The plurality of pixel electrodes 178, the central common electrode 179, the auxiliary common electrode 180 and the data lines 152 may be formed on the color filter layer (not shown) And the like. The columnar patterned spacers 184 are spaced apart from each other by a predetermined distance corresponding to the data lines 152. The gate and data pad electrodes (not shown) may be formed of the same material as the pixel electrodes 178, (Not shown) corresponding to the gate electrode and the data pad contact hole (not shown), respectively, and are formed with a gate and a data auxiliary pad electrode (not shown), respectively.

On the other hand, in the planar structure of the array substrate 101 for a transverse electric field type liquid crystal display according to the present invention having the above-described configuration, the data line 152, the pixel electrode 178, the common electrodes 114 and 179, The pixel electrode 178 and the common electrodes 114 and 179 and the auxiliary common electrode 180 may be formed as a modification of the data line 152 and the pixel electrode 178. However, May be formed so as to have a double domain structure by being configured to have a structure that is folded and symmetrical with respect to the center of each pixel region (P). A plurality of common electrodes 114 and 179 formed parallel to the data lines 152 and the data lines 152 and the auxiliary common electrodes 180 and the pixel electrodes 178 are bent at the center of the data lines 152, P), it is possible to reduce the occurrence of chrominance according to the viewing angle.

Next, with reference to Figs. 4, 5 and 6, a cross-sectional structure of an array substrate for a COT-structured transverse electric field type liquid crystal display device according to the present invention will be described. For convenience of explanation, a region where the thin film transistor Tr as a switching element is formed is referred to as a switching region TrA, a region where a storage capacitor StgC is formed is referred to as a storage region StgA, Regions are defined as a gate pad portion (GPA) and a data pad portion (DPA), respectively.

As shown in the figure, a gate wiring 105 is formed on a transparent insulating substrate 101 and forms a gate electrode 111 in part, and extends in one direction. The gate wiring 105 is spaced apart from the gate wiring 105 by a predetermined distance And common wirings 109 are formed in the same layer in the same layer as the gate wirings 105. The common wirings 109 branch off from the common wirings 109 and are arranged in parallel with the data wirings 152, And a first auxiliary common connection pattern (not shown) is formed by connecting the outermost common electrode 114 and one end of the outermost common electrode 114 at the outermost periphery. A gate pad electrode GPA is connected to the gate line 105 and a gate pad electrode 117 and a data pad electrode 118 is formed in the data pad unit DPA.

A gate insulating film composed of an inorganic insulating material is formed on the entire surface of the gate wiring 105 including the gate electrode 111, the common wiring 109, the outermost common electrode 114 and the first auxiliary common connection pattern (not shown) 120 are formed. Further, the red, green, and blue colors are sequentially and repeatedly applied to the pixel regions except for the switching region (TrA) over the gate insulating layer 120 on the gate insulating layer 120 for each pixel region P, and the color filter patterns 140a, 140b, not shown) are formed on the surface of the color filter layer 140. A first passivation layer 143 is formed on the color filter layer 140 except for the switching area TrA. The first passivation layer 143 is formed of an insulating material having photosensitive characteristics and having inorganic and organic hybrid characteristics.

A data line 152 is formed on the first passivation layer 143 and the gate insulating film 120 of the switching region TrA to define the pixel region P so as to intersect the gate line 105 have. At this time, the data line electrode 152 extends to the data pad unit DPA and is connected to the data pad electrode 118.

The semiconductor layer 130 is formed in the switching region TrA by island formation of the active layer 124 and the ohmic contact layer 128 spaced apart from the active layer 124 in correspondence with the gate electrode 111, Source and drain electrodes 154 and 156 are formed on the semiconductor layer 130 in contact with the ohmic contact layer 128, respectively. At this time, the gate electrode 111, the gate insulating layer 120, the semiconductor layer 130, and the source and drain electrodes 154 and 156 form a thin film transistor Tr.

The source electrode 154 is formed to be branched from the data line 152 and the drain electrode 156 extends to a portion where the common line 109 is formed. At this time, the source and drain electrodes 154 and 156 and the data line 152 have a bilayer structure.

The semiconductor layer 130 including the active layer 124 and the ohmic contact layer 128 is formed in an island shape only in the switching region TrA as the most characteristic portion of the present invention. A semiconductor pattern formed of the same material as the active layer 124 and the ohmic contact layer 128 is not formed under the data line 152. Therefore, since the semiconductor pattern formed by being exposed to the outside of the lower portion of the data line 152 is not constituted, the way noise generated by the semiconductor pattern can be prevented originally.

On the other hand, a plurality of pixel electrodes 178, a central common electrode 179, and an auxiliary common electrode 180 are formed in the pixel regions P alternately and spaced apart from each other. The plurality of pixel electrodes 178 are electrically connected to the drain electrode 156 through the pixel connection pattern 177. The plurality of central common electrodes 179 and the auxiliary common electrodes 180 (Not shown), and the second auxiliary common connection pattern (not shown) is electrically connected to the first auxiliary common connection pattern (not shown) through a plurality of common contact holes .

In the storage region StgA, a pixel connection pattern 177 made of the same material as the pixel electrode 178 is formed to overlap the common wiring 109 and form a storage capacitor StgC. At this time, the common wiring 109 and the pixel connection pattern 177 overlapping each other via the gate insulating layer 120 constitute first and second storage electrodes, respectively. In the gate and data pad portions GPA and DPA, gate and data pad contact holes (corresponding to the gate and data pad electrodes 117 and 118, respectively) corresponding to the plurality of pixel electrodes 178 are formed, 145, and 147, respectively, and gate and data auxiliary pad electrodes 182 and 183 are formed, respectively. The pixel connection pattern 177 and the gate and data assistant pad electrodes 182 and 183 are formed by the source and drain electrodes 154 and 156 of the double layer structure and the lower layers 154a, ) Is formed by the same process.

In addition, as another characteristic part of the present invention, the plurality of pixel electrodes 178, the central common electrode 179, the auxiliary common electrode 180, the pixel connection pattern 177, A second protective layer 175 is formed as an inorganic insulating material in a portion except for a connection pattern (not shown).

Next, columnar patterned spacers 184 are formed on the second passivation layer 175 at predetermined intervals corresponding to the data lines 152.

Hereinafter, a method of manufacturing an array substrate for a COT-structured transverse electric field type liquid crystal display device having the above-described structure will be described with reference to the drawings.

FIGS. 7A to 7E are process plan views of a pixel region of an array substrate for a COT-structured transverse electric field type liquid crystal display device according to the present invention. FIGS. 8A to 8J are sectional views taken along the line IV- FIGS. 9A to 9J are cross-sectional views illustrating steps of manufacturing a gate pad portion (GPA) of an array substrate for a COT-structured transverse electric field type liquid crystal display according to the present invention. 10A to 10J are cross-sectional views illustrating a data pad unit (DPA) of an array substrate for a COT-structured transverse electric field type liquid crystal display according to the present invention. At this time, although the process plan view has a pixel electrode having a linear bar shape and a central common electrode, a structure in which the central portion of the pixel is bent by the same process may be realized.

First, as shown in FIGS. 7A, 8A, 9A, and 10A, a first metal layer (not shown) is formed on the entire surface of a transparent insulating substrate 101 by depositing a first metal material on the entire surface, A gate wiring 111 and a common wiring 109 extending in a direction spaced by a predetermined distance from the gate wiring 105 are formed . A first auxiliary common connection pattern 115 for connecting the outermost common electrode 114 and one end of the outermost common electrode 114 in the shape of a branch from the common line 109 is formed in each pixel region P, . At this time, the outermost common electrode 114 may be formed so that its central portion is bent in each pixel region P so as to be vertically symmetrical. In the gate pad portion GPA and the data pad portion DPA, a gate pad electrode 117 connected to the gate wiring 105 and an island-shaped data pad electrode 118 are respectively formed. At this time, the data pad electrode 118 is electrically connected to a data line to be formed later.

Next, as shown in FIGS. 7B, 8B, 9B and 10B, the gate electrode 111, the gate wiring 105, the common wiring 109, the outermost common electrode 114, The gate insulating film 120 is formed on the entire surface by depositing an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN x) on the gate insulating film 115 and the gate and data pad electrodes 117 and 118.

Thereafter, a pure amorphous silicon layer (not shown) and an impurity amorphous silicon layer (not shown) are formed by sequentially depositing pure amorphous silicon and impurity amorphous silicon on the entire surface of the gate insulating layer 120, The active layer 124 of pure amorphous silicon having the same island shape and size and the impurity amorphous silicon pattern 127 of the impurity amorphous silicon are sequentially stacked in the switching region TrA corresponding to the gate electrode 111, . At this time, the gate insulating layer 120 corresponding to the central portion of the gate pad electrode 117 is removed in the gate pad portion GPA by the same process to expose the gate pad electrode 117, The second data pad contact 118 exposes the data pad electrode 118 by removing the gate insulating layer 120 corresponding to the central portion of the data pad electrode 118 in the data pad portion DPA. The hole 122 is formed. Also, a plurality of first common contact holes 123 exposing the first auxiliary common connection pattern 115 electrically connected to the common wiring 109 are formed. In this process, a photoresist layer (not shown) is formed on the impurity amorphous silicon layer (not shown), and then a halftone exposure or slit exposure is performed using an exposure mask (not shown) including a transflective region First and second photoresist patterns (not shown) having different thicknesses are formed, and portions exposed to the outside of the first and second photoresist patterns (not shown), that is, The impurity and the pure amorphous silicon layer (not shown) and the gate insulating layer 120 are removed corresponding to the portions where the holes 121 and 122 and the plurality of first common contact holes 123 are to be formed, Holes 121 and a first data pad contact hole 122 and a plurality of first common contact holes 123 are formed on the substrate 100. After the second photoresist pattern (not shown) having a small thickness is removed, Newly exposed part The active layer 124 and the impurity amorphous silicon pattern 127 are formed by removing the impurity and the pure amorphous silicon layer (not shown), exposing the gate insulating layer 120, and further forming the first photoresist pattern ). ≪ / RTI >

Next, as shown in FIGS. 7C, 8C, 9C, and 10C, on the gate insulating film 120 of the pixel region P in which the active layer 124 and the impurity amorphous silicon pattern 127 are formed, The color filter layer 140 is formed in such a manner that the green color and the blue color are sequentially and repeatedly formed. At this time, the color filter layer 140 is not formed in regions where the gate wirings 105 and the common wirings 109 adjacent to each other are formed, particularly the switching region TrA and the storage region StgA. The reason why the switching region TrA and the storage region StgA are formed so as to be exposed to the color filter layer 140 is that the source and drain electrodes (not shown) are not formed in the switching region TrA In order to form a channel region in the ohmic contact layer and the active layer 124 in the storage region TrA and to correspond to the common wiring 109 serving as the first storage electrode, (Not shown) is formed by forming only the gate insulating film as the dielectric layer on the pixel connection pattern 162 serving as a gate electrode. At this time, the color filter layer 140 is formed by forming a red color filter pattern 140a on one pixel region P by applying a red resist over the entire surface, exposing and developing the same, and patterning the red color filter pattern 140a. Green, and blue color filter patterns 140a and 140b (not shown) are sequentially and repeatedly formed for each pixel region P by progressing the red, green, and blue color filter patterns 140a and 140b.

Next, as shown in FIGS. 7D, 8D, 9D and 10D, a hybrid type insulating material having a photosensitive characteristic on the front surface is deposited on the color filter layer 140, for example, OSQ or photoacryl to deposit a first protective layer And the impurity amorphous silicon pattern 127 is exposed in correspondence with the switching region TrA by patterning the resist film by performing only exposure and development without an etching process, A second gate and data pad contact holes 145 and 147 are formed to expose the gate and data pad electrodes 117 and 118 respectively corresponding to the first and second data lines 121 and 122, A second common contact hole 148 exposing the first auxiliary common connection pattern 115 is formed corresponding to the common contact hole 123 (FIG. 7C).

Next, as shown in FIGS. 7E, 8E, 9E and 10E, the second gate pad contact hole 145, the second data pad contact hole 147 and the plurality of second common contact holes 148 are provided Molybdenum alloy (MoTi) or indium-tin-oxide (ITO), which is a transparent conductive material, is deposited on the entire surface of the substrate 101 over the first protective layer 143 to form a second metal layer 149, One of copper (Cu), copper alloy, aluminum (Al), and aluminum alloy (AlNd), which are low-resistance materials, is deposited on the second metal layer 149 to form a third metal layer 150. Then, a photoresist layer (not shown) is formed on the third metal layer 150 to form third and fourth photoresist patterns 185a and 185b having different thicknesses from each other . A third photoresist pattern 185a having a first thickness corresponding to the gate pad electrode 117 and the data pad electrode 118 is formed in the gate and data pad portions GPA and DPA, Corresponding to a portion where a pixel electrode (not shown), a central common electrode (not shown), a second auxiliary common connection pattern (not shown) and an auxiliary common electrode (not shown) are to be formed, A photoresist pattern 185a is formed and a fourth photoresist pattern 185b having a second thickness that is thinner than the first thickness is formed corresponding to a portion where a data line (not shown) is to be formed. At the same time, in the switching region TrA, a fourth photoresist pattern 185b having the second thickness is formed corresponding to a portion where source and drain electrodes (not shown) are to be formed. In the storage region StgA, a third photoresist pattern 185a is formed, but a fourth photoresist pattern may be formed.

On the other hand, the photoresist layer (not shown) is removed so that the third metal layer 150 is exposed to regions other than the above-described regions.

Next, as shown in FIGS. 7E, 8F, 9F and 10F, a third metal layer (150 of FIGS. 8D, 9D and 10D) exposed to the outside of the third and fourth photoresist patterns 185a and 185b, Layered data lines 152 (152a and 152b) are formed by etching and removing the two metal layers (149 in Figs. 8D, 9D and 10D) to cross the gate wirings 105 to define the pixel regions P A plurality of central common electrodes 166a and 166b and a plurality of pixel electrodes 164a and 164b are formed in the pixel region P at regular intervals and alternately and each having a bilayer structure, Layered auxiliary common electrodes 167 (167a and 167b) overlapping with the outermost common electrode 114 are formed and the auxiliary common electrodes 167 (167a and 167b) of the double layer structure and the plurality Layered second auxiliary common connection patterns 168 (1678a and 168b) connecting the central common electrodes 166 (166a and 166b). At this time, the second common connection patterns 168 (1678a, 168b) are brought into contact with the first common connection pattern 115 located below the second common connection holes 148.

Further, in the switching region TrA, the third and second metal layers (150 and 149 of FIGS. 8D, 9D, and 10D) exposed between the fourth photoresist patterns 185b are removed, An ohmic contact layer 128 spaced apart from the active layer 124 by removal of the impurity amorphous silicon pattern (127 in FIG. 8D) by dry etching is formed on the ohmic contact layer 128, Source and drain electrodes 154 (154a, 154b), 156 (156a, 156) are formed. The semiconductor layer 130 including the active layer 124 and the ohmic contact layer 128 and the source and drain electrodes 154 and 156, which are sequentially stacked, and the gate electrode 111, the gate insulating layer 120, Form a thin film transistor Tr.

In the storage region StgA, a pixel connection pattern 162 (162a, 162b) having a double-layer structure serving as a second storage electrode is formed corresponding to the common wiring 109 serving as the first storage electrode .

In the gate pad portion GPA, auxiliary gate pad electrodes 169 (169a and 169b) having a double-layer structure are formed to contact the gate pad electrode 117 through the second gate pad contact hole 145 Layered auxiliary data pad electrode 170 (170a, 170b) that contacts the data pad electrode 118 through the second data pad contact hole 147 is formed in the data pad unit DPA do.

In this case, the source and drain electrodes 154 and 156 do not have the active layer is formed for both ends, the data line 152 that is lower in the semiconductor pattern is not formed bar-way non-noise and the off current (I _off) increases No problem occurs.

Next, as shown in FIGS. 7E, 8G, 9G and 10G, ashing is performed to remove the fourth photoresist pattern (185b in FIG. 8D) of the second thickness, Thereby exposing the source and drain electrodes 154 and 156 having a bilayer structure. Although not shown in the drawing, when the fourth photoresist pattern is formed in the storage region StgA, the pixel connection pattern of the double-layer structure is also exposed. At this time, the thickness of the third photoresist pattern 185a is reduced by the ashing, but the thickness of the third photoresist pattern 185a is still thicker than the fourth photoresist pattern 185b (FIG. 8D) Respectively.

Next, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the entire surface of the third photoresist pattern 185a having a reduced thickness to form an inorganic insulating layer 173. In this case, the inorganic insulating layer 173 exposes the active layer 124 exposed between the source and drain electrodes 154 and 156 in the region exposed to the outside of the third photoresist pattern 185a, especially in the switching region TrA. And the source and drain electrodes 154 and 156, respectively. Therefore, it protects the active layer 124 exposed between the source and drain electrodes 154 and 156.

Next, as shown in Figs. 7E, 8H, 9H and 10H, the substrate 101 on which the inorganic insulating layer (173 of Figs. 8G, 9G and 10G) is formed is exposed to the strip liquid to form the third photoresist pattern A lift off process is performed to remove the inorganic insulating layers 185a (FIGS. 8g, 9g, and 10g) and the upper and side surfaces of the inorganic insulating layers (FIG. 8g, 9g, and 10g). At this time, the substrate 101 may be subjected to a heat treatment in order to perform a smooth lift-off process. 8g, 9g, and 10g), the third photoresist pattern (185a of FIGS. 8g, 9g, and 10g) cracks to the inorganic insulating layer (173 of FIGS. 8g, 9g, and 10g) And a lift off process is smoothly performed by penetrating the strip liquid through the cracked portion. 8G, 9G, and 10G) is completely covered with the third photoresist pattern (185a in FIGS. 8G, 9G, and 10G), the third and second metal layers 8g, 9g, and 10g) by progressing the over-etching angle at the time of patterning the first photoresist pattern (150a, 150b, 150c, 150d, The constituent elements made of the third and the second metallic materials such as the central common electrode 166 of the double layer structure have a width smaller than the width of the third photoresist pattern (185a in FIGS. 9g, 10g, 11g and 12g) And is formed in an undercut shape with respect to the third photoresist pattern (185a of FIGS. 8g, 9g, and 10g). When the inorganic insulating material is deposited in this state, the side surface of the third photoresist pattern (185a of FIGS. 8g, 9g, and 10g), the side surface of the pixel electrode 164 and the central common electrode 166, So that the strip liquid comes into contact with the third photoresist pattern (185a of FIGS. 8g, 9g, and 10g) through the portion where the break occurs.

Accordingly, when the above-described lift-off process is completed, as shown in the figure, corresponding to a region exposed to the outside of the second photoresist pattern (185a of Figs. 8g, 9g, and 10g) A second protective layer 175 made of an inorganic insulating material is formed.

Next, as shown in FIGS. 7E, 8I, 9I and 10I, the etch rate of the metal material having a predetermined selective etch rate with respect to the second passivation layer 175 and the component made of the third metal material (163, 166, 167, 169, 170) having a bilayer structure exposed to the outside of the second protective layer (175) by performing etching using an etchant A plurality of pixel electrodes 178 and a central common electrode 179 having a single layer structure by removing the upper layer (162b, 164b, 166b, 167b, 169b, The common electrode 180 and the second common connection pattern 181 are formed and at the same time the gate and data auxiliary pad electrodes 182 and 183 having a single layer structure in the gate and data pad portions GPA and DPA . In the case of the pixel connection pattern 177 serving as the second storage electrode, although it is shown as having a single layer structure in the drawings, it may have a double layer structure. At this time, due to the characteristics of the etchant, the plurality of pixel electrodes 178, the central common electrode 179, the auxiliary common electrode 180, and the second protection around the second common connection pattern 181 The layer 175 is also partially removed, so that the portion having the rough surface by the lift-off process has a smooth surface.

Next, as shown in FIGS. 7F, 8J, 9J and 10J, a plurality of pixel electrodes 178 and a central common electrode 179 having a single layer structure with the second protective layer 175 selectively formed, An organic insulating material layer (not shown) is formed on the auxiliary common electrode 180, the second common connection pattern 181 and the gate and data auxiliary pad electrodes 182 and 183 to form an organic insulating material layer A patterned spacer 184 is formed on the second passivation layer 175 corresponding to the data line 152 formed on the color filter layer 140 to form a patterned spacer 184 on the array substrate for a COT structure transverse electric field type liquid crystal display 101).

In the case of the array substrate 101 for a COT-structured transverse electric field type liquid crystal display completed by the above-described manufacturing method, the gate electrode 111 is completely overlapped with the source and drain electrodes 154 and 156 having a bilayer structure, having a thin film transistor according to the island shape by increasing the active layer bar, which is 124, to form the source and drain electrodes (154, 156) current, so the ends are not the active layer 124 is exposed with only the outer-off (I _off) ( Tr can be prevented from being deteriorated. Further, since the semiconductor pattern is not formed under the data line 152, the occurrence of the no-noise can be suppressed and the display quality can be improved.

Further, by forming the color filter layer 140 on the array substrate 101 so that the color filter patterns 140a and 140b (not shown) are located at the boundaries of the pixel regions P, the margin due to the adhesion error is reduced to improve the aperture ratio .

1 is an exploded perspective view of a general liquid crystal display device.

2 is a cross-sectional view of one pixel region including a thin film transistor which is a switching element of a conventional COT-structured transverse electric field liquid crystal display device.

3 is a plan view of one pixel region of an array substrate of a COT-structured transverse electric field type liquid crystal display device according to an embodiment of the present invention.

4 is a cross-sectional view of a portion cut along line IV-IV of FIG. 3;

5 is a sectional view of a gate pad portion of an array substrate of a COT-structured transverse electric field type liquid crystal display device according to an embodiment of the present invention.

6 is a cross-sectional view of a data pad portion of an array substrate of a COT-structured transverse electric field type liquid crystal display device according to an embodiment of the present invention.

7A to 7F are process plan views of a pixel region of an array substrate for a COT-structured transverse electric field type liquid crystal display according to the present invention.

Figs. 8A to 9J are cross-sectional views illustrating steps taken along the cutting line IV-IV of Fig. 3 for manufacturing steps. Fig.

9A to 9J are cross-sectional views illustrating steps of manufacturing the gate pad portion of the array substrate for a COT-structured transverse electric field type liquid crystal display according to the present invention.

10A to 10J are cross-sectional views illustrating a data pad portion of an array substrate for a COT-structured transverse electric field type liquid crystal display according to an embodiment of the present invention.

Description of the Related Art

101: (array) substrate 105: gate wiring

109: common wiring 111: gate electrode

114: outermost common electrode 120: gate insulating film

124: active layer 128: ohmic contact layer

129 (124, 128): semiconductor layer 152: data wiring

140 (140a, 140b): Color filter layer

140a, 140b: red, green color filter pattern 143: first protective layer

154: source electrode 156: drain electrode

177: pixel connection pattern 178: pixel electrode

179: central common electrode 180: auxiliary common electrode

184: Patterned spacer

P: pixel area StgA: storage area

StgC: storage capacitor Tr: thin film transistor

TrA: switching area

Claims (17)

Forming a common wiring on the substrate in parallel with the gate wiring extending in one direction; Forming an island-shaped active layer corresponding to a switching region in which a thin film transistor on the gate wiring is to be formed over the gate insulating film, and forming an impurity amorphous silicon pattern on the common wiring over the common wiring; Wow; Forming a color filter layer in an area other than the switching area; Forming a first protective layer over the color filter layer; Forming first and second metal layers on the entire surface of the substrate to expose the impurity amorphous silicon pattern on the first passivation layer; Layer structure in which the first and second metal layers are patterned to define a pixel region intersecting with the gate wiring over the first protective layer, and a plurality of double-layer structures alternately spaced apart from each other in the pixel region And forming a plurality of central common electrodes connected to the common wiring, the method comprising: forming source and drain electrodes spaced apart from each other in a bilayer structure in the switching region and an ohmic contact layer spaced apart from the source and drain electrodes; Forming a second passivation layer covering the exposed active layer between the source and drain electrodes; Forming a plurality of pixel electrodes and a central common electrode of a single layer structure between the second passivation layers by removing the pixel electrodes of the double layer structure and the upper layer of the central common electrode And a plurality of pixel electrodes formed on the substrate. The method according to claim 1, The step of forming a common wiring with the gate wiring includes: Further comprising a first common connection pattern which branches off from the common wiring and connects an outermost common electrode located at an outermost periphery of the pixel region and an end of the outermost common electrode Gt; 3. The method of claim 2, Wherein forming the first passivation layer comprises: And forming a plurality of common contact holes exposing the first common connection pattern. The method of claim 3, Forming a plurality of pixel electrodes and a central common electrode of the double- A second common connection pattern of a bilayer structure connecting one end of the plurality of central common electrodes of the double layer structure and contacting the first common connection pattern through the plurality of common contact holes, A second common electrode connected to the second common connection pattern, and a pixel connection pattern of a double-layer structure connected to the plurality of pixel electrodes of the double-layer structure. The method according to claim 1, The step of forming the double-layered data line, the plurality of pixel electrodes of a bilayer structure, the plurality of central common electrodes of a bilayer structure, the source and drain electrodes of a bilayer structure, and the ohmic contact layer, A first photoresist pattern having a first thickness corresponding to the source and drain electrodes and the data line is formed on the second metal layer and a second photoresist pattern having a second thickness corresponding to the pixel electrodes and the central common electrode of the double- Forming a thick second photoresist pattern; Removing the second and first metal layers exposed outside the first and second photoresist patterns; Removing the exposed impurity amorphous silicon pattern by removing the second and first metal layers And a plurality of pixel electrodes formed on the substrate. 6. The method of claim 5, Wherein forming the second passivation layer comprises: Performing ashing to remove the first photoresist pattern; Forming an inorganic insulating layer over the entire surface of the newly exposed double-layered data line and source and drain electrodes by removing the first photoresist pattern; Exposing the substrate on which the inorganic insulating layer is formed to the strip liquid, and performing a lift-off process of removing the second photoresist pattern and the inorganic insulating layer formed on the top and side surfaces of the second photoresist pattern together And a plurality of pixel electrodes formed on the substrate. The method according to claim 6, Wherein forming the plurality of pixel electrodes and the central common electrode of the single- Wherein the second metal layer and the inorganic insulating layer are simultaneously etched and the etching rate of the second metal layer is faster than the etching rate of the inorganic insulating layer. And removing the upper layer of the central common electrode. 8. The method of claim 7, Wherein the second protective layer covers the data line and the source and drain electrodes and is formed in a region between the plurality of pixel electrodes of the single layer structure and the central common electrode. Claim 9 has been abandoned due to the setting registration fee. The method according to claim 1, And forming a plurality of patterned spacers on the second protective layer, the patterned spacers being spaced apart from each other by a predetermined distance corresponding to the data lines. The method according to claim 1, The step of forming a common wiring with the gate wiring includes: A gate pad electrode connected to one end of the gate wiring, and a data pad electrode. 11. The method of claim 10, Wherein the data line is formed so that one end of the data pad electrode is in contact with the data pad electrode. 12. The method of claim 11, Wherein forming the first passivation layer comprises: A gate pad contact hole exposing the gate pad electrode, and a data pad contact hole exposing the data pad electrode. 12. The method of claim 11, Wherein forming the plurality of pixel electrodes and the central common electrode of the single- A gate pad electrode of a single layer structure contacting the gate pad electrode through the gate pad contact hole and an auxiliary data pad electrode of a single layer structure contacting the data pad electrode through the data pad contact hole, And forming a plurality of pixel electrodes on the array substrate. 5. The method of claim 4, Wherein the pixel connection pattern of the double layer structure is formed so as to overlap with the common wiring so that the common wiring and the pixel connection pattern of the double layer structure overlapping each other via the gate insulation film form a storage capacitor for the manufacture of an array substrate for a liquid crystal display Way. 15. The method of claim 14, Wherein forming the plurality of pixel electrodes and the central common electrode of the single- And removing the upper layer of the pixel connection pattern of the double layer structure to form a pixel connection pattern of a single layer structure. The method according to claim 1, A plurality of central common electrodes and an outermost common electrode of the single layer structure and a plurality of pixel electrodes of the single layer structure are formed to have a symmetrically bent structure with respect to a central portion of the pixel region Wherein the method comprises the steps of: The method according to claim 1, Wherein the active layer is formed to have a smaller size than the gate wiring and to have the gate wiring exposed around the active layer.

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