KR20050029917A - Method for manufacturing meel device - Google Patents
Method for manufacturing meel device Download PDFInfo
- Publication number
- KR20050029917A KR20050029917A KR1020030066191A KR20030066191A KR20050029917A KR 20050029917 A KR20050029917 A KR 20050029917A KR 1020030066191 A KR1020030066191 A KR 1020030066191A KR 20030066191 A KR20030066191 A KR 20030066191A KR 20050029917 A KR20050029917 A KR 20050029917A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- forming
- floating gate
- nitride film
- layer
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 title claims description 26
- 150000004767 nitrides Chemical class 0.000 claims abstract description 35
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 229920005591 polysilicon Polymers 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 230000005641 tunneling Effects 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 238000011065 in-situ storage Methods 0.000 claims abstract description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 238000005121 nitriding Methods 0.000 claims description 3
- 239000007789 gas Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000009835 boiling Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000010893 electron trap Methods 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Formation Of Insulating Films (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 MEEL 소자의 제조방법에 관한 것으로, 보다 상세하게는, MEEL(Merged EEPROM & Logic) 소자의 컨트롤/플로팅 게이트 구현에 있어서 MEEL 소자의 특성을 개선할 수 있는 MEEL 소자의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a MEEL device, and more particularly, to a method of manufacturing a MEEL device that can improve the characteristics of the MEEL device in the implementation of the control / floating gate of the MEEL (Merged EEPROM & Logic) device. .
디램(DRAM)과 로직(Logic) 또는 이이피롬(EEPROM)과 로직(Logic)을 단일 칩에 구현한 반도체 소자가 최근들어 그 관심이 높아지고 있다. 이것은 디램 또는 이이피롬 로직이 단일 칩에 구현되는 것과 관련해서 칩의 크기가 증가하고 제조 공정이 복잡하며 제조 수율이 낮다는 단점은 있지만, 단일 칩에 디램 또는 이이피롬 로직이 구현되는 것으로부터 기존 칩들에 비해 고속 및 저전력 구동이 가능한 잇점을 갖기 때문이다.In recent years, semiconductor devices that implement DRAM and logic, or EEPROM and logic on a single chip have recently gained increasing interest. This has the disadvantage of increasing the size of the chip, complicated manufacturing process and low manufacturing yield with respect to the implementation of DRAM or Ipyrom logic on a single chip, but existing chips from the implementation of DRAM or Ipyrom logic on a single chip. This is because the high speed and low power can be driven compared to the advantages.
이하에서는 종래 MEEL 소자의 제조방법에 대해 도 1a 내지 도 1f를 참조하여 설명하도록 한다. 여기에서, 각 도면 및 설명은 이이피롬 셀에 대해서만 도시하고 설명하도록 한다.Hereinafter, a method of manufacturing a conventional MEEL device will be described with reference to FIGS. 1A to 1F. Here, each drawing and description are shown and described only for an ypyrom cell.
먼저, 도 1a에 도시된 바와 같이, 실리콘 기판(1) 상에 터널링 산화막(3)과 플로팅 게이트용 폴리 실리콘막(5)을 차례대로 형성한 후에 하드마스크용 산화막(7)을 증착하고, 플로팅 게이트를 형성하기 위한 감광막 패턴(9)을 형성한다. 이때, 플로팅 게이트용 폴리 실리콘막(5)은 캐패시턴스(Capacitance)를 높이기 위해 기존의 로직(Logic) 공정에서 적용하는 폴리 실리콘막보다 훨씬 두껍게 약 3500~4000Å 정도로 형성한다.First, as shown in FIG. 1A, a tunneling oxide film 3 and a floating gate polysilicon film 5 are sequentially formed on the silicon substrate 1, and then, an oxide film 7 for hard mask is deposited and floated. The photosensitive film pattern 9 for forming a gate is formed. In this case, the floating gate polysilicon film 5 is formed to be about 3,500 to 4000 microns thicker than the polysilicon film applied in a conventional logic process in order to increase capacitance.
그 다음, 도 1b에 도시된 바와 같이, 감광막 패턴(9)을 식각 마스크로 사용하여 하드마스크용 산화막(7)과 플로팅 게이트용 폴리 실리콘막(5)에 차례대로 비등방성 식각 공정을 진행한다. 이때, 터널링 산화막(3)을 식각정지용막으로 사용한다.Next, as shown in FIG. 1B, an anisotropic etching process is sequentially performed on the hard mask oxide film 7 and the floating gate polysilicon film 5 using the photoresist pattern 9 as an etching mask. At this time, the tunneling oxide film 3 is used as an etch stop film.
이어서, 도 1c에 도시된 바와 같이, 로직에서의 ONO(Oxide-Nitride-Oxide) 캐패시터를 구현하기 위해 기판(1) 결과물 상에 질화막(11) 및 산화막(13)을 차례대로 형성한다.Subsequently, as illustrated in FIG. 1C, a nitride film 11 and an oxide film 13 are sequentially formed on the resultant substrate 1 to implement an oxide-nitride-oxide (ONO) capacitor in logic.
그 다음, 도 1d에 도시된 바와 같이, 하드마스크용 산화막(7)이 노출되도록 산화막(13) 및 질화막(11)을 차례로 비등방성 식각하고 이를 통해 ONO 구조의 컨트롤 게이트용 절연막(이하, ONO 절연막이라 칭함)을 형성한다. Next, as shown in FIG. 1D, the oxide film 13 and the nitride film 11 are anisotropically etched sequentially so that the hard mask oxide film 7 is exposed, and through this, an insulating film for a control gate having an ONO structure (hereinafter referred to as an ONO insulating film). Called).
이어서, 도 1e에 도시된 바와 같이, 상기 결과물의 전면 상에 컨트롤 게이트용 폴리 실리콘막(15)을 형성하고, 컨트롤 게이트를 형성하기 위한 감광막 패턴(17)을 형성한다. Subsequently, as shown in FIG. 1E, the polysilicon film 15 for the control gate is formed on the entire surface of the resultant product, and the photosensitive film pattern 17 for forming the control gate is formed.
그 다음, 도 1f에 도시된 바와 같이, 감광막 패턴(17)을 식각 마스크로 사용하여 컨트롤 게이트용 폴리 실리콘막(15)에 비등성 식각 공정을 진행함으로써 컨트롤 게이트(15a)를 형성한다.Next, as shown in FIG. 1F, the control gate 15a is formed by performing an boiling etching process on the polysilicon film 15 for control gate using the photoresist pattern 17 as an etching mask.
이후, 도시하지는 않았으나, 배선 공정을 포함한 일련의 후속 공정을 진행하여 MEEL 소자를 제조한다.Subsequently, although not shown, a series of subsequent processes including a wiring process are performed to manufacture the MEEL device.
상기와 같은 종래 MEEL 소자의 ONO 절연막은 FN(Fowler Nordheim) 터널링 전자를 트래핑(Trapping) 하고, 트래핑(Trapping)된 전자를 계속 유지하려는 역할을 한다.The ONO insulating layer of the conventional MEEL device serves to trap FN (Fowler Nordheim) tunneling electrons and to maintain the trapped electrons.
그러나, ONO 절연막의 두께를 얇게 형성하면 터널링 전자의 트래핑은 향상되나, 유전체막이 얇기 때문에 트래핑된 전자들이 빠져나가게 되어 누설 전류가 발생된다. However, if the thickness of the ONO insulating film is formed to be thin, the trapping of the tunneling electrons is improved. However, since the dielectric film is thin, the trapped electrons are released and a leakage current is generated.
또한, ONO 절연막의 두께를 두껍게 형성하면, 전자를 계속 유지하려는 전자 유지(Retention) 능력은 향상되나, FN 터널링 전자를 트래핑하는 경우에 절연막이 두껍기 때문에 소자를 구동시 높은 전압을 인가해야 하는 단점을 가지고 있다.In addition, if the thickness of the ONO insulating film is formed to be thick, the electron retention ability to keep the electrons is improved, but the insulating film is thick when trapping the FN tunneling electrons, so that a high voltage must be applied when driving the device. Have.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, MEEL 소자의 FN 터널링 전자 트래핑 특성 및 전자 유지 능력을 동시에 개선할 수 있는 MEEL 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a MEEL device that can simultaneously improve the FN tunneling electron trapping characteristics and the electron holding ability of the MEEL device.
상기 목적을 달성하기 위한 본 발명은, 실리콘 기판 상에 터널링 산화막과 플로팅 게이트용 폴리 실리콘막 및 하드마스크용 산화막을 차례로 형성하는 단계; 상기 하드마스크용 산화막과 플로팅 게이트용 폴리 실리콘막을 식각하여 플로팅 게이트를 형성하는 단계; 상기 노출된 플로팅 게이트의 측면을 질화(Nitridation)시켜 제1 질화막을 형성하는 단계; 상기 기판 결과물의 전면 상에 인-시튜 공정으로 제2 질화막을 형성하는 단계; 상기 제2 질화막 상에 산화막을 형성하는 단계; 상기 산화막과 제2 질화막을 식각하여 ONO 구조의 컨트롤 게이트용 절연막을 형성하는 단계; 상기 ONO 구조의 절연막 상에 컨트롤 게이트용 폴리 실리콘막을 형성하는 단계; 및 상기 컨트롤 게이트용 폴리 실리콘막을 식각하여 컨트롤 게이트를 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention for achieving the above object comprises the steps of sequentially forming a tunneling oxide film, a floating silicon polysilicon film and a hard mask oxide film on a silicon substrate; Forming a floating gate by etching the hard mask oxide layer and the floating gate polysilicon layer; Nitriding the exposed side of the floating gate to form a first nitride film; Forming a second nitride film on an entire surface of the substrate result by an in-situ process; Forming an oxide film on the second nitride film; Etching the oxide film and the second nitride film to form an insulating film for a control gate having an ONO structure; Forming a polysilicon film for a control gate on the insulating film having the ONO structure; And forming a control gate by etching the poly silicon film for the control gate.
(실시예)(Example)
이하, 본 발명의 바람직한 실시예에 대해 첨부된 도면을 참조하여 상세하게 설명한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 MEEL 소자의 제조방법을 설명하기 위한 공정별 단면도이다.2A to 2E are cross-sectional views of processes for explaining a method of manufacturing a MEEL device according to an exemplary embodiment of the present invention.
도 2a에 도시된 바와 같이, 실리콘 기판(21) 상에 터널링 산화막(23)과 플로팅 게이트용 폴리 실리콘막(25) 및 하드마스크용 산화막(27)을 차례로 형성하고, 플로팅 게이트를 형성하기 위한 감광막 패턴(29)을 형성한다. 이때, 플로팅 게이트용 폴리 실리콘막(25)은 퍼니스(Furnace) CVD(Chemical Vapor Deposition) 공정을 사용하며, SiH4, Si2H6, DCS 가스를 사용할 수 있다. 또한, 플로팅 게이트용 폴리 실리콘막(25)은 500~650℃의 온도에서 1000~5000Å의 두께로 형성된다.As shown in FIG. 2A, a tunneling oxide film 23, a floating gate polysilicon film 25, and a hard mask oxide film 27 are sequentially formed on the silicon substrate 21 to form a floating gate. The pattern 29 is formed. In this case, the floating silicon polysilicon layer 25 uses a furnace (CVD) chemical vapor deposition (CVD) process, and SiH 4 , Si 2 H 6 , and DCS gas may be used. The floating silicon polysilicon film 25 is formed to a thickness of 1000 to 5000 kPa at a temperature of 500 to 650 占 폚.
그 다음, 도 2b에 도시된 바와 같이, 감광막 패턴(29)을 식각 마스크로 이용하여 하드마스크용 산화막(27)과 플로팅 게이트용 폴리 실리콘막(25)에 차례대로 비등방성 식각 공정을 진행하여 플로팅 게이트(28)를 형성한다. 이때, 터널링 산화막(23)을 식각정지용막으로 사용한다.Next, as shown in FIG. 2B, the anisotropic etching process is sequentially performed on the hard mask oxide layer 27 and the floating gate polysilicon layer 25 by using the photoresist pattern 29 as an etching mask. The gate 28 is formed. At this time, the tunneling oxide film 23 is used as an etch stop film.
이어서, 도 2c에 도시된 바와 같이, 상기 노출된 플로팅 게이트(28)의 측면을 질화(Nitridation)시켜 제1 질화막(31)을 형성한다. 이때, 제1 질화막(31)을 형성하기 위해 습식 또는 건식 분위기의 퍼니스 공정(30)으로 수행하거나 또는 RTP(Rapid Thermal Process) 공정으로 진행한다. Subsequently, as illustrated in FIG. 2C, the exposed side of the floating gate 28 is nitrided to form the first nitride film 31. At this time, in order to form the first nitride film 31, it is performed by the furnace process 30 in a wet or dry atmosphere or proceeds to a rapid thermal process (RTP) process.
또한, 제1 질화막(31)을 형성하기 위해 800~1200℃의 퍼니스 내에 NO 또는 N20, NH3 가스로 구성된 그룹으로부터 선택되는 어느 하나를 1~30 SLM(Standard Liters Per Minute)으로 주입시킨다. 그리고, 제1 질화막(31)을 10~100Å의 두께로 형성한다.In addition, in order to form the first nitride film 31, any one selected from the group consisting of NO, N 2 O and NH 3 gas is injected into a 1 to 30 standard liters per minute (SLM) in a furnace at 800 to 1200 ° C. . The first nitride film 31 is formed to a thickness of 10 to 100 GPa.
이렇게 제1 질화막(31)은 플로팅 게이트(28) 측면의 실리콘과 NO 또는 N20, NH3에서 열분해된 질소의 반응을 유도시켜 형성되며, 퍼니스 공정(30)은 온도, 가스의 종류, 가스 주입률에 따라 제어할 수 있다.Thus, the first nitride film 31 is formed by inducing the reaction of silicon on the side of the floating gate 28 with nitrogen pyrolyzed in NO or N 2 O, NH 3 , the furnace process 30 is the temperature, type of gas, gas It can be controlled according to the injection rate.
그 다음, 도 2d에 도시된 바와 같이, ONO 캐패시터를 구현하기 위해 기판(21) 결과물의 전면 상에 인-시튜(In-situ) 공정으로 제2 질화막(33)을 형성하고 제2 질화막(33) 상에 산화막(35)을 형성한다. 이때, 제2 질화막(33)과 산화막(35)은 각각 50~200Å 및 300~500Å의 두께로 형성된다.Next, as shown in FIG. 2D, the second nitride film 33 is formed on the entire surface of the substrate 21 by an in-situ process to implement the ONO capacitor, and the second nitride film 33 is formed. ), An oxide film 35 is formed. At this time, the second nitride film 33 and the oxide film 35 are formed to have a thickness of 50 to 200 kPa and 300 to 500 kPa, respectively.
도시되지 않았으나, 산화막(35) 및 제2 질화막(33)을 식각하여 ONO 구조의 컨트롤 게이트용 절연막을 형성한다. 계속해서, ONO 구조의 절연막 상에 컨트롤 게이트용 폴리 실리콘막(미도시)을 형성하고, 컨트롤 게이트를 형성하기 위한 감광막 패턴(미도시)을 형성한다.Although not shown, the oxide film 35 and the second nitride film 33 are etched to form an insulating film for a control gate having an ONO structure. Subsequently, a control gate polysilicon film (not shown) is formed on the insulating film of the ONO structure, and a photosensitive film pattern (not shown) for forming the control gate is formed.
이어서, 도 2e에 도시된 바와 같이, 감광막 패턴(미도시)을 식각 마스크로 사용하여 컨트롤 게이트용 폴리 실리콘막(미도시)에 비등성 식각 공정을 진행하므로써 컨트롤 게이트(37)를 형성한다.Subsequently, as shown in FIG. 2E, the control gate 37 is formed by performing a boiling process on the polysilicon film (not shown) for the control gate using the photoresist pattern (not shown) as an etching mask.
따라서, 본 발명은 실리콘 기판 상에 플로팅 게이트를 형성한 후에 노출된 플로팅 게이트의 측면을 질화시켜 제1 질화막을 형성하고, 기판 결과물 전면 상에 인-시튜 공정으로 제2 질화막을 형성함으로써 터널링 전자 트래핑 기능을 향상시킬 수 있어 MEEL 소자의 특성을 향상시킬 수 있다. Accordingly, the present invention forms a first nitride film by nitriding the exposed side of the floating gate after forming a floating gate on a silicon substrate, and forming a second nitride film by an in-situ process on the entire surface of the substrate resultant, thereby trapping tunneling electrons. The function can be improved and the characteristics of the MEEL element can be improved.
이상, 본 발명을 몇 가지 예를 들어 설명하였으나, 본 발명은 이에 한정되는 것은 아니며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자라면 본 발명의 사상에서 벗어나지 않으면서 많은 수정과 변형을 가할 수 있음을 이해할 것이다.In the above, the present invention has been described with reference to some examples, but the present invention is not limited thereto, and a person of ordinary skill in the art may make many modifications and variations without departing from the spirit of the present invention. I will understand.
이상에서와 같이, 본 발명은 실리콘 기판 상에 플로팅 게이트를 형성한 후에 기판 결과물을 NO 분위기에서 어닐링하여 노출된 플로팅 게이트의 측면에 제1질화막을 형성하고, 기판 결과물 전면 상에 인-시튜 공정으로 제2질화막을 형성함으로써 FN 터널링 전자 트래핑 기능을 향상시킬 수 있으며, 동시에 트래핑된 전자의 유지 능력을 향상시킬 수 있어 MEEL 소자의 특성을 효과적으로 향상시킬 수 있다.As described above, according to the present invention, after forming a floating gate on a silicon substrate, the substrate resultant is annealed in a NO atmosphere to form a first nitride film on the exposed side of the floating gate, and in-situ on the substrate resultant front surface. By forming the second nitride film, the FN tunneling electron trapping function can be improved, and at the same time, the holding ability of the trapped electrons can be improved, thereby effectively improving the characteristics of the MEEL device.
도 1a 내지 도 1f는 종래의 MEEL 소자의 제조방법을 설명하기 위한 공정별 단면도. 1A to 1F are cross-sectional views for each process for explaining a method of manufacturing a conventional MEEL device.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 MEEL 소자의 제조방법을 설명하기 위한 공정별 단면도.2A to 2E are cross-sectional views for each process for explaining a method of manufacturing a MEEL device according to an exemplary embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
21 : 실리콘 기판 23 : 터널링 산화막21 silicon substrate 23 tunneling oxide film
25 : 플로팅 게이트용 폴리 실리콘막 27 : 하드마스크용 산화막25 polysilicon film for floating gate 27: oxide film for hard mask
28 : 플로팅 게이트 31 : 제1 질화막28: floating gate 31: first nitride film
33 : 제2 질화막 35 : 산화막33: second nitride film 35: oxide film
37 : 컨트롤 게이트37: control gate
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030066191A KR101006512B1 (en) | 2003-09-24 | 2003-09-24 | Method for manufacturing meel device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030066191A KR101006512B1 (en) | 2003-09-24 | 2003-09-24 | Method for manufacturing meel device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20050029917A true KR20050029917A (en) | 2005-03-29 |
| KR101006512B1 KR101006512B1 (en) | 2011-01-07 |
Family
ID=37386415
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020030066191A KR101006512B1 (en) | 2003-09-24 | 2003-09-24 | Method for manufacturing meel device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR101006512B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101064281B1 (en) * | 2005-05-23 | 2011-09-14 | 매그나칩 반도체 유한회사 | Method for manufacturing semiconductor memory device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3240999B2 (en) | 1998-08-04 | 2001-12-25 | 日本電気株式会社 | Semiconductor memory device and method of manufacturing the same |
| KR20010059234A (en) * | 1999-12-30 | 2001-07-06 | 박종섭 | Method For Forming The Flash Memory |
| KR100611079B1 (en) * | 2001-02-02 | 2006-08-09 | 삼성전자주식회사 | Method of forming gate spacer in non-volatile memory device |
-
2003
- 2003-09-24 KR KR1020030066191A patent/KR101006512B1/en active IP Right Grant
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101064281B1 (en) * | 2005-05-23 | 2011-09-14 | 매그나칩 반도체 유한회사 | Method for manufacturing semiconductor memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR101006512B1 (en) | 2011-01-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20030057432A1 (en) | Ultrathin high-k gate dielectric with favorable interface properties for improved semiconductor device performance | |
| KR20050009190A (en) | Semiconductor device and method for manufacturing semiconductor device | |
| JP2006032948A (en) | Method of forming composite dielectric film and method of manufacturing semiconductor device using said composite dielectric film | |
| KR20060100092A (en) | Method for manufacturing a semiconductor device | |
| KR20060003402A (en) | Method for fabricating semiconductor device by using radical oxidation | |
| KR100490301B1 (en) | Method of manufacturing a flash memory cell | |
| KR100543209B1 (en) | Method for fabrication of transistor having sonos structure | |
| KR101006512B1 (en) | Method for manufacturing meel device | |
| KR100907931B1 (en) | Radical oxide film formation method and dual gate oxide film formation method using the same | |
| KR100596775B1 (en) | Method of manufacturing semiconductor device | |
| KR20040068952A (en) | Fabrication of non-volatile memory cell | |
| KR20050064233A (en) | Non-volatile memory device of sonos structure and method for fabrication of the same | |
| KR100675897B1 (en) | Method for forming transistor of semiconductor device | |
| KR100997781B1 (en) | Method of manufacturing EEPROM device | |
| KR100650799B1 (en) | Method of manufacturing in flash memory device | |
| US7262098B2 (en) | Manufacturing process of a semiconductor non-volatile memory cell | |
| KR100881736B1 (en) | Method of manufacturing semiconductor device | |
| KR20070058725A (en) | Method of manufacturing non-volatile memory device | |
| KR100554985B1 (en) | Non-volatile memory device of sonos structure and method for fabrication of the same | |
| KR20050060267A (en) | Method for fabrication of triple gate having sonos structure | |
| JPH09205155A (en) | Manufacture of semiconductor storage device | |
| JPH11176959A (en) | Manufacture of semiconductor device | |
| KR100919244B1 (en) | Method for fabrication of the non-volatile memory device with reliable tunnel oxide | |
| KR100672126B1 (en) | Method of forming a gate in semiconductor device | |
| KR20060029383A (en) | Method of manufacturing in non volatile memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| N231 | Notification of change of applicant | ||
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20131118 Year of fee payment: 4 |
|
| FPAY | Annual fee payment |
Payment date: 20141119 Year of fee payment: 5 |
|
| FPAY | Annual fee payment |
Payment date: 20151118 Year of fee payment: 6 |
|
| FPAY | Annual fee payment |
Payment date: 20161118 Year of fee payment: 7 |
|
| FPAY | Annual fee payment |
Payment date: 20171117 Year of fee payment: 8 |
|
| FPAY | Annual fee payment |
Payment date: 20181120 Year of fee payment: 9 |
|
| FPAY | Annual fee payment |
Payment date: 20191119 Year of fee payment: 10 |