KR20050028934A - Mcm packaged with a chip for memory test and for driving plasma display panel - Google Patents

Abstract

An MCM(Multi-Chip Module) embedded with a memory test and PDP driving chip is provided to reduce test time and cost of a memory installed in the MCM. An MCM(Multi-Chip Module) has a plurality of memories storing an image signal while driving PDP, and also has a memory test and a PDP driving chip testing the memories and driving PDP. According to the memory test and the PDP driving chip, a memory test device(130) and a PDP driving device are formed in a body. According to the memory test device, an address generation part(131) generates an address to write and read data and then outputs the address to write and read data to/from a memory(110). A test pattern generation part(132) outputs a test pattern to the memory. A verify pattern generation part(133) generates an equal verify pattern to the test pattern generation part. A comparison part(134) compares the test pattern with the verify pattern of the verify pattern generation part. And a control part(135) controls the address generation part and the test pattern generation part and the verify pattern generation part.

Description

Multi-chip module packaged with memory test and PD drive chip {MCM packaged with a chip for memory test and for driving plasma display panel}

The present invention relates to a memory test and a multi-chip module (hereinafter, referred to as 'MCP') in which a plasma display panel (PDP) driving chip is packaged. For example, by implementing a multi-chip module (MCM) by embedding a memory test device, a built-in self test (BIST) device, in a PDP driving chip, the test time and cost of the memory installed in the MCM can be reduced. The present invention relates to a multichip module in which a memory test and a PDP driving chip are packaged.

In general, a PDP is a display device in which visible light is generated from a phosphor when ultraviolet rays generated by gas discharge excite the phosphor.

Such a PDP is thinner and lighter than the Cathode Ray Tube (CRT), which has been the mainstay of the display means, and has the advantage of enabling high definition / large screen.

In addition, PDP has the advantages of being easy to fabricate by a simple structure, high brightness and high luminous efficiency, a memory function, a wide viewing angle of 160 ° or more, and a large screen of 40 inches or more.

The PDP obtains a discharge through voltage control applied between vertical and horizontal electrodes of a cell constituting a pixel, and the amount of light discharged is controlled by changing the length of the discharge time in the cell.

That is, the PDP includes a write pulse for inputting a digital image signal to the vertical and horizontal electrodes of each cell, a scan pulse for scanning, a sustain pulse for maintaining a discharge, and a discharged cell. By applying an erase pulse for stopping the discharge of the battery, the erase pulse is driven in a matrix form.

Here, the step brightness required for image display, that is, gray scale, implements different lengths of time for discharging individual cells within a time when a screen of one frame is displayed (16.67 ms in case of an NTSC TV signal). I express it.

Contrast, which represents the difference in contrast, is determined by the brightness and brightness of a background, such as a lamp. In order to increase this contrast, not only the background needs to be darkened, but also the brightness needs to be increased.

Such PDPs are generally classified into AC and DC types according to driving methods.

On the other hand, PDP uses a PDP controller ASIC (Application Specific IC) and several SDRAMs (Synchronous Dynamic Random Access Memory) on the controller board. The PDP controller ASICs and SDRAMs are already packaged and tested by the manufacturer. The product was supplied and used in a completed state, and the product was reliable to some extent.

However, PDPs are manufactured in the form of MCM (Multi-Chip Module) in which PDP controller ASICs and SDRAMs are received in wafer form from a manufacturer and integrated into one package in order to reduce the slimness of the PDP module and the cost of the controller board. I use it.

1 is a diagram illustrating an MCM in which a PDP and a PDP driving chip are packaged according to the prior art. The MCM 100 includes driving chips for driving the PDP 10 to receive a video signal from an external source and to generate a sustain signal. (11a, 11b), scan signals 12a, 12b and data signals 13a, 13b are generated and output to the PDP 10, the image is displayed on the PDP 10. FIG.

At this time, the ASIC chip for driving the PDP used in the MCM 100 extracts a good sample through EDS (Electric Die Sorting), and mostly has good characteristics, but the SDRAM is in an unpackaged wafer state. Because of the supply, there are many difficulties in testing wafers and also many times and costs for testing.

In order to solve the above problems, the present invention implements a multi-chip module (MCM) by embedding a memory test device, which is a built-in self test (BIST) device, in a PDP driving chip. Accordingly, an object of the present invention is to provide a multichip module packaged with a memory test and PDP driving chip that can reduce the test time and the cost of the memory mounted in the MCM.

According to a preferred aspect of the present invention, a memory test and a PDP driving chip capable of testing a memory and driving a PDP are packaged therein.

According to an embodiment of the present invention, a memory test and a PDP driving chip are packaged, and a memory test and a PDP driving chip are packaged.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 2 is a block diagram illustrating an MCM in which a memory test and a PDP driving chip are packaged according to the present invention. The memory test and the PDP driving chip 120 capable of testing a memory in the MCM 100 and driving a PDP are shown in FIG. and; First to eighth memories 111, 112, 113, 114, 115, 116, 117, and 118 which are tested by the memory test and the PDP driving chip 120 and store image signals when driving the PDP are packaged.

3 is a block diagram illustrating a memory test apparatus according to the present invention, in which the memory test apparatus 130 generates an address for writing and reading data, and outputs an address for writing and reading data to the memory 110. 131; A test pattern generator 132 generating a test pattern and outputting a test pattern to the memory 110; A verification pattern generator 133 which generates the same verification pattern as the test pattern generator 132; A comparison unit (134) for comparing the test pattern stored in the memory (110) and outputted with the verification pattern of the verification pattern generator (133); The control unit 135 controls the address generator 131, the test pattern generator 132, and the verification pattern generator 133.

The memory test apparatus configured as described above generates an address for reading and writing data in the address generator 131 to give the memory 110 an address for reading and writing data, and the test pattern generator 132 patterns the data. A test pattern is generated and stored in the memory 110.

The verification pattern generator 133 generates a verification pattern identical to the test pattern generated by the test pattern generator 132, and compares the verification pattern with a test pattern stored in the memory 110 and output. By comparing and outputting at 134, the characteristics of the memory 110 can be tested.

Here, it is preferable that the memory uses an SDRAM memory.

In addition, the control unit 135 is preferably designed as a finite state machine (FSM).

The test pattern may be any one of a solid pattern, a checkerboard pattern, a checkerboard bar pattern, a stripe pattern, a stripe bar pattern, and a march pattern. .

Referring to the above-described test pattern in detail, first, the solid pattern is only a pattern of '0' or '1', and the checkerboard pattern is a bit line direction first row (Row) as shown in FIG. 0,1,0,1, ... ', the second row is' 1,0,1,0, ...' and the third row is again '0,1,0,1, ...' The data to be written to the neighboring address with " 1 " and " 0 " are alternately formed.

The checkerboard bar pattern is opposite to the checkerboard pattern, for example, a pattern in which the first row Row in the bit line direction is '1,0,1,0, ...'.

In addition, in the stripe pattern, the first row is '1,1,1,1, ....', the second row is '0,0,0,0, ...', and the third row is '1'. , 1,1,1, ... 'pattern, and the stripe bar pattern is opposite to the stripe pattern.

Finally, the pattern may be divided into a pattern 1 (PAT (00,01)) and a pattern 2 (PAT (11,10)), and the pattern 1 may be ↑ (w0); ↑ (r0, w1, r1); ↑ (r1, w0, r1); ↓ (r0, w1, r1); ↓ (r1, w0, r0); ↓ (r0).

Here, '↑' is performed in ascending order to addresses in a matrix form arranged in rows and columns, and '↓' is performed in descending order.

That is, as if pattern 1 performs ↑ (w0) which writes '0' from the last address of the last row to the first address of the first row, and then performs ↑ (r0, w1, r1). Bar, read '0' sequentially from the last row to the first row, write '1', and read '1'.

Then, '1' is read in ascending order, '0' is written, and '↑ (r1, w0, r1)' is read to read '1'.

After that, '↓ (r0, w1, r1); ↓ (r1, w0, r0); ↓ (r0)' is performed in descending order.

On the contrary, it is pattern 2 to give and perform data.

Meanwhile, in the present invention, like the memory test and the PDP driving chip shown in FIG. 2, the memory test and the PDP driving device may be integrally implemented on a single chip, and the memory test chip and the PDP driving chip may be manufactured as separate chips. It can also be implemented.

FIG. 5 is an operation diagram of reading and writing a test pattern into a memory to test the memory according to the present invention. The memory is tested in the following order.

1.POWER-UP SEQUENCE: Waiting for stabilization after power is applied to memory

2. ALL_ZERO / ALL_ONE: Write and read solid patterns '0' and '1' into memory

3. Checkerboard / Checkerboard bar: Write and read checkerboard / checkerboard bar patterns into memory

4. Stripe / Stripe bar: Write and read stripe / stripe bar patterns into memory

5. March: as if writing and reading patterns in memory

As described above, the present invention implements MCM by embedding a memory test device, which is a built-in self test (BIST) device, in a PDP driving chip, thereby reducing test time and cost of a memory mounted in the MCM. There is an advantage.

As described above, the present invention implements MCM by embedding a memory test device, which is a built-in self test (BIST) means, in a PDP driving chip, thereby reducing test time and cost of a memory mounted in the MCM. That effect occurs.

In addition, by applying the MCM that can reduce the size of the PDP controller board, there is an effect that can reduce the reliability and cost of the PDP product.

Although the invention has been described in detail only with respect to specific examples, it will be apparent to those skilled in the art that various modifications and variations are possible within the spirit of the invention, and such modifications and variations belong to the appended claims.

1 is a diagram illustrating an MCM in which a PDP and a PDP driving chip according to the related art are packaged.

2 is a block diagram illustrating an MCM in which a memory test and a PDP driving chip are packaged according to the present invention.

3 is a block diagram of a memory test apparatus according to the present invention;

4 shows a checkerboard pattern in accordance with the present invention.

5 is an operation diagram of reading and writing a test pattern to a memory for testing a memory according to the present invention.

<Description of the symbols for the main parts of the drawings>

100: MCM

110, 111, 112, 113, 114, 115, 116, 117, 118: memory

120: memory test and PDP driving chip 130: memory test device

131: address generator 132: test pattern generator

133: verification pattern generation unit 134: comparison unit

135: control unit

Claims (3)

A plurality of memories are packaged therein for storing a video signal when driving a PDP; And a memory test capable of testing the memories and driving the PDP, and a memory test and PDP driving chip packaged with the PDP driving chip. The method of claim 1, The memory test and PDP driving chip, PDP driver and memory test device are integrally formed, The memory test apparatus includes an address generator for generating an address for writing and reading data, and outputting an address for writing and reading data to the memory; A test pattern generator for generating a test pattern and outputting a test pattern to the memory; A verification pattern generator which generates the same verification pattern as the test pattern generator; A comparison unit comparing the verification pattern stored in the memory and outputted with the verification pattern of the verification pattern generator; And a control unit for controlling the address generator, the test pattern generator, and the verification pattern generator. The method of claim 2, The test pattern is, A memory comprising any one of a solid pattern, a checkerboard pattern, a checkerboard bar pattern, a stripe pattern, a stripe bar pattern, and a march pattern Multichip module packaged with test and PD drive chips.