KR20050016960A - Tft electronic devices and their manufacture - Google Patents

Abstract

The electronic device 70 including the TFTs 9 and 59 according to the invention comprises a channel 16 defined in a layer of polycrystalline semiconductor material 10 and 48. The polycrystalline semiconductor material is produced by crystallizing the amorphous semiconductor material 2, 44 using the metal atoms 6 to facilitate the crystallization process. The average concentration range of the metal atoms of the polycrystalline semiconductor material 10 is 1.3 × 10 ¹⁸ to 7.5 × 10 ¹⁸ atoms / cm ³ . This allows the polycrystalline semiconductor TFT to be formed with a leakage characteristic suitable for use in an active matrix display using a metal induced crystallization process of considerably smaller duration than expected. In addition, the reduction in the process duration facilitates the reliable manufacture of poly-Si TFTs with bottom gates formed of metal.

Description

Electronic device and manufacturing method thereof, active matrix display device {TFT ELECTRONIC DEVICES AND THEIR MANUFACTURE}

FIELD OF THE INVENTION The present invention relates to electronic devices comprising polycrystalline semiconductor materials and methods of making such materials and devices.

Due to the higher carrier mobility of polycrystalline silicon (polysilicon or poly-Si) compared to amorphous silicon (a-Si), polycrystalline silicon is an active matrix liquid crystal display (AMLCD), an active matrix polymer LED display (AMPLED), solar cells and images. It is an attractive material for use in large area electronic devices such as sensors. An example of a flat active matrix display is disclosed in US-A-5130829, the contents of which are incorporated herein by reference.

For illustrative purposes, the term "amorphous" refers to a material in which constituent atoms are randomly located. The term "polycrystal" relates to a material comprising a plurality of single crystals, the single crystal having a lattice structure which regularly repeats constituent atoms. This is particularly relevant for poly-Si formed by melting and cooling amorphous silicon. Typical grain sizes of poly-Si are 0.1 μm to 5 μm. However, if crystallized under certain conditions, the silicon can have a microscopic grain size, typically 0 to 0.5 μm. The term "microcrystalline" relates to a crystalline material having a microscopic grain size.

Conventionally, for example, poly-Si films used in thin film transistors (TFTs) have been produced by solid phase crystallisation (SPC). This includes depositing an a-Si film on an insulating substrate and exposing the a-Si film to high temperature for a long time, ie, exposing it to a temperature of 600 ° C. or higher for a period of time up to 24 hours.

Alternatively, US-A-5147826 discloses a low temperature method for crystallizing a-Si films. The method includes depositing a thin film of metal atoms (eg nickel) on an a-Si film and annealing the thin film. This metal induces crystal growth at temperatures up to 600 ° C. and also provides faster crystal growth than otherwise. For example, a typical annealing using US-A-5147826 method can be done at about 550 ° C. for 10 hours. This represents an improvement over the conventional method for at least the following two reasons. First, this allows low cost, low temperature, non-alkali glass substrates such as borosilicate, which typically undergo glass compaction and warping at temperatures above 600 ° C., to be used. Secondly, the annealing period is reduced, the manufacturing yield rate is increased, and thus the associated manufacturing cost may be reduced. The contents of US-A-5147826 are incorporated herein by reference. The use of a metal such as nickel in this manner is hereinafter referred to as metal induced crystallisation or "MIC" and the resulting poly-Si material is referred to as "MIC poly-Si".

More recently, the production of poly-Si using laser annealing processes has been developed and widely commercialized. However, since the narrow laser beam is progressively scanned across the substrate irradiating each part of the surface with several shots, this process is relatively slow, and the non-uniformity of the laser shots causes the non-uniformity in the poly-Si. Uniformity is derived and laser devices are expensive to implement and maintain. The annealing step in the process of US-A-5147826 can be performed as a relatively simple batch process in the furnace, resulting in high yield.

TFTs fabricated using the technique of US-A-5147826 had the problem of relatively high leakage current in the "off" state, which makes them unsuitable for use in applications such as AMLCDs. This disadvantage makes the image retention by the AMLCD inappropriate.

Typically, in conventional poly-Si AMLCDs, the value of the minimum leakage current (i.e., the minimum value of leakage current over the normal operating range of the gate voltage) of the TFT to be accepted is about 10 pA or less at a source-drain voltage of 5V. In other words, if the TFT off current exceeds this value during normal operation of the display, it is not desirable that the TFT off current exceeds this value during normal operation of the display, since current leakage will drop unacceptably. . This threshold may vary somewhat depending on the characteristics of the pixel associated with the TFT. In a TFT having a channel width of 4 μm, a leakage current of 10 A is 2.5 × 10 ⁻¹² A / μm. (A / μm in the context of the TFT herein means amperes per μm of the channel width of the TFT).

Sooyoung Yoon et al., “A High-Performance Polycrystalline Silicon Thin-Film Transistor Using Metal-Induced Crystallsation with Ni Solution”, Jpn. J. Appl. Phys. Vol. 37 (1998) pp7193-7197 discloses further refinements of the technique of US-A-5147826. The 100 nm thick a-Si film on the substrate is crystallized by immersion in Ni absorption solution at 500 ° C. for 20 hours. The Ni concentration in the resulting poly-Si is 1.2 x 10 ¹⁸ atoms / cm ³ . The off-state leakage current of a TFT with a channel of poly-Si formed using this process was found to be 2.7 × 10 ⁻¹¹ A / μm at a drain voltage of 5V, which is larger than the threshold mentioned above.

1 illustrates a metal implantation step of a process in accordance with one embodiment of the present invention.

FIG. 2 shows the relationship between nickel concentration and depth in semiconductor films in different doping processes. FIG.

3 is a cross-sectional view of a top gate poly-Si TFT formed using a process embodying the present invention.

4 through 7 illustrate cross-sectional views of successive stages of bottom gate TFT fabrication in accordance with an addition process embodying the present invention.

8 is a perspective view of an active matrix display.

It is an object of the present invention to form an electronic device comprising a polycrystalline semiconductor material in a more cost effective manner.

In an electronic device comprising a TFT, the TFT comprises a channel defined in a layer of polycrystalline semiconductor material produced by crystallizing the amorphous semiconductor material using metal atoms to facilitate the crystallization process, wherein the metal of the semiconductor material The average concentration range of atoms provides an electronic device with 1.3 × 10 ¹⁸ to 7.5 × 10 ¹⁸ atoms / cm ³ . Using this metal concentration, it was possible to form a TFT with improved leakage current characteristics. In particular, a TFT having this characteristic may be suitable for use as a switching element in an AMLCD without a leakage current in the TFT off state which degrades the performance of the display to an unacceptable degree.

The inventors have found that, by using metal atoms in the above-described concentration ranges, polycrystalline semiconductor TFTs having the leakage characteristics defined above can be formed by an annealing process of a much smaller duration than expected. While the desired properties can be achieved with an annealing time of 20 hours at a temperature of about 550 ° C., the metal concentrations disclosed herein reduce this time to 10 hours, 8 hours or even 6 hours or less at temperatures below 600 ° C. You can. Thus, the actual productivity and efficiency in the manufacturing process increases.

Preferably, the average concentration of metal atoms in the polycrystalline semiconductor material is at least 1.9 × 10 ¹⁸ atoms / cm ³ and / or at most 5 × 10 ¹⁸ atoms / cm ³ . More preferably, the average concentration of metal atoms in the polycrystalline semiconductor material is in the range of 2 to 3 x 10 ¹⁸ atoms / cm ³ .

In a preferred embodiment, the average concentration of metal atoms is about 2.5 × 10 ¹⁸ atoms / cm ³ .

Preferably, the TFT is a low-doped drain (LDD) structure. This may increase the range of gate voltages at which the minimum leakage current is substantially achieved.

The present invention also provides a method of manufacturing an electronic device, comprising the steps of (a) depositing an amorphous semiconductor material on a substrate, and (b) an average concentration of 1.3x10 ¹⁸ to 4x10 ¹⁸ atoms / cm ^{3 in the} semiconductor material. Adding a phosphorous metal atom, wherein the metal atom is suitable for accelerating crystallization of an amorphous semiconductor material; and (c) annealing the amorphous semiconductor material to form a polycrystalline semiconductor material. do.

It has also been found that the application of an electric field to the substrate during the annealing step may accelerate this process and reduce the duration.

Various metal atoms may be used in the process of the present invention. One or more elements selected from the group consisting of Ni, Cr, Co, Pd, Pt, Cu, Ag, Au, In, Sn, Pb, As, Sb may be used. More preferably, at least one element from Ni, Co and Pd groups is used.

Reference herein to the addition of metal atoms includes metal in the form of a compound or element containing atoms of the metal.

Ion implantation is used to inject amorphous semiconductor materials containing metals in the process of the present invention because it allows precise control over the dose, uniformity and ion depth. However, other methods may be used for this purpose. For example, metal atoms may be applied to the amorphous semiconductor material in a solution, typically by a spin coating process. Other processes include the use of nickel precursors during sputtering or sol-gel coating of nickel layers and CVD processes of amorphous semiconductor materials.

As mentioned above, the process of forming MIC poly-Si disclosed herein may greatly reduce the duration of the annealing step of such a process. The inventors have also found that a reduction in the thermal capacity of this step may be sufficient to allow the use of MIC poly-Si in the bottom gate TFT structure. Examples of known bottom gate TFT structures are back channel etch (BCE) TFTs and etch stop TFTs. In particular, according to the present invention, the gate electrode of the bottom gate poly-Si TFT structure may be formed of a metal. Previously, even if facilitated by the addition of suitable metal atoms, the use of thermal annealing was sufficient to form polycrystalline silicon, or diffusion of the gate metal through the gate electrode by forming poly-Si using a laser annealing process This occurs to short the lower gate with poly-Si.

The ability to reliably form bottom gate poly-Si TFTs (especially in applications with low temperature substrates) is a significant commercial value that allows the mask count of the manufacturing process to be reduced for conventional top gate poly-Si TFT manufacturing processes. Has In addition, this process is compatible with existing a-Si fabrication lines—many of which currently produce bottom gate TFT structures—reducing the cost of line changes to produce poly-Si TFTs. In addition, laser annealing may not be required to produce acceptable quality poly-Si, thereby reducing the associated costs.

Suitable materials for forming the gate electrode in the bottom gate TFT according to the present invention are low-resistances such as Au, Ag or Ni, which may be more suitable for refractory materials such as Cr, W, MoCr or larger displays where gate resistance reduction is important. Metal. Depending on other parameters and thermal capacities of a given process and device application, different gate materials may be selected.

For example, metal silicide material may be used to form the gate. Suitable materials for forming silicides include tungsten, molybdenum, nickel and platinum. A separate annealing step may be performed to react the selected material with a-Si to form the corresponding silicide. Alternatively, the annealing step performed during the formation of the MIC poly-Si of the TFT may simultaneously form silicide. As mentioned above, the relatively low thermal capacity of this annealing has the advantage of minimizing the risk of metal diffusion into the gate dielectric.

Other materials that may be used to form the gate electrode include doped hydrogenated a-Si, or microcrystalline silicon. Bottom gate poly-Si TFTs with gate electrodes comprising these materials are disclosed in British Patent Application No. 0210065.9, the contents of which are incorporated herein by reference. In addition, metal atoms suitable for promoting the crystallization of silicon may be included in a-Si or microcrystalline silicon, thus improving the crystallinity of the gate material during the MIC annealing step. Thus, the gate electrode may comprise a semiconductor material and a metal atom suitable for promoting its crystallization.

In a preferred embodiment of the electronic device manufacturing method disclosed herein, the TFT is formed with a defined channel in a polycrystalline semiconductor material having a bottom gate structure, which method includes a BCE step. Compared with the fabrication of the bottom gate BCE a-Si TFT, the BCE step has a more clearly defined end point according to this embodiment. Removal of n + a-Si in the BCE process exposes poly-Si (rather than intrinsic a-Si), and thus a-Si and poly-Si to ensure that the etching process ends when the exposed n + a-Si is etched. An optional etchant may be selected between.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

The drawings are schematically depicted and are not drawn to scale. The relative sizes and ratios of the parts in the drawings are enlarged or reduced in size for clarity and convenience in the drawings.

The process of implementing the present invention is described with reference to FIG. 1 shows an a-Si (2) layer deposited on a glass substrate 4. The layer is typically 40 nm thick and was formed using, for example, plasma enhanced chemical vapor deposition (PECVD).

An area density of nickel of about 1 × 10 ¹³ atoms / cm ² is then injected into the a-Si layer with an implantation energy of typically 20 keV (this step is indicated by arrow 6 in FIG. 1). Energy up to 30 keV has been successfully used for this thickness layer to produce a TFT with the desired leakage characteristics. Thus, the average concentration of nickel atoms in the 40 nm thick a-Si layer due to this dose is about 2.5 x 10 ¹⁸ atoms / cm ³ .

The dose profile of typical nickel in the a-Si layer is shown schematically in FIG. 2 for several processes. The depth into the layer increases along the x axis, with 0 representing the top surface of the layer. Line 8 represents the profile achieved using the implantation process and line 10 represents the profile for the spin coating or sputtering process. As a result of the injection, a peak of the profile occurs in the body of the layer, with other processes the highest concentration occurring at the top of the layer. As the concentration of nickel increases toward the center of the body of the semiconductor material, it is believed that this may lead to the formation of a better quality crystalline material compared to other doping techniques. Using injection facilitates precise control of the nickel dose. The semiconductor material is preferably crystallized by annealing in an atmosphere of N ₂ at 550 ° C. for about 8 hours.

Photolithography, implantation, deposition and etching process steps are then performed in a known manner to form a poly-Si TFT structure as shown in FIG. The structure shown as an example in FIG. 3 is a top-gate, gate-overlapped, lightly doped drain TFT. The semiconductor material is patterned into poly-Si islands 10 and includes doped source and drain regions 12 and 14, with intrinsic channel regions 16 and weakly doped regions 18 and 20 therebetween. Insulating material layer 22 is deposited over island 10 and has vias 24 and 26 defined therein, which are defined by source and drain terminals 30 and 32, respectively. 14). A metal gate electrode 28 is provided over the insulating material layer 22.

The MIC process disclosed herein allows bottom gate TFTs to be reliably fabricated on low temperature substrates. Examples of processes for forming such devices according to the present invention are described below with reference to FIGS. 4 to 7. The completed TFT device shown in Fig. 7 is a BCE TFT. This process requires only five mask steps less than conventional poly-Si TFT processes and is therefore relatively cost effective. The use of each mask is shown in the process description under parentheses. Photolithography, implantation, deposition, and etching process steps suitable for forming a device are well known in the art and will not be described in detail.

First, as shown in FIG. 4, for example, a bottom gate 40 of Cr is provided on a glass substrate (mask 1). The gate material is chosen to withstand the thermal capacity and other processing of subsequent MIC anneals. The relatively low thermal capacity of the MIC process disclosed herein enables the use of materials such as Cr.

Next, as shown in FIG. 5, a gate insulating layer 42 and a-Si layer 44 are deposited on the gate 40. As described with respect to FIG. 1, Ni is added to the a-Si layer 44 by, for example, implantation, and the substrate is then annealed at 550 ° C. for 8 hours, in order to convert a-Si to MiC poly-Si. To.

An n + doped a-Si layer is deposited over the MIC poly-Si and the two layers are patterned to form a device island 46 (FIG. 6) comprising the MIC poly-Si island 48 and the top n + a-Si. (Mask 2). In order to provide good electrical contact between the two layers, it may be necessary to clean the MIC poly-Si surface prior to the deposition of n + a-Si. For example, a thin silicon dioxide layer may be formed on the MIC poly-Si. Hydrofluoric acid treatment may be a suitable method for removing such oxide layers.

A metal layer is then deposited, which is patterned to form source and drain electrodes 50 and 52 (mask 3). Using the source and drain electrodes 50, 52 as the mask defining etch window 58, a BCE step is now performed to remove the n + a-Si material between them, expose the underlying MIC poly-Si, and Si source and drain contact layers 54 and 56 are defined.

In the known a-Si BCE TFT manufacturing process, the end point of the etching BCE step cannot be clearly defined or controlled because the etching process is not selective between n + a-Si and lower a-Si. This problem was solved by forming the a-Si layer thicker and removing some a-Si to ensure that unnecessary n + a-Si was removed. This has the disadvantage of increasing processing time and cost and making the process less reliable to reproduce. However, in the process of FIG. 4 sol 7, the MIC poly-Si material is exposed by etching n + a-Si, and the etchant used in the BCE step can be selectively selected between n + a-Si and poly-Si, Provide a clearly defined end point for the etching step.

Thus, the present process makes it possible to form BCE TFTs having relatively thin poly-Si regions that accept channels rather than relatively thick a-Si layers. This reduced layer thickness reduces the processing time required to deposit the layer and also serves to reduce leakage in the layer. For example, the channel receiving the a-Si layer of a BCE a-Si TFT is typically about 100 nm thick, while the poly-Si layer of the device may be thicker than this, which layer is about 40 or even 20 nm thick. Phosphorus devices may be reliably manufactured.

Then, as shown in FIG. 7, a passivation layer 60 is deposited thereon, opening a contact hole 62 in the passivation layer 60 (mask 4), and a suitable material (usually indium tin oxide) is applied. By depositing and patterning to form the pixel electrode 64, the TFT device is completed (e.g. for an active matrix display device).

In another method described in connection with FIGS. 5 and 6, an n + Si layer may be deposited over the a-Si layer 44 before the MIC process is performed. Then n + a-Si is patterned to define the source and contact layers 54, 56, with the channel region of a-Si exposed therebetween. Metal atoms for the promotion of crystallization of a-Si are added by one of the methods disclosed herein, for example implantation, and MIC annealing is performed. In this method, not only the channel region of the TFT but also the source and drain contact layers of the n + a-Si layer are crystallized, thus improving the conductivity of the source and drain contact layers.

In an active matrix display device, an array of TFTs is provided on an active plate for switching each pixel of the display. As shown in FIG. 8, in the liquid crystal display device 68, an active plate 70 and an opposing passive plate 72 and a liquid crystal material 74 therebetween are provided.

It is particularly preferred in the process according to the invention to carry out the plasma hydrogenation process after device manufacture to improve its performance. Typically this is done at about 350 ° C. for about 1 hour.

TFTs formed according to the process described herein having a channel width of 50 μm have an off state of about 8 × 10 ⁻¹¹ A and about 20 cm ² at a source-drain voltage of 5V equivalent to 1.6 × 10 ⁻¹² A / μm. It was found to represent the leakage current of the mobility of / Vs.

TFT leakage characteristics may be further improved by employing a fingered channel structure with two, three or more fingers.

In the embodiment described above with reference to FIGS. 4-7, metal is used to form the gate electrode. However, other materials may be used in accordance with the present invention to form the gate electrode.

In another preferred embodiment, the gate electrode comprises metal silicide. Various methods may be used to form such gate electrodes. For example, an a-Si layer may be deposited and patterned in a preferred configuration for the gate electrode. Next, a layer of suitable material is deposited and an annealing step of appropriate temperature and duration is performed to react with the metal having a-Si to form metal silicide. For example, in the case of NiSi ₂ , annealing may be performed at 350 ° C. for about 1 hour. The metal material that has not reacted with a-Si is then stripped away leaving the gate electrode comprising the metal silicide material. Suitable materials include tungsten, molybdenum, nickel and platinum. Other metals may be used, assuming that the corresponding silicides formed are able to withstand subsequent processing, in particular the MIC annealing step.

The thickness of the a-Si layer may be between about 20 and 100 nm, and the metal forming the silicide may have an extra thickness (or more, to provide a desired stochiometric ratio of atoms reacting with a-Si). Metal may be removed).

In a variation of the metal silicide gate electrode formation process above, a metal layer may be deposited on the unpatterned layer of a-Si. In this case, silicide annealing is performed before patterning to form a gate electrode.

In another variation, the annealing step performed to form the MIC poly-Si of the TFT may simultaneously form silicides without requiring a separate annealing step to form the silicides. In this method, an a-Si layer and a silicide forming metal layer may be deposited and patterned together to define the gate electrode configuration. They are not annealed to form silicides until the later MIC annealing step of device fabrication.

Although embodiments of the present invention have been described with reference to silicon materials (ie, a-Si and poly-Si), according to the present invention other semiconductor materials, or synthetic semiconductor films (eg, silicon films comprising germanium) may be used. It is obvious that it may be used.

Polycrystalline semiconductors produced in accordance with the techniques disclosed herein are suitable for use in a wide range of applications in which electronic circuits are formed on substrates that cannot withstand high temperatures such as glass. The film may be used to form active devices such as TFTs or passive devices (e.g., resistors, temperature sensors, and piezo-resistors) in circuits on such substrates. TFTs may be employed in AMLCDs, AMPLEDs, X-ray sensors, fingerprint detectors, and the like as switching matrixes of integrated circuits and / or devices on the same structure as the switching matrix.

The crystal quality of the polycrystalline semiconductor material formed using the process described herein may be further improved by irradiating the material with an energy beam. As mentioned above, it may take considerable time to scan the energy beam across the substrate. However, as disclosed in pending applicant's UK Patent Application No. 0211724.0 (reference PHGB020072), the time taken for this can be determined by simply examining the peripheral circuitry integrated on the display substrate around the display area. It may be minimized in manufacturing. The content of British Patent No. 0211724.0 is incorporated herein by reference.

From this specification, other variations and modifications will be apparent to those skilled in the art. Such variations and modifications may include equivalent other features as are already known in the art, and may be used instead of or in addition to the features disclosed herein.

While the claims have been formulated with specific combinations of features in the present application, the scope of the invention is any or all equivalents to what is done in the present invention and whether or not it relates to the same invention as the one currently claimed in the claims. Note that it includes any novel feature or novel combination of explicitly or implicitly disclosed features or any generalization, whether or not to mitigate technical problems.

Note that in the course of this application or further applications derived therefrom, new claims may be formulated with such features and / or combinations of such features.

Claims (14)

In the electronic device 70 including the TFTs 9 and 59, The TFT comprises a channel 16 defined in a layer of polycrystalline semiconductor material 10, 48 produced by crystallizing the amorphous semiconductor material 2, 44 using metal atoms 6 to facilitate the crystallization process. , The average concentration range of the metal atoms of the semiconductor material is 1.3 × 10 ¹⁸ to 7.5 × 10 ¹⁸ atoms / cm ³ Electronic device. The method of claim 1, The average concentration of metal atoms in the semiconductor material is about 2.5 × 10 ¹⁸ atoms / cm ³ Electronic device. The method according to claim 1 or 2, The TFT 59 has a bottom gate configuration Electronic device. The method of claim 3, wherein The gate electrode 40 of the TFT 59 includes a metal material Electronic device. The method according to any one of claims 1 to 4, The gate electrode 40 of the TFT 59 includes a metal silicide Electronic device. The method according to any one of claims 1 to 5. The gate electrode 40 comprises a metal atom and a semiconductor material suitable for promoting the crystallization Electronic device. In the electronic device manufacturing method, (a) depositing an amorphous semiconductor material (2, 44) on the substrate (4), (b) adding a metal atom 6 having a mean concentration in the range of 1.3 × 10 ¹⁸ to 4 × 10 ¹⁸ atoms / cm ³ to the semiconductor material, the metal atoms being suitable for accelerating crystallization of an amorphous semiconductor material - Wow, (c) annealing the amorphous semiconductor material to form a polycrystalline semiconductor material. Electronic device manufacturing method. The method of claim 7, wherein The metal atoms 6 are added to the amorphous semiconductor material at an average concentration of about 2.5 × 10 ¹⁸ atoms / cm ³ Electronic device manufacturing method. The method according to claim 7 or 8, The metal atom 6 is added by implantation Electronic device manufacturing method. The method according to any one of claims 7 to 9, The annealing process is performed for 10 hours or less at a temperature of 600 ° C. or less, and has a TFT having a defined channel in the polycrystalline semiconductor material exhibiting a minimum leakage current of about 2.5 × 10 ⁻¹² A / μm at a source-drain voltage of 5V ( 9, 59) are formed Electronic device manufacturing method. The method of claim 10, The annealing process is performed for up to 8 hours at a temperature of 550 ° C. or less, and has a TFT having a defined channel in the polycrystalline semiconductor material exhibiting a minimum leakage current of about 2.5 × 10 ⁻¹² A / μm at a source-drain voltage of 5V 9, 59) are formed Electronic device manufacturing method. The method according to any one of claims 7 to 11, A TFT 59 having a defined channel in the polycrystalline semiconductor material having a bottom gate configuration is formed, and the method includes a back channel etching step. Electronic device manufacturing method. The electronic device according to any one of claims 1 to 6 or the method according to any one of claims 7 to 12, wherein the metal atom (6) comprises a nickel atom. In the active matrix display device 68, An active matrix display device according to any of the preceding claims, wherein the electronic device (70) forms an active plate of the active matrix device.