KR20050014419A - A method for forming a transistor of a semiconductor device - Google Patents

A method for forming a transistor of a semiconductor device

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Publication number
KR20050014419A
KR20050014419A KR1020030053053A KR20030053053A KR20050014419A KR 20050014419 A KR20050014419 A KR 20050014419A KR 1020030053053 A KR1020030053053 A KR 1020030053053A KR 20030053053 A KR20030053053 A KR 20030053053A KR 20050014419 A KR20050014419 A KR 20050014419A
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region
atoms
semiconductor substrate
rta
nmos
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KR1020030053053A
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Korean (ko)
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유경동
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주식회사 하이닉스반도체
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Priority to KR1020030053053A priority Critical patent/KR20050014419A/en
Publication of KR20050014419A publication Critical patent/KR20050014419A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

PURPOSE: A method for forming a transistor of a semiconductor device is provided to improve a punch-through phenomenon and enable high integration by increasing a threshold voltage of a high-integrated semiconductor device. CONSTITUTION: Low density impurities are implanted into a NMOS(n-channel metal oxide semiconductor) region and a PMOS(p-channel metal oxide semiconductor) region on a semiconductor substrate having a gate electrode. An insulation layer spacer is formed on the sidewall of the gate electrode. High density N-type impurities are implanted into the semiconductor substrate in the NMOS region. The first RTA(rapid thermal annealing) process is performed. High density P-type impurities are implanted into the semiconductor substrate in the PMOS region. The second RTA process is performed to form a source/drain junction region in the NMOS and PMOS regions, respectively.

Description

반도체소자의 트랜지스터 형성 방법{A method for forming a transistor of a semiconductor device}A method for forming a transistor of a semiconductor device

본 발명은 반도체 소자의 트랜지스터 형성 방법에 관한 것으로, 특히 CMOS 집적회로, 바이폴라 집적회로 그리고 상기 CMOS 집적회로와 바이폴라 집적회로가 혼합된 BICMOS 집적회로의 숏채널마진 ( short channel margin )을 개선할 수 있도록 하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a transistor of a semiconductor device, and more particularly, to improve short channel margin of a CMOS integrated circuit, a bipolar integrated circuit, and a BICMOS integrated circuit in which the CMOS integrated circuit and the bipolar integrated circuit are mixed. It is about technology to do.

일반적으로, 반도체소자의 집적회로를 구성하는 기본요소인 접합의 깊이 변화없이 주입된 불순물만을 활성화시켜 트랜지스터의 구성요소인 불순물과 실리콘기판의 접합깊이를 얕게 형성하기 위하여, RTA ( rapid thermal annealing ) 공정을 사용한다.In general, a rapid thermal annealing (RTA) process is performed in order to shallowly form a junction depth between an impurity of a transistor and a silicon substrate by activating only the impurity implanted without changing the depth of a junction, which is a basic element of an integrated circuit of a semiconductor device. Use

그러나, 반도체소자의 고집적화에 따라 최근에는 150 ㎚ 이하의 길이를 갖는 트랜지스터의 접합 깊이를 100 ㎚ 이하로 한정하고 있다.However, with the high integration of semiconductor devices, recently, the junction depth of transistors having a length of 150 nm or less has been limited to 100 nm or less.

그러나, 트랜지스터의 길이가 작아질수록 요구되는 깊이가 낮아지는데 비하여, 상기 접합깊이를 낮추는 공정은 용이하지 않다.However, the smaller the length of the transistor, the lower the required depth, whereas the process of lowering the junction depth is not easy.

이로 인하여, 상기 트랜지스터의 게이트전극과 관계없이 소오스/드레인 접합영역 사이에 전류가 흐르는 펀치 쓰루우 ( punch through ) 가 유발되어 소자의 전기적 특성을 열화시키고 그에 따른 반도체소자의 특성 및 신뢰성이 저하되는 문제점이 있다.This causes a punch through through which current flows between the source / drain junction regions irrespective of the gate electrode of the transistor, resulting in deterioration of the electrical characteristics of the device and deterioration of the characteristics and reliability of the semiconductor device. There is this.

본 발명은 이러한 종래기술의 문제점을 해결하기 위하여, RTA 공정을 이용하여 CMOS 의 NMOS 와 PMOS 모두의 숏채널마진을 개선할 수 있도록 하는 반도체소자의 트랜지스터 형성방법을 제공하는데 그 목적이 있다.In order to solve the problems of the prior art, an object of the present invention is to provide a method for forming a transistor of a semiconductor device that can improve the short channel margin of both CMOS NMOS and PMOS using the RTA process.

도 1 및 도 2 는 CMOS 트랜지스터의 게이트전극 길이에 따른 문턱전압 변화를 도시한 그래프.1 and 2 are graphs showing a change in threshold voltage according to the gate electrode length of a CMOS transistor.

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 트랜지스터 형성방법은,In order to achieve the above object, a method of forming a transistor of a semiconductor device according to the present invention,

게이트전극이 형성된 반도체기판 상의 NMOS 영역 및 PMOS 영역에 저농도의 불순물을 임플란트하여 엘.디.디. ( lightly doped drain, LDD ) 접합영역을 형성하는 공정과,Low concentration impurities are implanted in the NMOS region and PMOS region on the semiconductor substrate on which the gate electrode is formed. (lightly doped drain, LDD) process of forming a junction region,

상기 게이트전극의 측벽에 절연막 스페이서를 형성하는 공정과,Forming an insulating film spacer on sidewalls of the gate electrode;

상기 NMOS 영역의 반도체기판에 고농도의 N형 불순물을 임플란트하는 공정과,Implanting a high concentration of N-type impurities into the semiconductor substrate in the NMOS region;

연속적으로 제1 RTA 처리하는 공정과,Continuously treating the first RTA,

상기 PMOS 영역의 반도체기판에 고농도의 P형 불순물을 임플란트하는 공정과,Implanting a high concentration of P-type impurities into the semiconductor substrate in the PMOS region;

연속적으로 제2 RTA 처리하여 NMOS 영역과 PMOS 영역에 각각 소오스/드레인 접합영역을 형성하는 공정을 포함하는 것과,Successively performing a second RTA process to form a source / drain junction region in each of the NMOS region and the PMOS region;

상기 엘.디.디. 접합영역은 1E12 원자/㎠ ∼ 1E15 원자/㎠ 만큼 저농도의 불순물을 임플란트하여 형성하는 것과,L.D.D. The junction region is formed by implanting impurities of low concentration by 1E12 atoms / cm 2 to 1E15 atoms / cm 2,

상기 제1 RTA 처리 공정은 800 ∼ 1100 ℃ 의 온도에서 실시하는 것과,The first RTA treatment step is carried out at a temperature of 800 to 1100 ℃,

상기 소오스/드레인 접합영역은 1E15 원자/㎠ ∼ 7E15 원자/㎠ 만큼 고농도의 불순물을 임플란트하여 형성하는 것과,The source / drain junction region is formed by implanting impurities having a high concentration of 1E15 atoms / cm 2 to 7E15 atoms / cm 2,

상기 제2 RTA 처리 공정은 800 ∼ 1100 ℃ 온도에서 상기 제1 RTA 공정보다 20 ∼ 100 ℃ 만큼 낮은 온도로 실시하는 것을 특징으로 한다.The second RTA treatment step is carried out at a temperature lower by 20 to 100 ° C. than the first RTA step at a temperature of 800 to 1100 ° C.

도시되지 않았으나, 본 발명을 상세히 설명하면 다음과 같다.Although not shown, the present invention will be described in detail as follows.

먼저, 반도체기판 상에 활성영역을 정의하는 소자분리막을 형성한다.First, an isolation layer defining an active region is formed on a semiconductor substrate.

상기 활성영역의 반도체기판에 트랜지스터의 펀치 쓰루우 특성을 방지할 수 있는 P형 및 N형 불순물을 주입한다.P-type and N-type impurities are implanted into the semiconductor substrate in the active region to prevent the punch-through characteristics of the transistor.

이때, 상기 P형 불순물은 NMOS 영역에 주입하고, 상기 N형 불순물은 PMOS 영역에 주입한다.In this case, the P-type impurity is implanted into the NMOS region, and the N-type impurity is implanted into the PMOS region.

그 다음, 상기 반도체기판 상부에 게이트산화막, 게이트전극용 도전층 및 하드마스크층의 적층구조를 형성한다.Next, a stacked structure of a gate oxide film, a gate electrode conductive layer, and a hard mask layer is formed on the semiconductor substrate.

게이트전극 마스크를 이용한 사진식각공정으로 상기 적층구조를 식각하여 상기 PMOS 영역과 NMOS 영역에 게이트전극을 각각 형성한다.The stacked structure is etched by a photolithography process using a gate electrode mask to form gate electrodes in the PMOS region and the NMOS region, respectively.

전체표면상부에 상기 PMOS 영역만을 노출시키는 제1감광막패턴을 형성한다.A first photoresist pattern is formed over the entire surface to expose only the PMOS region.

상기 제1감광막패턴 및 게이트전극을 마스크로 하여 상기 PMOS 영역의 반도체기판에 P형 불순물을 임플란트하여 LDD 접합영역을 형성한다. 이때, 상기 P형 불순물의 임플란트 공정은 1E12 원자/㎠ ∼ 1E15 원자/㎠ 불순물 농도로 실시하여 1E16 원자/㎤ ∼ 1E22 원자/㎤ 의 농도 구간을 형성할 수 있도록 한다.An LDD junction region is formed by implanting P-type impurities into the semiconductor substrate of the PMOS region using the first photoresist pattern and the gate electrode as masks. In this case, the implantation process of the P-type impurity may be performed at a concentration of 1E12 atoms / cm 2 to 1E15 atoms / cm 2 impurity to form a concentration section of 1E16 atoms / cm 3 to 1E22 atoms / cm 3.

상기 제1감광막패턴을 제거하고, 상기 NMOS 영역만을 노출시키는 제2감광막패턴을 형성한다.The first photoresist layer pattern is removed, and a second photoresist layer pattern exposing only the NMOS region is formed.

상기 제2감광막패턴 및 게이트전극을 마스크로 하여 상기 NMOS 영역의 반도체기판에 N형 불순물을 임플란트하여 LDD 접합영역을 형성한다. 이때, 상기 N형 불순물의 임플란트 공정은 1E12 원자/㎠ ∼ 1E15 원자/㎠ 불순물 농도로 실시하여 1E16 원자/㎤ ∼ 1E22 원자/㎤ 의 농도 구간을 형성할 수 있도록 한다.An LD type junction region is formed by implanting an N-type impurity into the semiconductor substrate of the NMOS region using the second photoresist pattern and the gate electrode as masks. At this time, the implantation process of the N-type impurity is carried out at a concentration of 1E12 atoms / cm 2 to 1E15 atoms / cm 2 impurity to form a concentration section of 1E16 atoms / cm 3 to 1E22 atoms / cm 3.

상기 제2감광막패턴을 제거하고 상기 게이트전극의 측벽에 절연막 스페이서를 형성한다.The second photoresist layer pattern is removed, and an insulating layer spacer is formed on sidewalls of the gate electrode.

이때, 상기 절연막 스페이서는 전체표면상부에 산화막, 질화막 및 이들의 적층구조를 증착하고 증착된 두께만큼 이방성 식각하여 형성한 것이다.In this case, the insulating film spacer is formed by depositing an oxide film, a nitride film and a stacked structure thereof on the entire surface and anisotropically etching by the deposited thickness.

그 다음, 상기 LDD 접합영역을 형성하는 공정과 같이 NMOS 영역의 반도체기판에 고농도의 N형 불순물을 임플란트하여 소오스/드레인 불순물 접합영역을 형성한다. 이때, 상기 고농도의 N형 불순물 임플란트 공정은 1E15 원자/㎠ ∼ 7E15 원자/㎠ 불순물 농도로 실시하여 1E21 원자/㎤ ∼ 4E22 원자/㎤ 의 농도 구간을 형성할 수 있도록 한다.Next, as in the step of forming the LDD junction region, a source / drain impurity junction region is formed by implanting a high concentration of N-type impurities on the semiconductor substrate of the NMOS region. At this time, the high concentration of the N-type impurity implant process is carried out with a concentration of 1E15 atoms / cm 2 ~ 7E15 atoms / cm 2 impurity to form a concentration range of 1E21 atoms / cm 3 to 4E22 atoms / cm 3.

연속적으로, 상기 임플란트된 N형 불순물을 활성화시키기 위하여 제1 RTA 공정을 실시한다.Subsequently, a first RTA process is performed to activate the implanted N-type impurity.

이때, 상기 제1 RTA 공정은 800 ∼ 1100 ℃ 온도로 실시한다.At this time, the first RTA step is carried out at a temperature of 800 ~ 1100 ℃.

그 다음, 상기 PMOS 영역의 반도체기판에 고농도의 P형 불순물을 임플란트하여 소오스/드레인 불순물 접합영역을 형성한다. 이때, 상기 고농도의 P형 불순물 임플란트 공정은 1E15 원자/㎠ ∼ 7E15 원자/㎠ 불순물 농도로 실시하여 1E21 원자/㎤ ∼ 4E22 원자/㎤ 의 농도 구간을 형성할 수 있도록 한다.Then, a source / drain impurity junction region is formed by implanting a high concentration of P-type impurities into the semiconductor substrate of the PMOS region. At this time, the high concentration P-type impurity implant process is carried out with a concentration of 1E15 atoms / cm 2 ~ 7E15 atoms / cm 2 impurity to form a concentration range of 1E21 atoms / cm 3 to 4E22 atoms / cm 3.

연속적으로, 상기 임플란트된 P형 불순물을 활성화시키기 위하여 제2 RTA 공정을 실시한다. 이때, 상기 제2 RTA 공정은 800 ∼ 1100 ℃ 온도에서 실시하되, 상기 제1 RTA 공정보다 20 ∼ 100 ℃ 만큼 낮은 온도에서 실시한다.Subsequently, a second RTA process is performed to activate the implanted P-type impurity. At this time, the second RTA process is carried out at a temperature of 800 ~ 1100 ℃, but at a temperature lower by 20 ~ 100 ℃ than the first RTA process.

여기서, 상기 제2 RTA 공정은 일반적인 열처리 공정으로 대신할 수도 있다.Here, the second RTA process may be replaced by a general heat treatment process.

도 1 및 도 2 는 각각 NMOS 와 PMOS 에서 게이트전극 길이에 따른 문턱전압 변화를 도시한 그래프로서, 종래기술에 비하여 문턱전압 높이가 높아짐을 알 수 있다.1 and 2 are graphs illustrating changes in threshold voltages according to gate electrode lengths in NMOS and PMOS, respectively, and it can be seen that the threshold voltage height is higher than that in the prior art.

상기 문턱전압의 증가로 인하여 펀치 쓰루우 특성이 향상됨을 알 수 있다.It can be seen that the punch through characteristic is improved due to the increase in the threshold voltage.

이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자의 트랜지스터 형성방법은, 고집적화된 반도체소자의 문턱전압을 증가시켜 소자의 펀치 쓰루우 특성을 개선함으로써 반도체소자의 고집적화를 가능하게 하는 효과를 제공한다.As described above, the method for forming a transistor of a semiconductor device according to the present invention provides an effect of enabling high integration of a semiconductor device by increasing the threshold voltage of the highly integrated semiconductor device to improve punch through characteristics of the device.

Claims (5)

게이트전극이 형성된 반도체기판 상의 NMOS 영역 및 PMOS 영역에 저농도의 불순물을 임플란트하여 엘.디.디. 접합영역을 형성하는 공정과,Low concentration impurities are implanted in the NMOS region and PMOS region on the semiconductor substrate on which the gate electrode is formed. Forming a junction region, 상기 게이트전극의 측벽에 절연막 스페이서를 형성하는 공정과,Forming an insulating film spacer on sidewalls of the gate electrode; 상기 NMOS 영역의 반도체기판에 고농도의 N형 불순물을 임플란트하는 공정과,Implanting a high concentration of N-type impurities into the semiconductor substrate in the NMOS region; 연속적으로 제1 RTA 처리하는 공정과,Continuously treating the first RTA, 상기 PMOS 영역의 반도체기판에 고농도의 P형 불순물을 임플란트하는 공정과,Implanting a high concentration of P-type impurities into the semiconductor substrate in the PMOS region; 연속적으로 제2 RTA 처리하여 NMOS 영역과 PMOS 영역에 각각 소오스/드레인 접합영역을 형성하는 공정을 포함하는 반도체소자의 트랜지스터 형성방법.And forming a source / drain junction region in each of the NMOS region and the PMOS region by successive second RTA treatment. 제 1 항에 있어서,The method of claim 1, 상기 엘.디.디. 접합영역은 1E12 원자/㎠ ∼ 1E15 원자/㎠ 만큼 저농도의 불순물을 임플란트하여 형성하는 것을 특징으로 하는 반도체소자의 트랜지스터 형성방법.L.D.D. The junction region is formed by implanting impurities of low concentration by 1E12 atoms / cm 2 to 1E15 atoms / cm 2. 제 1 항에 있어서,The method of claim 1, 상기 제1 RTA 처리 공정은 800 ∼ 1100 ℃ 의 온도에서 실시하는 것을 특징으로 하는 반도체소자의 트랜지스터 형성방법.The first RTA treatment step is performed at a temperature of 800 to 1100 ° C. The transistor formation method of a semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 소오스/드레인 접합영역은 1E15 원자/㎠ ∼ 7E15 원자/㎠ 만큼 고농도의 불순물을 임플란트하여 형성하는 것을 특징으로 하는 반도체소자의 트랜지스터 형성방법.The source / drain junction region is formed by implanting impurities having a high concentration of 1E15 atoms / cm 2 to 7E15 atoms / cm 2. 제 1 항에 있어서,The method of claim 1, 상기 제2 RTA 처리 공정은 800 ∼ 1100 ℃ 온도에서 상기 제1 RTA 공정보다 20 ∼ 100 ℃ 만큼 낮은 온도로 실시하는 것을 특징으로 하는 반도체소자의 트랜지스터 형성방법.And the second RTA treatment step is performed at a temperature of 800 to 1100 ° C. at a temperature lower by 20 to 100 ° C. than the first RTA step.
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