KR20050014137A - Method for detecting error concerning of test power connection for testing semiconductor device - Google Patents

Abstract

PURPOSE: A method for detecting a connection failure of a test power source at a semiconductor device is provided to conveniently detect a failure that test power is connected to a chip on a chip improperly due to a wrong test standard or a failure that is caused by a wrong design of a test board. CONSTITUTION: A semiconductor device having cores operated at different operation voltages and at least one pad for each of the cores is tested by using test voltages applied thereto. A predetermined test voltage is applied to at least one pad which supplies the operation voltage to one core selected from the cores. Whether a test voltage is detected from the at least one pad supplying voltages to the rest cores is determined.

Description

Method for detecting error concerning of test power connection for testing semiconductor device}

The present invention relates to a test method of a semiconductor device, and more particularly, in the case of incorrectly connecting a test voltage for testing a semiconductor device using a plurality of different power sources due to an error of a test standard and a design error of a test board. The present invention relates to a method for detecting a power connection error generated.

As the SOC (system on chip) is integrated, the SOC becomes more complicated and the types of power supplies used for the SOC also vary. Therefore, it takes a lot of time to manufacture a test board for testing an SOC having various power supplies and to write a program for testing the SOC. In addition, the time for testing the SOC is also getting longer.

When an error occurs in a test standard written by the designer of the SOC or when a test board for testing the SOC is manufactured incorrectly, the failure analysis of the SOC becomes more difficult, and thus the time for the failure analysis is also increased. Is increased.

Accordingly, the technical problem to be achieved by the present invention is to provide a method for easily detecting an error caused by a wrong test specification connecting an incorrect test power supply to an SOC, or an error caused by a design error of a test board.

The detailed description of each drawing is provided in order to provide a thorough understanding of the drawings cited in the detailed description of the invention.

1 is a diagram illustrating an example in which a test power source for testing a semiconductor device having two types of power sources is connected incorrectly.

FIG. 2 is a diagram illustrating an example in which a test power source for testing a semiconductor device having three types of power sources is incorrectly connected.

3 is a flowchart illustrating a method of detecting an error in connection information of a test power source for testing a semiconductor device according to an exemplary embodiment of the present invention.

A method of detecting a connection error of a test voltage for testing a semiconductor device having cores using different operating voltages and at least one pad connected to each of the cores for achieving the technical problem may include the cores. Applying a predetermined test voltage to at least one pad supplying operating power to one selected core from among the selected cores, and determining whether the test voltage is detected from at least one pad supplying power to each of the remaining cores It is equipped with a step.

The first pad for supplying the first operating voltage to the first core using the first operating voltage for achieving the technical problem and the second supplying voltage to the second core using the second operating voltage A method of detecting a connection error of a test voltage for testing a semiconductor device having two pads includes applying the test voltage to the first pad; And determining whether the test voltage is detected at the second pad.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 is a diagram illustrating an example in which a test power source for testing a semiconductor device having two types of power sources is connected incorrectly. Referring to FIG. 1, the semiconductor device 100 includes a 1.8V core 101, a 3.3V core 103, a CDL 105, and a plurality of PADs 1 to 14.

The 1.8V core 101 has predetermined circuits that use 1.8 volts as an operating power supply, and the 3.3V core 103 includes predetermined circuits that use 3.3 volts as an operating power supply. The common discharge line (CDL) 105 connected between the 1.8V core 101 and the 3.3V core 103 is a bidirectional diode that operates only at a voltage of about 2000 volts or more.

Each of the plurality of PADs 1-14 represents a pin of a pad or package for an electro static discharge (ESD). Here, each of the plurality of PADs 1 to 5 is a power supply pin of the 1.8V core 101, and each of the plurality of PADs 6 to 14 is a power supply pin of the 3.3V core 103.

When the designer of the semiconductor device 100 prepares a test specification, pins 1, 4, and 7 are designated as power pins of the 1.8V core 101, and pins 8, 11, and 14 are 3.3V cores. Assume that the power pins of 103 are determined.

When the semiconductor device 100 is tested, the first power supply terminal 110 of the test device (not shown) is connected to pins 1, 4, and 7 and the second power supply terminal 120 of the test device is It is connected to pins 8, 11 and 14.

Therefore, since the test apparatus does not determine that pin 7 is erroneously connected, the test apparatus determines that the semiconductor device 100 is defective.

In addition, due to a design error of the test board for testing the semiconductor device 100, the first power supply terminal 110 of the test device is connected to pins 1, 4, and 7 and the second power supply of the test device. When the terminal 120 is connected to pins 8, 11, and 14, the test apparatus does not determine that pin 7 is incorrectly connected, and thus the test apparatus determines that the semiconductor device 100 is defective. do.

FIG. 2 is a diagram illustrating an example in which a test power source for testing a semiconductor device having three types of power sources is incorrectly connected.

Referring to FIG. 2, the semiconductor device 200 may include a 1.2V core 201, a 1.8V core 203, a 3.3V core 205, a plurality of CDLs 202, 204, and 206 and a plurality of PADs ( 1 to 14). src1 to src3 are the channels (or power supply terminals) of the test apparatus.

The 1.2V core 201 has predetermined circuits for operating voltage of 1.2 volts, the 1.8V core 203 has predetermined circuits for operating voltage of 1.8 volts, and the 3.3V core 205 has 3.3. Certain circuits using a volt as an operating power source are provided.

The CDL 202 is connected between the 1.2V core 201 and the 1.8V core 203, the CDL 204 is connected between the 1.8V core 203 and the 3.3V core 205, and the CDL 206 is connected. Is connected between the 3.3V core 205 and the 1.2V core 201.

Each of the plurality of PADs 1-14 represents a pin of a pad or package for ESD. Here, each of the plurality of PADs 5 to 7 is a power supply pin of a 1.2V core 201, each of the plurality of PADs 1 to 4 is a power supply pin of a 1.8V core 203, and a plurality of PADs ( Each is a power supply pin of the 3.3V core 103.

3 is a flowchart illustrating a method of detecting an error in connection information of a test power source for testing a semiconductor device according to an exemplary embodiment of the present invention.

It is assumed that power is incorrectly connected to pin 5 due to an error of a test standard and / or a design error of a test board, and an error of power connection information for testing a semiconductor device according to the present invention is described with reference to FIGS. 2 and 3. The detection method is as follows.

The first channel src1 of the test device (not shown) is connected to each of the pads 1, 4, and 5 of the semiconductor device 200, and the second channel src2 is connected to each pad 8 of the semiconductor device 200. , 11 and 14, and the third channel src3 is connected to the pad 6 of the semiconductor device 200.

In operation 310, the test apparatus determines how many channels 210, 220, and 230 are connected to the semiconductor device 200.

If the test device is assumed to be a device for supplying different voltages to the semiconductor device 200 using at most N (where N is a natural number and N is 4) channels, the test device is a predetermined test program. Through this, it is determined that the number of channels connected to the semiconductor device 200 is three. Therefore, the test apparatus determines that the fourth channel src [4] is not connected to the semiconductor device 200 (step 311).

Since the first channel Src [1] 210 of the test device is not null, the test device performs step 320.

In operation 320, the test device inputs a test voltage Vsrc [1] to the first channel src1. Hereinafter, the test voltage Vsrc [1] is 2V, the maximum input allowable current isrc input to the first channel 210 is 200 kHz, and the maximum output allowed from each of the other channels 220 and 230 is allowed. Assume that the current is 200 mA.

In operation 330, the test apparatus measures the voltage output from each channel 220 or 230. If the voltage Vsrc [2] output from the second channel src2 220 is smaller than the reference voltage Vdet, the power information and the second channel of at least one pad connected to the first channel 210 may be used. Power information on at least one pad connected to 220 may be determined to be accurate. The reference voltage Vdet is preferably set lower than the test voltage.

As shown in FIG. 2, when the test standard for the pad 5 is incorrect or the design of the test board for the pad 5 is incorrect, the pad 5 is connected to the first channel 210. The voltage Vsrc [3] output from the src3 230 is greater than the reference voltage Vdet.

In this case, since the test device generates an error message (step 360), the tester performs a test specification for at least one of the pads 1, 4, and 5 connected to the first channel 210. Or you can provisionally determine that the design of the test board is incorrect. Therefore, the person performing the test task may stop the test (step 370).

After applying the test voltage Vsrc [1] to the first channel 210, the voltage Vsrc [2] or Vsrc [3] output from the second channel 220 and the third channel 230, respectively, is referenced. If the voltage Vdet is smaller than all of them (step 330), the test apparatus applies the test voltage Vsrc [2] to the second channel 220 and then the first channel 210 and the third channel 230, respectively. It is determined whether the voltages Vsrc [1] and Vsrc [3] output from the both are smaller than the reference voltage Vdet, and any one of steps 340 and 360 is performed according to the determination result.

In addition, the test apparatus applies the test voltage Vsrc [3] to the third channel 230, and then outputs the voltages Vsrc [1] and Vsrc output from the first and second channels 210 and 220, respectively. In operation 330, it is determined whether the reference voltage Vdet is smaller than the reference voltage Vdet.

As a result of the determination in step 330, since the voltage Vsrc [1] output from the first channel 210 is greater than the reference voltage, the test apparatus generates an error message (step 360).

Therefore, the person performing the test task may determine that a test specification for at least one of the pads 1, 4, and 5 connected to the first channel 230 or the design of the test board is incorrect.

That is, when the test voltage is applied to the first channel 210, the voltage Vsrc [3] output from the third channel 230 is greater than the reference voltage Vdet, and the test voltage is applied to the third channel 230. When applied, since the voltage Vsrc [1] output from the first channel 210 is greater than the reference voltage Vdet, at least one of the pads 1, 4, and 5 connected to the first channel 230. You can finally determine that the test specification for either pad or the design of the test board is incorrect.

However, when the test voltage is applied to the first channel 210, the voltage Vsrc [3] output from the third channel 230 is greater than the reference voltage Vdet, and the test voltage is applied to the third channel 230. In one case, when the voltage Vsrc [1] output from the first channel 210 is smaller than the reference voltage Vdet, there is a problem in the CDL connected between the 1.2V core 201 and the 1.8V core 203. You can judge.

When the test voltage is applied to any one of the plurality of channels and the voltages output from the remaining channels are all smaller than the reference voltage, the test apparatus or the person performing the test task may proceed to the next test (350). .

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the method of detecting an error in power connection information for testing a semiconductor device according to the present invention has an effect of detecting a product defect caused by a test power source connected incorrectly by a wrong test standard in a short time. .

In addition, the method of detecting an error in power connection information of a semiconductor device according to the present invention has an effect of detecting a product defect caused by an incorrect test board design in a short time.

In addition, the method of detecting an error in power connection information of a semiconductor device according to the present invention has an effect of detecting an error of a test standard by only one test.

The method of detecting an error in power connection information of a semiconductor device according to the present invention has an effect of detecting a design error of a test board by only one test.

Claims (5)

A method of detecting a connection error of a test voltage for testing a semiconductor device having cores using different operating voltages and at least one pad connected to each of the cores, the method comprising: Applying a predetermined test voltage to at least one pad for supplying operating power to one of the cores selected from among the cores; And Determining whether the test voltage is detected from at least one pad supplying power to each of the remaining cores. A semiconductor device comprising a first pad supplying the first operating voltage to a first core using a first operating voltage and a second pad supplying the second operating voltage to a second core using a second operating voltage. In the method for detecting a connection error of the test voltage for testing the, Applying the test voltage to the first pad; And And determining whether the test voltage is detected in the second pad. A first pad supplying the first operating voltage to a first core using a first operating voltage, a second pad supplying the second operating voltage to a second core using a second operating voltage, and a third operation A method for detecting a connection error of a test voltage for testing a semiconductor device having a third pad for supplying the third operating voltage to a third core using a voltage, the method comprising: Applying the test voltage to the first pad; And And determining whether or not the test voltage is detected at the second pad and the third pad. The method of claim 3, wherein the connection error detection method of the test voltage comprises: Applying the test voltage to the second pad; And And determining whether the test voltage is detected at the first pad and the third. The method of claim 3, wherein the connection error detection method of the test voltage comprises: Applying the test voltage to the third pad; And And determining whether the test voltage is detected at the first pad and the second.