KR20050012472A - Method of Driving Plasma Display Panel - Google Patents

Abstract

PURPOSE: A method of driving a plasma display panel is provided to control luminance and prevent a degradation of image by controlling a voltage value of a sustain pulse applied to a scan electrode and a sustain electrode. CONSTITUTION: A process for supplying a first sustain pulse is performed to supply the first sustain pulse to a scan electrode during a sustain period. A process for supplying a second sustain pulse is performed to supply the second sustain pulse to a sustain electrode during the sustain period. The second sustain pulse has a different voltage value from a voltage value of the first sustain pulse. The voltage value of the second sustain pulse is lower than the voltage value of the first sustain pulse. The voltage value of the second sustain pulse is higher than 120V.

Description

Driving Method of Plasma Display Panel {Method of Driving Plasma Display Panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a plasma display panel, and more particularly, to a method of driving a plasma display panel in which a natural luminance can be expressed by controlling a voltage of a sustain pulse.

Plasma Display Panel (hereinafter referred to as "PDP") is an ultraviolet light generated when an inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne, etc. discharges to display an image by emitting phosphors. do. Such PDPs are not only thin and large in size, but also have improved in image quality due to recent technology development.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP includes a scan electrode 30Y and a sustain electrode 30Z formed on the upper substrate 10, and an address electrode formed on the lower substrate 18. 20X).

Each of the scan electrode 30Y and the sustain electrode 30Z has a line width smaller than that of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z, and the metal bus electrodes 13Y, which are formed at one edge of the transparent electrode, respectively. 13Z). The transparent electrodes 12Y and 12Z are usually formed on the upper substrate 10 by indium tin oxide (ITO). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance.

The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan electrode 30Y and the sustain electrode 30Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used.

The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in the direction crossing the scan electrode 30Y and the sustain electrode 30Z. The partition wall 24 is formed in a straight or lattice shape to prevent the ultraviolet rays and the visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert mixed gas is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to implement grayscale of an image. Each subfield is divided into an initialization period for initializing the full screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gray levels according to the number of discharges. Here, the initialization period is divided into a setup period in which the rising ramp waveform is supplied and a set down period in which the falling lamp waveform is supplied.

For example, when the image is to be displayed with 256 gray levels, as shown in FIG. 2, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into an initialization period, an address period, and a sustain period. The initialization period and the address period of each subfield are the same for each subfield, while the sustain period is increased at a rate of 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. .

3 is a diagram showing a drive waveform of a PDP supplied during a subfield period.

In Fig. 3, Y represents a scan electrode and Z represents a sustain electrode. And X represents an address electrode.

Referring to FIG. 3, the PDP is driven by being divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initialization period, the rising ramp waveform Ramp-up is applied to all the scan electrodes Y simultaneously. This rising ramp waveform (Ramp-up) causes a slight discharge in the cells of the full screen to generate wall charges in the cells. During the set down period, the rising ramp waveform Ramp-up is supplied, and then the falling ramp waveform Ramp-down falling from the positive voltage Vs lower than the peak voltage of the rising ramp waveform Ramp-up is applied to the scan electrodes ( Is simultaneously applied to Y). Ramp-down generates weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by the setup discharges, and uniformly distributing wall charges required for address discharges in the full-screen cells. Will remain.

In the address period, a negative scan pulse scan is sequentially applied to the scan electrodes Y, and a positive data pulse data is applied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage of the wall charge generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse data is applied. Here, wall charges are generated in the discharge cells in which the address discharge is generated.

On the other hand, the positive electrode DC voltage of the sustain voltage level Vs is supplied to the sustain electrodes Z during the set down period and the address period.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. Then, the cell selected by the address discharge is sustained in the form of surface discharge between the scan electrode Y and the sustain electrode Z each time the sustain pulse sus is applied while the wall voltage and the sustain pulse sus in the cell are added. Discharge occurs. Here, the first sustain pulse 1st sus applied to the scan electrodes Y is set to have a wider width than the remaining sustain pulses su.

In detail, the sustain discharge generated by the first sustain pulse (1st sus) occurs in a state in which sufficient charged particles are not supplied. Therefore, the pulse width of the first sustain pulse (1st sus) is set to be wider, for example, approximately 3 ms or more so that the first sustain discharge occurs stably. Since the sustain discharge generated thereafter is sufficiently charged particles formed by the previous sustain discharge, stable generation occurs even if the pulse width of the remaining sustain pulses (sus) is set smaller than the width of the first sustain pulse (1st sus).

Finally, after the sustain discharge is completed, an erase lamp waveform (erase) having a small pulse width is supplied to the sustain electrode (Z) to erase wall charges in the cell.

In the conventional PDP driven as described above, gradation is implemented using the number of sustain pulses. That is, in the conventional PDP, a large number of sustain pulses (sus) are supplied to express a high gray level, and a small number of sustain pulses (sus) are supplied to represent a low gray level. However, expressing the gray scale using the number of the sustain pulses in this way makes it difficult to express the natural (smooth) luminance. In other words, since gray scales are implemented using only the number of the sustain pulses sus, it is difficult to realize fine changes in luminance. In particular, when expressing low gradations, it is necessary to implement minute changes in luminance using a small number of sustain pulses, which makes natural luminance more difficult. On the other hand, if the number of sustain pulses (sus) is excessively reduced in order to express low gradation, a problem of deterioration of image quality occurs.

Accordingly, it is an object of the present invention to provide a method of driving a plasma display panel which enables natural luminance expression by controlling the voltage of a sustain pulse.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

2 shows a frame of a general plasma display panel.

3 is a waveform diagram showing a driving method of a conventional plasma display panel.

4 is a waveform diagram showing a method of driving a plasma display panel according to an embodiment of the present invention;

5A to 5D are diagrams showing luminance generated in response to the voltage value of the sustain pulse.

6A and 6B are diagrams showing voltage values of sustain pulses that can be varied in low and high gradations.

7A and 7B are views showing luminance generated in the sustain period of the conventional plasma display panel and the plasma display panel of the present invention.

8A to 8D show a reset voltage margin when the present invention shown in FIG. 4 is applied.

9A to 9D show an address voltage margin when the present invention shown in FIG. 4 is applied.

10 is a view showing a method of driving a plasma display panel according to another embodiment of the present invention.

11 is a view showing a driving method of a plasma display panel according to another embodiment of the present invention;

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12Y, 12Z: transparent electrode

13Y, 13Z: bus electrode 14, 22: dielectric layer

16: protective film 18: lower substrate

20X: address electrode 24: partition wall

26: phosphor layer 30Y: scanning electrode

30Z: sustain electrode

In order to achieve the above object, a method of driving a plasma display panel according to the present invention includes supplying a first sustain pulse to a scan electrode during a sustain period, and maintaining a second sustain pulse having a different voltage value from the first sustain pulse during the sustain period. Supplying the electrode.

The voltage value of the second sustain pulse is set lower than the voltage value of the first sustain pulse.

The voltage value of the second sustain pulse is set higher than approximately 120V.

The voltage value of the second sustain pulse is set corresponding to the luminance value generated by the discharge between the scan electrode and the sustain electrode when the second sustain pulse is supplied.

Before the first and second sustain pulses are applied, a first sustain pulse having a wider pulse width than the first and second sustain pulses is supplied to the scan electrode.

The voltage value of the first sustain pulse is set lower than the voltage value of the second sustain pulse.

The voltage value of the first sustain pulse is set higher than approximately 120V.

The voltage value of the first sustain pulse is set corresponding to the luminance value generated by the discharge between the scan electrode and the sustain electrode when the first sustain pulse is supplied.

According to an exemplary embodiment of the present invention, a method of driving a plasma display panel includes supplying first and second sustain pulses to a scan electrode and a sustain electrode to generate light corresponding to luminance in a discharge cell, and any one of the first and second sustain pulses. Controlling the brightness by adjusting the voltage value of?.

In the step of controlling the luminance, the voltage value of any one of the first and second sustain pulses is set lower than the voltage value of the other pulse.

Before the first and second sustain pulses are applied, a first sustain pulse having a wider pulse width than the first and second sustain pulses is supplied to the scan electrode.

The pulse width of the first sustain pulse is set to 3 kHz or more.

According to the present invention, luminance is controlled by adjusting the voltage value of any one of the first and second sustain pulses supplied to the scan electrode and the sustain electrode in the sustain period of at least one subfield among the plurality of subfields.

The luminance is controlled by setting the voltage value of any one of the first and second sustain pulses lower than the voltage value of the other pulse.

Before the first and second sustain pulses are applied, a first sustain pulse having a wider pulse width than the first and second sustain pulses is supplied to the scan electrode.

Sustain pulses having the same voltage value are supplied in the sustain period of the remaining subfields except for the at least one subfield.

The present invention provides a method of supplying a first sustain pulse to a scan electrode during a sustain period, a second sustain pulse having a voltage value equal to that of the first sustain pulse to a sustain electrode during a sustain period, a scan electrode and a sustain electrode during a sustain period. And supplying a third sustain pulse having a voltage value different from the first sustain pulse to any one of the sustain electrodes.

The voltage value of the third sustain pulse is set lower than the voltage value of the first sustain pulse.

The voltage value of the third sustain pulse is set higher than approximately 120V.

The voltage value of the third sustain pulse is set corresponding to the luminance value generated by the discharge between the scan electrode and the sustain electrode when the third sustain pulse is supplied.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 11.

4 is a waveform diagram illustrating one subfield included in a frame according to an embodiment of the present invention.

In Fig. 4, Y represents a scan electrode and Z represents a sustain electrode. X represents an address electrode.

Referring to FIG. 4, the subfield of the present invention is driven by being divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initialization period, the rising ramp waveform Ramp-up is applied to all the scan electrodes Y simultaneously. This rising ramp waveform (Ramp-up) causes a weak discharge in the cells of the full screen to form wall charges in the cells. During the set down period, the rising ramp waveform Ramp-up is supplied, and then the falling ramp waveform Ramp-down falling from the positive voltage Vs lower than the peak voltage of the rising ramp waveform Ramp-up is applied to the scan electrodes ( Is simultaneously applied to Y). Ramp-down generates weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by the setup discharges, and uniformly distributing wall charges required for address discharges in the full-screen cells. Will remain.

In the address period, a negative scan pulse scan is sequentially applied to the scan electrodes Y, and a positive data pulse data is applied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage of the wall charge generated during the initialization period are added, an address discharge is generated in the cell to which the data pulse data is applied. Here, wall charges are generated in the discharge cells in which the address discharge is generated.

On the other hand, the positive electrode DC voltage of the sustain voltage level Vs is supplied to the sustain electrodes Z during the set down period and the address period.

In the sustain period, sustain pulses sus1 and sus2 are applied to the scan electrodes Y and the sustain electrodes Z alternately. Then, the cell selected by the address discharge is sustained in the form of surface discharge between the scan electrode Y and the sustain electrode Z each time the sustain pulse sus is applied while the wall voltage and the sustain pulse sus in the cell are added. Discharge occurs. Here, the pulse width of the first sustain pulse (1st sus) applied to the scan electrodes (Y) is set wider (approximately 3 ms or more) than the pulse widths of the remaining sustain pulses (sus1, sus2) so that a stable sustain discharge can occur. . The voltage value of the first sustain pulse 1st sus is set to the sustain voltage Vs as in the prior art.

Meanwhile, in the present invention, voltage values of the first sustain pulse sus1 applied to the scan electrodes Y and the second sustain pulse sus2 applied to the sustain electrodes Z are set differently. For example, in FIG. 4, the voltage value of the first sustain pulse sus1 is set to the sustain voltage Vs, and the voltage value of the second sustain pulse sus2 is set to the sustain voltage Vs or less. As such, when the voltage value of the second sustain pulse sus2 is set to the sustain voltage Vs or less, the amount of light generated by the sustain discharge (luminance) is lowered as compared with the prior art, thereby realizing a fine gradation luminance. Natural luminance can be expressed.

This will be described in detail with reference to FIGS. 5A to 5D.

In FIG. 5A, the pulse widths of the first and second sustain pulses sus1 and sus2 are set to a width narrower than the pulse width of the first sustain pulse 1st sus, for example, 2 ms. Then, the voltage values of the first and second sustain pulses sus1 and sus2 are set to a sustain voltage Vs, for example, 180 V, as in the prior art. (In fact, the sustain voltage Vs is determined by the panel's inch, resolution, etc.). If the voltage values of the first and second sustain pulses (sus1, sus2) are set to the sustain voltage (Vs), stable sustain discharge is generated in the cell and a large amount is generated by the discharge. It can be seen that light is generated.

In FIG. 5B, the pulse widths of the first and second sustain pulses sus1 and sus2 are set to a width narrower than the pulse width of the first sustain pulse 1st sus, for example, 2 ms. The voltage value of the first sustain pulse sus1 is set to be the same as the sustain voltage Vs, and the voltage value of the second sustain pulse sus2 is set to 150 V, which is lower than the sustain voltage Vs. As described above, even when the voltage value of the second sustain pulse sus2 is set lower than the sustain voltage Vs, stable discharge occurs in the discharge cell. When the voltage value of the second sustain pulse sus2 is lower than the sustain voltage Vs, the amount of light emitted by the sustain discharge (ie, luminance) decreases as compared with FIG. 5A.

In FIG. 5C, the pulse widths of the first and second sustain pulses sus1 and sus2 are set to a width smaller than the pulse width of the first sustain pulse 1st sus, for example, 2 ms. The voltage value of the first sustain pulse sus1 is set equal to the sustain voltage Vs, and the voltage value of the second sustain pulse sus2 is set to 125 V lower than the sustain voltage Vs. Here, even when the voltage value of the second sustain pulse sus2 is set to 125 V, stable discharge is generated in the discharge cell. In addition, when the voltage value of the second sustain pulse sus2 is lowered to 125V, it can be seen that the amount of light emitted by the sustain discharge (that is, the luminance) decreases as compared with FIG. 5B.

In FIG. 5D, the pulse widths of the first and second sustain pulses sus1 and sus2 are set to a width narrower than the pulse width of the first sustain pulse 1st sus, for example, 2 ms. The voltage value of the first sustain pulse sus1 is set equal to the sustain voltage Vs, and the voltage value of the second sustain pulse sus2 is set to 100 V lower than the sustain voltage Vs. Here, when the voltage value of the second sustain pulse sus2 is set to 100V, stable discharge does not occur. That is, if the voltage value of the second sustain pulse sus2 is set too low, normal sustain discharge does not occur.

In fact, the voltage value of the second sustain pulse sus2 should be set to approximately 120 V or more as shown in Figs. 6A and 6B to cause stable sustain discharge. 6A is a diagram illustrating a luminance controllable range at low gray levels.

Referring to FIG. 6A, at low gradation (approximately 12 cd / m 2 to 27 cd / m 2), the control of fine luminance is achieved by setting the voltage value of the second sustain pulse sus2 between 120 V and 180 V (here, sustain voltage Vs). It becomes possible. In other words, by setting the voltage value of the second sustain pulse sus2 between 120 V and 180 V, the luminance generated by the sustain discharge can be set within the range of approximately 15 cd / m 2 to 27 cd / m 2. In other words, in the conventional PDP, the luminance is set within the range of 15 cd / m 2 to 27 cd / m 2 in the normal luminance, that is, about 27 cd / m 2 at low gradation, so that natural luminance can be expressed.

6B is a diagram illustrating a luminance controllable range at high gradation.

Referring to FIG. 6B, in high gradation (approximately 12 cd / m 2 to 410 cd / m 2), the control of fine luminance is achieved by setting the voltage value of the second sustain pulse sus2 between approximately 120 V and 180 V (here, the sustain voltage Vs). In other words, by setting the voltage value of the second sustain pulse sus2 between 120 V and 180 V in high gradation, the luminance generated by the sustain discharge can be set within the range of approximately 260 cd / m 2 to 410 cd / m 2. In other words, the conventional PDP expresses a luminance of approximately 410 cd / m 2 at normal luminance, that is, at high gradation, whereas the luminance can be set within the range of 260 cd / m 2 to 410 cd / m 2 in the present invention, thereby enabling natural luminance. Become.

Actually, the luminance value measured with the voltage value of the second sustain pulse sus2 set to approximately 125 V as shown in Fig. 7A (PDP of the present invention) and the first and second sustain as shown in Fig. 7B (conventional PDP). Comparing the luminance values measured with the voltage value of the pulse sus2 set to the sustain voltage Vs, when the voltage value of the second sustain pulse sus2 is set to approximately 125 V as shown in FIG. It can be seen that. Meanwhile, in the present invention, as shown in FIG. 7A, the luminance value gradually decreases while approximately five sustain pulses sus1 and sus2 are initially supplied, and thereafter, the luminance value decreases.

8A to 8D are diagrams illustrating a reset voltage margin in a state in which the voltage value of the second sustain pulse sus2 is set to 130V.

Here, FIG. 8A was measured with the pulse width of the first sustain pulse (1st sus) set to 2 Hz, and FIG. 8B was measured with the pulse width of the first sustain pulse (1st sus) set to 3 Hz. 8C was measured with the pulse width of the first sustain pulse 1st sus set to 4 Hz, and FIG. 8D was measured with the pulse width of the first sustain pulse 1st sus set to 5 Hz.

8A to 8D, when the voltage value of the second sustain pulse sus2 is lowered to 130V while the pulse width of the first sustain pulse 1st sus is set to 2 Hz, the reset driving voltage margin is lower than that of the conventional PDP. It can be seen that this is degraded. However, it can be seen that when the voltage value of the second sustain pulse sus2 is lowered to 130 V while the pulse width of the first sustain pulse 1 st sus is set to 3 m or more, it has a reset driving voltage margin similar to that of a conventional PDP. . That is, in the present invention, a stable reset discharge can be generated by setting the voltage value of the second sustain pulse sus2 low while the pulse width of the first sustain pulse 1 st sus is set to 3 ms or more.

9A to 9D are diagrams illustrating address voltage margins in a state in which the voltage value of the second sustain pulse sus2 is set to 130V.

Here, FIG. 9A was measured with the pulse width of the first sustain pulse 1st sus set to 2 Hz, and FIG. 9B was measured with the pulse width of the first sustain pulse 1st sus set to 3 Hz. 9C was measured in a state where the pulse width of the first sustain pulse 1st sus was set to 4 Hz, and FIG. 9D was measured in a state where the pulse width of the first sustain pulse 1st sus was set to 5 Hz.

9A to 9D, when the voltage value of the second sustain pulse sus2 is lowered to 130V while the pulse width of the first sustain pulse 1st sus is set to 2 ms, the address driving voltage margin is lower than that of the conventional PDP. It can be seen that this is degraded. However, when the voltage value of the second sustain pulse sus2 is lowered to 130V while the pulse width of the first sustain pulse 1st sus is set to 3 m or more, it can be seen that the address driving voltage margin is similar to that of the conventional PDP. . That is, in the present invention, a stable address discharge can be caused by setting the voltage value of the second sustain pulse sus2 low while the pulse width of the first sustain pulse 1 st sus is set to 3 ms or more.

Meanwhile, in the present invention, the subfields of the present invention as shown in FIG. 4 may be applied to all subfields included in one frame. In the present invention, the conventional subfield as shown in FIG. 3 and the subfield of the present invention as shown in FIG. 4 may be used in one frame. In other words, the normal luminance may be expressed using the conventional subfield as shown in FIG. 3, and the fine luminance may be controlled using the subfield of the present invention as shown in FIG. 4. 4 may be applied to at least one frame requiring fine luminance control among i (i is a natural number) frames.

10 is a waveform diagram illustrating one subfield included in a frame according to another embodiment of the present invention.

Referring to FIG. 10, Y represents a scan electrode and Z represents a sustain electrode. X represents an address electrode.

Referring to FIG. 10, a subfield according to another embodiment of the present invention is driven by being divided into an initialization period for initializing a full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initialization period, the rising ramp waveform Ramp-up is applied to all the scan electrodes Y simultaneously. This rising ramp waveform (Ramp-up) causes a weak discharge in the cells of the full screen to form wall charges in the cells.

During the set down period, the rising ramp waveform Ramp-up is supplied, and then the falling ramp waveform Ramp-down falling from the positive voltage Vs lower than the peak voltage of the rising ramp waveform Ramp-up is applied to the scan electrodes ( Is simultaneously applied to Y). Ramp-down generates weak erase discharges in the cells, thereby eliminating wall charges and space charge line unnecessary charges generated by the setup discharges, and uniformly distributing the wall charges required for address discharges in the full screen cells. Will remain.

In the address period, a negative scan pulse scan is sequentially applied to the scan electrodes Y, and a positive data pulse data is applied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage of the wall charge generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse data is applied. Here, wall charges are generated in the discharge cells in which the address discharge is generated.

On the other hand, the positive electrode DC voltage of the sustain voltage level Vs is supplied to the sustain electrodes Z during the set down period and the address period.

In the sustain period, sustain pulses sus1 and sus2 are applied to the scan electrodes Y and the sustain electrodes Z alternately. Then, the cell selected by the address discharge is sustained in the form of surface discharge between the scan electrode Y and the sustain electrode Z each time the sustain pulse sus is applied while the wall voltage and the sustain pulse sus in the cell are added. Discharge occurs. Here, the pulse width of the first sustain pulse (1st sus) applied to the scan electrodes (Y) is set wider (approximately 3 ms or more) than the pulse widths of the remaining sustain pulses (sus1, sus2) so that a stable sustain discharge can occur. . The voltage value of the first sustain pulse 1st sus is set to the sustain voltage Vs as in the prior art.

Meanwhile, in the present invention, voltage values of the first sustain pulse sus1 applied to the scan electrodes Y and the second sustain pulse sus2 applied to the sustain electrodes Z are set differently. For example, the voltage value of the second sustain pulse sus2 is set to the sustain voltage Vs, and the voltage value of the first sustain pulse sus1 is set to the sustain voltage Vs or less. As such, when the voltage value of the first sustain pulse sus1 is set to the sustain voltage Vs or less, the amount of light generated by the sustain discharge (luminance) is lowered as compared with the prior art, thereby realizing a fine gradation luminance. Natural luminance can be expressed. That is, in another embodiment of the present invention, the luminance is adjusted while adjusting the voltage value of the first sustain pulse sus1 applied to the scan electrode Y. The other operation process and the brightness control process is the same as the embodiment of the present invention shown in FIG.

11 is a waveform diagram illustrating one subfield included in a frame according to another embodiment of the present invention.

Referring to FIG. 11, Y represents a scan electrode and Z represents a sustain electrode. X represents an address electrode.

Referring to FIG. 11, a subfield according to another embodiment of the present invention is driven by being divided into an initialization period for initializing a full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initialization period, the rising ramp waveform Ramp-up is applied to all the scan electrodes Y simultaneously. This rising ramp waveform (Ramp-up) causes a weak discharge in the cells of the full screen to form wall charges in the cells.

During the set down period, the rising ramp waveform Ramp-up is supplied, and then the falling ramp waveform Ramp-down falling from the positive voltage Vs lower than the peak voltage of the rising ramp waveform Ramp-up is applied to the scan electrodes ( Is simultaneously applied to Y). Ramp-down generates weak erase discharges in the cells, thereby eliminating wall charges and space charge line unnecessary charges generated by the setup discharges, and uniformly distributing the wall charges required for address discharges in the full screen cells. Will remain.

In the address period, a negative scan pulse scan is sequentially applied to the scan electrodes Y, and a positive data pulse data is applied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage of the wall charge generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse data is applied. Here, wall charges are generated in the discharge cells in which the address discharge is generated.

On the other hand, the positive electrode DC voltage of the sustain voltage level Vs is supplied to the sustain electrodes Z during the set down period and the address period.

In the sustain period, sustain pulses sus 1, sus 2, and sus 3 are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. Then, the cell selected by the address discharge is sustained in the form of surface discharge between the scan electrode Y and the sustain electrode Z every time the sustain pulse sus is applied while the wall voltage and the sustain pulse sus are added to the cell. Discharge occurs. Here, the pulse width of the first sustain pulse (1st sus) applied to the scan electrodes (Y) is wider than the pulse widths of the remaining sustain pulses (sus1, sus2, sus3) so that stable sustain discharge can occur (approximately 3 ms or more). Is set. The voltage value of the first sustain pulse 1st sus is set to the sustain voltage Vs as in the prior art.

The voltage values of the first sustain pulse sus1 applied to the scan electrode Y and the second sustain pulse sus2 applied to the sustain electrode Z are set to the same sustain voltage Vs as in the prior art. On the other hand, the voltage value of the third sustain pulse sus3 applied to the sustain electrode Z after the second sustain pulse sus2 is set below the sustain voltage Vs. Here, at least one third sustain pulse sus3 is applied to the sustain electrode Z.

When the luminance expression process is described in detail, first, when the first and second sustain pulses sus1 and sus2 are supplied in the sustain period, light having the same normal luminance as the conventional one is generated in the cell. Thereafter, when the first and third sustain pulses sus1 and sus3 are supplied, light lower than the normal luminance is generated in the cell. That is, in the present invention, natural luminance can be expressed by applying the third sustain pulse sus3 having a voltage lower than the sustain voltage Vs to the sustain electrode Z. FIG.

Meanwhile, the third sustain pulse sus3 may be applied to the scan electrode Y. In other words, the third sustain pulse sus3 is applied to the scan electrode Y alternately with the second sustain pulse sus2 so that natural luminance can be expressed in the cell. The other operation process and the brightness control process is the same as the embodiment of the present invention shown in FIG.

As described above, according to the driving method of the plasma display panel according to the present invention, the luminance can be adjusted by adjusting the voltage value of the sustain pulse applied to the scan electrode or the sustain electrode. As such, when the luminance is adjusted using the voltage value of the sustain pulse, natural luminance may be expressed in the plasma display panel. In addition, in the present invention, since the brightness is adjusted by using the voltage value of the sustain pulse when expressing the low gray level, it is possible to prevent the image quality deterioration phenomenon caused by the decrease in the number of the sustain pulses.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (20)

Supplying a first sustain pulse to the scan electrode during the sustain period; And supplying a second sustain pulse having a different voltage value from the first sustain pulse to the sustain electrode during the sustain period. The method of claim 1, And the voltage value of the second sustain pulse is set lower than the voltage value of the first sustain pulse. The method of claim 2, And the voltage value of the second sustain pulse is set higher than approximately 120V. The method of claim 2, And the voltage value of the second sustain pulse is set corresponding to a luminance value generated by the discharge between the scan electrode and the sustain electrode when the second sustain pulse is supplied. The method of claim 1, And a first sustain pulse having a wider pulse width than the first and second sustain pulses is supplied to the scan electrode before the first and second sustain pulses are applied. The method of claim 1, And the voltage value of the first sustain pulse is set lower than the voltage value of the second sustain pulse. The method of claim 2, And the voltage value of the first sustain pulse is set higher than approximately 120V. The method of claim 2, And the voltage value of the first sustain pulse is set corresponding to a luminance value generated by the discharge between the scan electrode and the sustain electrode when the first sustain pulse is supplied. Supplying first and second sustain pulses to the scan electrodes and the sustain electrodes to generate light corresponding to the luminance in the discharge cells; And controlling the luminance by adjusting the voltage value of any one of the first and second sustain pulses. The method of claim 9, And controlling the luminance to set the voltage value of any one of the first and second sustain pulses lower than the voltage value of the other pulses. The method of claim 9, And a first sustain pulse having a wider pulse width than the first and second sustain pulses is supplied to the scan electrode before the first and second sustain pulses are applied. The method of claim 11, And a pulse width of the first sustain pulse is set to 3 mW or more. A driving method of a plasma display panel in which one frame includes a plurality of subfields, In the sustain period of at least one subfield of the plurality of subfields, the luminance is controlled by adjusting a voltage value of any one of the first and second sustain pulses supplied to the scan electrode and the sustain electrode. Driving method. The method of claim 13, And the luminance is controlled by setting the voltage value of any one of the first and second sustain pulses lower than the voltage value of the other pulses. The method of claim 14, And a first sustain pulse having a wider pulse width than the first and second sustain pulses is supplied to the scan electrode before the first and second sustain pulses are applied. The method of claim 13, And a sustain pulse having the same voltage value is supplied in the sustain period of the remaining subfields other than the at least one subfield. Supplying a first sustain pulse to the scan electrode during the sustain period; Supplying a second sustain pulse having the same voltage value as that of the first sustain pulse to the sustain electrode during the sustain period; And supplying a third sustain pulse having a voltage value different from that of the first sustain pulse to either one of the scan electrode and the sustain electrode during the sustain period. The method of claim 17, And the voltage value of the third sustain pulse is set lower than the voltage value of the first sustain pulse. The method of claim 18, And the voltage value of the third sustain pulse is set higher than approximately 120V. The method of claim 18, And the voltage value of the third sustain pulse is set corresponding to a luminance value generated by the discharge between the scan electrode and the sustain electrode when the third sustain pulse is supplied.