KR20050009642A - Method of manufacturing a flash device - Google Patents

Abstract

PURPOSE: A method for fabricating a flash device is provided to simultaneously prevent an undercut effect of a patterned conductive layer and a gate bridge by performing an etch process using an etch condition of low selectivity with an oxide layer in over-etching a control gate conductive layer. CONSTITUTION: A tunnel oxide layer(114), the first and second conductive layers(116,118) that are patterned, a dielectric layer(120), the third conductive layer(122), a metal layer(124) and a hard mask layer(126) are sequentially formed on a semiconductor substrate(110) in which an active region and a field region are defined. The hard mask layer and the metal layer are patterned by using a gate mask. The first etch process is performed to remove the third conductive layer formed on the active region. The second etch process is performed to remove a part of the third conductive layer remaining on the field region. The third etch process is performed to remove the dielectric layer exposed to the active region and the field region. The fourth etch process is performed to completely eliminate the third conductive layer remaining on the field region. The fifth etch process is performed to eliminate the dielectric layer remaining on the field region. The sixth etch process is performed to remove the first and second conductive layers that are patterned.

Description

Method of manufacturing a flash device

The present invention relates to a method for manufacturing a flash device, and more particularly, to an etching process for forming a gate pattern.

In the flash memory device of 100 nanometers or less, the space between the polysilicon films to be used as the floating gate is reduced due to the reduction of the pattern size. There is a problem that occurs to deteriorate the electrical characteristics of the device.

In order to solve the above problems, various methods such as etching preconditioning are being studied to reduce an over-etching target or a micro loading effect during gate etching. However, in the conventional scheme, there is still a problem of freezing due to the remaining of poly residual, and as the pattern size of the gate decreases, the space between the floating gate electrodes decreases further, and the above-mentioned problem becomes more severe.

1 is a layout diagram of a flash device.

Referring to FIG. 1, a flash device includes a device isolation layer 12 for separating an active region and a field region of a semiconductor substrate 10, and a floating gate FG and a control gate CG formed on the active region.

FIG. 2 is a cross-sectional view illustrating a gate structure of a conventional flash device. FIG. 2A is a cross-sectional view taken along the line C-C 'of FIG. 1, and FIG. 2B is a cross-sectional view taken along the line B-B' of FIG.

3 is a conceptual view illustrating etching along the line C-C 'of FIG. 1 for explaining a conventional problem.

2 and 3, a conventional flash device includes a floating gate electrode 19 including a tunnel oxide film 14 and first and second conductive films 16 and 18 on an active region of a semiconductor substrate 10. And a stack gate structure in which a control gate electrode made of the dielectric film 20, the third conductive film 22, and the metal film 24 and the hard mask film 26 are stacked. In order to form the stack gate structure, the metal layer 24, the third conductive layer 22, the dielectric layer 20, the second conductive layer 18, and the first conductive layer 16 are sequentially formed on the active region. The metal film 24 and the third conductive film 22 must be sequentially etched in the field region. This etching results in areas with weak gate bridges. Due to the high level of the second conductive layer 18, the conductive layer remains in the stepped region when the third conductive layer 22 for the control gate is etched. Due to the remaining of the third conductive film 22, the dielectric film fence and the second conductive film 18 are also generated, which causes deterioration of the electrical characteristics of the device.

4 to 8 are cross-sectional views illustrating problems of a conventional method of manufacturing a flash device, a of each drawing is a cross-sectional view taken along line CC ′ of FIG. 1, b is a cross-sectional view of A-A ′, and c is B It is a sectional view of -B '.

Referring to FIG. 4, the tunnel oxide film 14, the first conductive film 16, and the device isolation layer 12 are formed by performing a self-aligned cell trench trench isolation process. After forming the second conductive film 18 for the floating gate, the second conductive film 18 is patterned to form a floating gate electrode 19 pattern composed of the first and second conductive films 16 and 18. The ONO structure dielectric film 20, the third conductive film 22 for the control gate electrode, and the metal film 24 are formed over the entire structure. After forming the hard mask film 26 on the metal film 24, a patterning process using a mask for forming a gate electrode is performed to pattern the hard mask film 26.

Referring to FIG. 5, the metal film 24 and the third conductive film 22 are etched by performing a predetermined etching process using the hard mask film 26 as an etching mask. After the main etching of the metal film 24, the metal film 24 is overetched to remove the metal film 24. After that, the main conductive etching of the third conductive film 22 is performed, whereby the third conductive film 22 on the active region is removed, whereas the third conductive film 22 of the field region is formed by the step of the second conductive film 18. Will remain.

Referring to FIG. 6, the third conductive layer 22 is excessively etched to etch the third conductive layer 22 remaining in the field region. At this time, the third conductive layer 22 exposed to the active region is etched by the excessive etching to generate an under cut. That is, the sidewall of the third conductive film 22 patterned on the active region is recessed during the excessive etching, which causes a problem of deteriorating the electrical characteristics of the device (see L region of FIG. 6B).

Referring to FIG. 7, an etching process for removing the dielectric film 20 having the ONO structure is performed. When the dielectric film 20 having the ONO structure is etched, an upper portion of the device isolation layer 12 in the field region is recessed. That is, since there is no etching selectivity difference with the lower element isolation layer 12 when the oxide layer is etched in the ONO structure, a part of the upper region of the element isolation layer 12 is etched together during the ONO etching of the sidewall of the second conductive layer 18.

Referring to FIG. 8, the second conductive layer 18 is etched by performing main etching and transient etching of the second conductive layer 18. At this time, the first conductive film 16 under the second conductive film 18 is also etched together to isolate the floating gate electrode 19 pattern, whereby the tunnel oxide film 14, the isolated floating gate electrode 19, and the dielectric film ( 20) and the control gate electrodes 22 and 24 form a stacked gate electrode.

However, as described above, when the third conductive layer 22 remaining above the field region is not completely removed when the third conductive layer 22 for the control gate electrode is etched, many problems may occur. Problems will arise.

FIG. 9A is a SEM photograph on line C-C 'of FIG. 1 after patterning the control gate electrode, and FIG. 9B is an SEM photograph on line B-B' of FIG. 1.

FIG. 10A is a SEM photograph on line C-C 'of FIG. 1 after etching the gate electrode, and FIG. 10B is a SEM photograph on line B-B' of FIG. 1.

9A, 9B, 10A, and 10B, an undercut phenomenon occurs due to the excessive etching of the third conductive film for removing the third conductive film remaining on the field region, thereby causing the third for the control gate. The phenomenon that the sidewall area of the conductive film is recessed occurs.

11 is a conceptual diagram illustrating a problem by a conventional etching method.

Referring to FIG. 11, in the third conductive film transient etching, negative ions are built up in the upper part of the pattern, and thus, negative ions do not reach the lower part, and positive ions are built up in the lower part of the pattern. Due to the positive ions built up in the lower part, the trajectory of the positive ions is deformed and undercut occurs. The undercut of the third conductive layer is a phenomenon caused by the charge built up in the pattern after the etching of the third conductive layer is completed. The larger the transient etching target, the larger the pattern aspect ratio. That gets worse.

12A to 12C are SEM images of devices according to the transient etching target of the conductive film for the control gate.

12A to 12C, the fan shape of the dielectric film and the residual phenomenon of the third conductive film are generated according to the etching target of the third conductive film transient etching for the control gate electrode, or the undercut shape of the third conductive film or the element isolation film A loss-like phenomenon occurs.

The above-mentioned problem is that as the flash device becomes more and more integrated, the pattern aspect ratio increases and the gap between the floating gate electrodes becomes narrow, so that in the third conductive film etching for the control gate, both the undercut and the gate bridge of the third conductive film are free. The free etch target range becomes narrower. In fact, in the tech of about 120 nm or less, a problem arises in that the above-described etching target range does not exist.

Accordingly, the present invention can solve the undercut phenomenon of the patterned conductive film and the gate bridge at the same time by performing an etching process using an etching condition having a low selectivity with respect to the oxide film when the control gate conductive film is excessively etched to solve the above problems. Provided is a method of manufacturing a flash device capable of increasing the thickness of a conductive film for a gate, thereby increasing a coupling ratio of the device.

1 is a layout diagram of a flash device.

FIG. 2 is a cross-sectional view illustrating a gate structure of a conventional flash device. FIG. 2A is a cross-sectional view taken along the line C-C 'of FIG. 1, and FIG. 2B is a cross-sectional view taken along the line B-B' of FIG.

3 is a conceptual view illustrating etching along the line C-C 'of FIG. 1 for explaining a conventional problem.

4 to 8 are cross-sectional views illustrating problems of a conventional method of manufacturing a flash device, a of each drawing is a cross-sectional view taken along line CC ′ of FIG. 1, b is a cross-sectional view of A-A ′, and c is B It is a sectional view of -B '.

FIG. 9A is a SEM photograph on line C-C 'of FIG. 1 after patterning the control gate electrode, and FIG. 9B is an SEM photograph on line B-B' of FIG. 1.

FIG. 10A is a SEM photograph on line C-C 'of FIG. 1 after etching the gate electrode, and FIG. 10B is a SEM photograph on line B-B' of FIG. 1.

11 is a conceptual diagram illustrating a problem by a conventional etching method.

12A to 12C are SEM images of devices according to the transient etching target of the conductive film for the control gate.

13 to 19 are cross-sectional views illustrating a method of manufacturing a flash device according to the present invention, each of which is a cross-sectional view along the line CC ′ of FIG. 1, b is a cross-sectional view along the line AA ′, and c is a line along the line BB ′. It is a cross section of.

20A through 20C are SEM images of an active region and a field region according to gate etching of a flash device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10, 110: semiconductor substrate 12, 112: device isolation film

14, 114: tunnel oxide film

19, 119: floating gate pattern 20, 120: dielectric film

24, 124: metal film 26, 126: hard mask film

16, 18, 22, 116, 118, 122: conductive film

Sequentially forming a tunnel oxide film, a patterned first and second conductive film, a dielectric film, a third conductive film, a metal film, and a hard mask film on a semiconductor substrate in which an active region and a field region are defined according to the present invention; Patterning the hard mask layer and the metal layer using a gate mask, removing the third conductive layer formed on the active region by performing a first etching process, and performing a second etching process on the field region Removing a portion of the third conductive film remaining in the phase; performing a third etching to remove the dielectric film exposed to the active region and the field region; and performing a fourth etching process to remove the dielectric layer exposed to the field region. Completely removing the third conductive film remaining in the substrate; and performing a fifth etching to remove the dielectric film remaining in the field region and a sixth etching. It provides a method of manufacturing a flash device comprising the step of removing the patterned first and first conductive film.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

One embodiment of the present invention can achieve the above object by changing the etching process and etching conditions of the conductive film for the control gate electrode and the dielectric film during the etching step for forming the gate electrode of the flash device.

In the flash device, a device isolation film is formed in a field region, and a third conductive film for a dielectric film control gate electrode and a metal film are formed on a semiconductor substrate on which a floating gate electrode pattern composed of a tunnel oxide film and a first and a second conductive film is formed in an active region. And a hard mask film are formed, and then a hard mask film is patterned. The metal film is patterned using the patterned hard mask film.

The first etching is performed to etch the third conductive film for the control gate electrode formed on the active region. The second etching is performed to remove a part of the third conductive film for the control gate electrode remaining on the field region. In the second etching process, the etching rate is about 50 to 100% based on the thickness of the etched third conductive film in the active region under an etching condition in which the etching selectivity with respect to the oxide film is 10 or more. The third etching is performed to remove the dielectric film in the exposed region. In the third etching process, the etching rate is about 200 to 300% of the thickness of the dielectric film under an etching condition in which the etching selectivity with respect to the oxide film is 1 or less. The fourth etching is performed to completely remove the third conductive film remaining on the field region. During the fourth etching, the etching rate is about 50 to 80% of the thickness of the floating gate electrode under etching conditions in which the etching selectivity with respect to the oxide layer is 10 or more. The fifth etching is performed to remove the dielectric film remaining in the field region. During the fifth etching, the etching rate is 300 to 500% of the thickness of the dielectric film under an etching condition in which the etching selectivity with respect to the oxide film is 1 or less. The floating gate electrode pattern is isolated by removing the exposed second and first conductive layers by performing the sixth etching. Thus, it is preferable to form a gate electrode of a flash element in which a tunnel oxide film, an isolated floating gate electrode, a dielectric film, and a control gate electrode are stacked. In the first to sixth etching, a patterned hard mask layer may be used as an etching mask. In addition, all or part of the first to sixth etching may be performed in situ according to etching conditions.

The spacing between the control gate electrodes of the flash element is about 0.115 mu m and the spacing between the floating gate electrodes is 0.07 mu m. The width of the floating gate electrode is about 0.115 μm, and the width of the first conductive film for the floating gate electrode is about 0.12 μm.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

13 to 19 are cross-sectional views illustrating a method of manufacturing a flash device according to the present invention, each of which is a cross-sectional view along the line CC ′ of FIG. 1, b is a cross-sectional view along the line AA ′, and c is a line along the line BB ′. It is a cross section of.

Referring to FIG. 13, the tunnel oxide film 114, the first conductive film 116, and the device isolation layer 118 are formed by performing a self-aligned cell trench trench isolation process on the semiconductor substrate 110 having active and field regions defined therein. Form. After forming the second conductive layer 118 for the floating gate, the second conductive layer 118 is patterned to form a pattern of the floating gate electrode 119 including the first and second conductive layers 116 and 118. An ONO structure dielectric film 120, a third conductive film 122 for control gate electrodes, and a metal film 124 are formed over the entire structure. After forming the hard mask film 126 on the metal film 124, a patterning process using a mask for forming a gate electrode is performed to pattern the hard mask film 126.

A tunnel oxide film 114, a first conductive film 116, and a pad insulating film (not shown) are formed on the semiconductor substrate 110. The pad insulating layer, the first conductive layer 116, the tunnel oxide layer 114, and the semiconductor substrate 110 are sequentially etched through ISO mask patterning to form a shallow trench isolation (STI) structure. It is effective to form trenches (not shown). A high density plasma (HDP) oxide film is deposited on the entire structure to fill the trench. The planarization process may be performed to remove the HDP oxide film on the pad insulating film, and the predetermined isolation process may be performed to remove the pad insulating film to form the device isolation film 112. In addition, the device isolation layer 112 may be formed by removing the pad insulating layer and the HDP oxide layer on the first conductive layer 116 through the planarization process. This defines the active area and the field area.

The tunnel oxide film 114 is preferably formed through a wet oxidation process. The first conductive film 116 to be used for the buffer or as part of the floating gate is preferably formed by depositing an undoped amorphous silicon film on the tunnel oxide film 114. The pad insulating film may be formed using a nitride film based material film (LP-Nitride, PE-Nitride or Oxynitride) and an oxide film based material film (PE-TEOS, LP-TEOS, HOT or USG).

The floating gate pattern 119 is formed by depositing a second conductive layer 118 on the semiconductor substrate 110 on which the device isolation layer 112, the tunnel oxide layer 114, and the first conductive layer 116 are formed. It is preferable to form the pattern 118. As a result, the floating gate pattern 119 including the tunnel oxide layer 114 and the first and second conductive layers 116 and 118 may be formed on the active region of the semiconductor substrate 118. In the patterning of the second conductive layer 118, a photosensitive layer is coated on the second conductive layer 118 and then subjected to a photolithography process using a floating gate mask to form a photosensitive layer pattern (not shown). It is preferable to include the process of etching the 2nd conductive film 118 by performing the etching process used as an etching mask. In this case, in order to improve the degree of integration of the device, etching may be performed without inclination, or etching with a certain inclination may be performed. In order to form a gate pattern of 100 nanometers or less, it is preferable to form a floating gate electrode having a vertical shape and to pattern a portion overlapping with a part of the field region to prevent an alignment error. For example, when the floating gate pattern is formed by etching with a constant slope, the spacing between the floating gate patterns has a width of 140 to 60 μs by the slop. However, when the floating gate pattern is formed by performing the inclination-free etching, the gap between the floating gate patterns may have a width of about 70 to about 40 μs. The second conductive film 118 is preferably formed using a polysilicon film having a thickness that can maximize the coupling ratio of the flash memory device.

The dielectric film 120, the third conductive film 122, the metal film 124, and the hard mask film 126 are sequentially formed on the entire structure.

The dielectric film 120 preferably forms an ONO (first oxide film-nitride film-second oxide film; SiO ₂ -Si ₃ N ₄ -SiO ₂ ) dielectric film 120. The third conductive film 122 is preferably formed of a polysilicon film that is a conductive material film for forming a control gate, and the metal film 124 is preferably formed of a tungsten silicide film. The hard mask layer 126 may be formed using a nitride layer-based material layer (LP-Nitride, PE-Nitride or Oxynitride) and an oxide layer-based material layer (PE-TEOS, LP-TEOS, HOT, or USG). .

The hard mask film 126 is patterned using a control gate mask. In the patterning of the hard mask layer 126, a photoresist layer is coated on the hard mask layer 126, and then a photolithography process is performed using a control gate mask to form a photoresist pattern (not shown), and the photoresist pattern is etched. It is preferable to include the process of etching the hard mask film 126 by performing the etching process used as a mask.

Referring to FIG. 14, it is preferable to perform a break through etching to remove a native oxide formed on the entire structure. Using the hard mask layer 126 as an etching mask, it is preferable to remove the metal layer 124 by performing main etching for removing the metal layer 124 and transient etching for removing the metal layer 124. The metal film main etching refers to a stock angle for removing the metal film 124, and the excessive etching of the metal film 124 further etches for a predetermined time under the same etching conditions to remove the remaining metal film 124. Refers to implementation.

First etching is performed to remove the third conductive layer 122. The first etching refers to the main etching for removing the third conductive layer 122, and it is preferable to remove the third conductive layer 122 on the active region as a target. At this time, the third conductive film 122 on the field region is left between the steps by the step height of the second conductive film 118. Since the metal film 124 and the third conductive film 122 are each formed using a tungsten silicide film and a polysilicon film, etching processes for etching them are preferably performed under different etching conditions.

Referring to FIG. 15, a portion of the third conductive layer 122 remaining on the field region is removed by performing a second etching. The second etching refers to a transient etching for removing the remaining third conductive film 122, it is preferably carried out under an etching condition that does not cause the undercut phenomenon in the third conductive film 122 patterned in the active region. Do. The second etching may be etched by about 50 to 100% based on the thickness of the etched third conductive layer 122 in the active region under an etching condition in which the etching selectivity with respect to the oxide layer is 10 or more. The second etching is preferably performed using at least one of HBr, Cl 2 and O 2 gases. The etching selectivity with respect to the oxide film is preferably about 10 to 30. As a result, the space between the second conductive film 118 in the field region is not filled with the third conductive film 122, and a part of the third conductive film 122 remains in the lower predetermined region.

Referring to FIG. 16, a third etching is performed to remove the dielectric film 120 in the exposed region. The third etching refers to oxide etching for removing the dielectric film 120. The third etching removes the dielectric film 120 on the active region to prevent an undercut shape that may occur during the subsequent etching of the remaining third conductive film 122. It is preferable. That is, the charge is prevented from building up by removing the dielectric film 120 of the ONO structure on the active region. The third etching is an etching condition for etching the dielectric film 120 having the ONO structure. The third etching may be performed such that 200 to 300% of the thickness of the dielectric film 120 having the etching selectivity with respect to the oxide film is 1 or less is etched. It is preferable to use the F series etching gas for 3rd etching. It is preferable that the etching selectivity with respect to the oxide film is 0.1 to 1 so that the ratio of etching of the oxide film is larger than that of the conductive film. As a result, a part of the second conductive film 118 1 on the active region is exposed.

Referring to FIG. 17, a fourth etching is performed to remove the remaining third conductive layer 122. The fourth etching refers to the transient etching for removing the third conductive layer 122, and removes the third conductive layer 122 remaining on the field region and exposes the second conductive layer 118 on the active region. It is also desirable that some of) be removed together. The etching step of the second conductive layer 118 can be reduced, and the gate bridge phenomenon of the device can be prevented. The fourth etching may be performed to etch about 50 to 80% of the thickness of the floating gate electrode under etching conditions in which the etching selectivity with respect to the oxide film is 10 or more. It is preferable to perform 4th etching using at least any one of HBr, Cl2, and O2 gas. The etching selectivity with respect to the oxide film is preferably about 10 to 30. As a result, the third conductive film 122 remaining in the space between the second conductive films 118 in the field region can be completely removed, and the undercut phenomenon of the third conductive film 122 in the active region occurs during the etching process. In addition, a portion of the exposed second conductive layer 118 may also be removed to shorten the time of the etching process and to secure an etching margin during the etching process for isolation of the subsequent floating gate electrode pattern.

Referring to FIG. 18, a fifth etching is performed to remove the dielectric film 120 remaining in the field region. The fifth etching refers to oxide etching for removing the dielectric film 120, and may prevent a phenomenon in which the dielectric film 120 is generated in the field region. The fifth etching is an etching condition for etching the dielectric film 120 of the ONO structure, and the dielectric film 118 remaining on the sidewall of the second conductive film 118 for the floating gate electrode pattern when the etching selectivity with respect to the oxide film is 1 or less. Although completely removed, etching may be performed such that 300 to 500% of the thickness of the dielectric film 118 is etched. The portion of the upper portion of the device isolation layer 112 in the field region may be etched by the etching target of the fifth etching for etching the dielectric layer 118. It is preferable to use the F series etching gas for the 5th etching. It is preferable that the etching selectivity with respect to the oxide film is 0.1 to 1 so that the ratio of etching of the oxide film is larger than that of the conductive film. In addition, the fifth etching is preferably performed by etching having an isotropic characteristic.

Referring to FIG. 19, a sixth etching is performed to isolate the floating gate pattern 119 to form a gate electrode of a flash device. The sixth etching refers to the main etching and the transient etching for isolating the floating gate pattern. The sixth etching removes the first and second conductive layers 116 and 118 on the field region and exposes the first and second portions to the active region. It is preferable to remove the conductive films 116 and 118. The main etching may be performed under etching conditions in which the etching selectivity with respect to the oxide film is increased by 10, and the transient etching may be performed under etching conditions in which the etching selectivity with respect to the oxide film is 50 or more. Thus, it is preferable to form the gate electrode of the flash element in which the tunnel oxide film 114, the isolated floating gate electrode 119, the dielectric film 120, and the control gate electrode are stacked. In the first to sixth etching, a patterned hard mask layer may be used as an etching mask. In addition, all or part of the first to sixth etching may be performed in situ according to etching conditions.

Table 1 is an etching table according to the overall etching step according to an embodiment of the present invention.

setp B.T Metal Film Main Etch Metal Film Over Etch 3rd conductive film Main Etch Third Conductive Film 1st Over Etch Oxide 1 Etch Third Conductive Film 1st Over Etch 2nd Oxide Etch 2nd conductive film Main Etch 2nd conductive film Over Etch Etch Film Native oxide Wsix Wsix & Poly Poly Poly ONO Poly ONO Poly Poly Process Requirement Slightly slope Completely Remove Wsix Verticla Removal of the third conductive film between the second conductive films (~ 700Å) Remove ONO on active area Complete removal of 3rd conductive film (between 2nd conductive film) ONO Fence Free Vertical Vertical Oxide selectivity > 5 > 10 <1.0 > 10 > 10 > 50

20A through 20C are SEM images of an active region and a field region according to gate etching of a flash device according to the present invention.

20A to 20C, an undercut phenomenon in which the third conductive film for the control gate electrode is etched does not appear, an ONO fence used as the dielectric film, and a residual phenomenon of the third conductive film do not appear. It is possible to prevent the membrane from being damaged.

As described above, the present invention can simultaneously solve the undercut phenomenon of the patterned conductive film and the gate bridge by performing an etching process using an etching condition having a low selectivity with respect to the oxide film when the control gate conductive film is excessively etched.

Regardless of the aspect ratio of the pattern, undercut of the control gate conductive film, panning of the dielectric film, and residual generation of the floating gate conductive film can be suppressed.

In addition, since the thickness of the conductive film for the floating gate can be increased, the coupling ratio of the device can be increased.

Claims (5)

Sequentially forming a tunnel oxide film, a patterned first and second conductive film, a dielectric film, a third conductive film, a metal film, and a hard mask film on a semiconductor substrate in which an active region and a field region are defined; Patterning the hard mask layer and the metal layer using a gate mask; Performing a first etching to remove the third conductive layer formed on the active region; Performing a second etching to remove a portion of the third conductive film remaining on the field region; Performing a third etching to remove the dielectric film exposed to the active region and the field region; Performing a fourth etching to completely remove the third conductive film remaining on the field region; Performing a fifth etching to remove the dielectric film remaining in the field region; And And removing the patterned first and first conductive layers by performing a sixth etching process. The method of claim 1, The second etching is performed under an etching condition in which the etching selectivity with respect to the oxide film is 10 or more to etch about 50 to 100% based on the thickness of the third conductive film etched in the active region. The method of claim 1, The third etching is a method of manufacturing a flash device for etching about 200 to 300% of the thickness of the dielectric film under an etching condition that the etching selectivity to the oxide film is 1 or less. The method of claim 1, The fourth etching is a method of manufacturing a flash device for etching 50 to 80% of the thickness of the patterned first and second conductive film under an etching condition that the etching selectivity to the oxide film is 10 or more. The method of claim 1, The fifth etching is a method of manufacturing a flash device for etching about 300 to 500% of the thickness of the dielectric film under an etching condition that the etching selectivity to the oxide film is 1 or less.