KR20050008313A - The method for forming capacitor in semiconductor device - Google Patents

Abstract

PURPOSE: A method of forming a capacitor of a semiconductor device is provided to prevent leakage current by forming an insulating layer on an undercut part of an insulator layer. CONSTITUTION: A first metal layer, an insulator layer, a second metal layer, and a hard mask are sequentially formed on a semiconductor substrate. An upper electrode region is defined by forming a photoresist pattern on the hard mask. The hard mask is etched by using the photoresist pattern as a mask. The first metal layer is etched by using the photoresist pattern and the remaining hard mask as masks. The photoresist pattern is removed therefrom. The insulator layer is etched by using the remaining hard mask as a mask. An oxide layer(210) is formed on the resultant structure.

Description

The method for forming capacitor in semiconductor device

The present invention relates to a method of forming a capacitor of a semiconductor device, and more particularly, to a method of forming a capacitor having a metal-insulator-metal structure (hereinafter, referred to as MIM).

In the manufacture of semiconductor integrated circuits, MIM capacitors are generally applied in the implementation of analog circuits in the RF band. The MIM capacitor has a metal-insulator-metal structure in which upper and lower electrodes are formed through an insulator, and a poly-insulator-poly (PIP) and a low depletion and low resistance metal material are used as the upper and lower electrodes. Compared to a capacitor having a poly-insulator-metal (PIM) structure, the capacitor has a high quality factor (Q).

1A to 1G are cross-sectional views illustrating a method of forming a MIM capacitor according to the prior art.

Referring to FIG. 1A, in order to form a MIM capacitor, a conventional method first forms a first metal film 100, an insulator film 102, and a second metal film 104 on top of a semiconductor substrate.

The first metal film 100 has a structure in which a Ti / TiN film 100a, an Al film 100b, and a Ti / TiN film 100c are sequentially deposited on an upper surface of a semiconductor substrate, and the second metal film 104 is formed. ) Has a structure in which a TiN film having a single structure is laminated on the insulator film 102.

The first metal film 100 may be formed of a Ti / TiN / Al / Ti / TiN or TiN / Al / Ti / TiN structure, and the second metal film 104 may include Ti / TiN, TiN, Al, It can be formed in a single structure for the structure combining W and a specific metal or the like, or for each of Ti / TiN, TiN, Al, W and a specific metal.

The Al film 100a has a low resistance to serve to transmit a substantial electrical signal, and may be replaced with tungsten (W). In the Ti / TiN film 100c, titanium (Ti) serves as an adhesive film for increasing adhesion between upper and lower layers formed of different materials, and titanium nitride (TiN) emits light when patterning a photoresist. It acts as an anti-reflective coat layer that absorbs and reduces the reflection of light.

Meanwhile, the insulator film 102 is formed using an oxide having a high dielectric constant, and is generally a film of silicon oxynitride (SiO _X N _Y ) and silicon nitride (Si ₃ N ₄ ) material or PECVD (Plasma-Enhanced). It is made of an oxide film formed by the Chemical Vapor Deposition method.

Although not shown in the drawings, in order to electrically connect the semiconductor substrate on which the semiconductor device is integrated with the first metal film 100 through an interlayer insulating film, that is, a Pre Metal Dielectric (PMD) or an Inter Metal Dielectric (IMD). It should be noted that the contact plug is formed under the first metal film 100.

Referring to FIG. 1B, a photoresist is applied on the second metal layer 104 and then patterned to form a photoresist pattern 106 defining an upper electrode of the MIM capacitor.

Referring to FIG. 1C, the second metal film is formed by using a plasma activated by a combination of Cl ₂ / BCL ₃ / N ₂ gas with the photoresist pattern 106 formed on the second metal film 104 as a mask. By dry etching 104, the upper electrode 104a of the MIM capacitor is formed.

Then, after removing the photoresist pattern 106, the gas having the upper electrode 104a as a mask and the main components of 'C' and 'F', such as CF ₄ , C ₂ F ₆ , C ₄ F ₈ , C _The remaining insulator film 102a is formed by dry etching the insulator film 102 using a plasma activated by a combination of CxFy gas such as _{5F 8} . At this time, an under cut occurs in the lower portion of the second metal film 104 as in A of FIG. 1C.

The undercut may be caused by ion sputtering when plasma ions are in contact with the first metal film 100 during plasma etching, thereby insulating the insulator film 102 under the second metal film 104. Because.

When Fig. 1d and FIG. 1e, of the resultant product after the front applying a photoresist on the photoresist after forming the pattern 108, the photoresist as a mask, the pattern 106 and the Cl ₂ / BCL ₃ / N ₂ gas The first metal film 100 is etched using the plasma activated by the combination to form the lower metal wiring film 110a and the lower electrode 110b of the MIM capacitor. Accordingly, the first metal film 100 is divided into the lower metal wiring region R1 and the MIM capacitor region R2.

Referring to FIG. 1F, an interlayer insulating film 112 is formed on the resultant, and then the surface thereof is planarized and controlled at the same time through a chemical mechanical polishing (CMP) process. In this case, when a single layer of oxide material is applied to form the interlayer insulating layer 112, the interlayer insulating layer 112 may be formed due to the surface topology of the lower metal wiring region R1 and the MIM capacitor region R2. Full planarization is not achieved.

Accordingly, the interlayer insulating film 112 is a single film composed of a BPSG film for complete planarization, or a double film or a laminated film of a planarizing film 112a such as SOG, FOX, and FSG and a PE-TEOS film 112b. It consists of.

Referring to FIG. 1G, via holes exposing portions of the lower metal wiring layer 110a and the lower electrode 110b and the upper electrode 104a of the MIM capacitor may be selectively etched by selectively etching portions of the interlayer insulating layer 112. Then, a conductive material such as tungsten (W) or copper (Cu) is embedded in the exposed via hole to form contact plugs 114a, 114b, and 114c.

Next, a metal film having a deposition structure of Ti / TiN / Al / Ti / TiN is formed on the entire surface of the resultant product in the same manner as the first and second metal films 100 and 104 and then patterned to form upper metal wiring films 116a and 116b. 116c). As a result, the contact plugs 114a, 114b, and 114c are electrically coupled to the corresponding upper metal wiring layers 116a, 116b, and 116c.

However, in the conventional MIM capacitor manufacturing method, the source of leakage current when the undercut generated when the upper electrode is formed is electrically connected to the lower electrode 110b and the upper electrode 104a of the MIM capacitor to the upper metal wiring films 116b and 116c. Will act as.

In order to solve this problem, if the etching amount of the insulator film 102 is reduced by controlling the progress of plasma dry etching, a bridge is generated between the upper electrode and the lower electrode of the MIM capacitor when the upper metal wiring film is formed.

Accordingly, the present invention provides a method for forming a capacitor of a semiconductor device to prevent the occurrence of leakage current by forming an MIM capacitor to insulate the lower electrode and the upper electrode by forming an insulating film on the undercut portion of the insulator film to solve the above problems. There is.

1A to 1G are cross-sectional views illustrating a method of forming a MIM capacitor according to the prior art.

2A to 2D are cross-sectional views illustrating a method of forming a MIM capacitor according to an embodiment of the present invention.

The present invention for achieving the above object, in the method of forming a capacitor of a semiconductor device having a metal-insulator-metal structure, the first metal film, the insulator film, the second metal film and a hard mask sequentially on the semiconductor substrate Forming to; Defining an upper electrode region by forming a photoresist pattern on the hard mask; A first etching step of etching the hard mask using the photoresist pattern as a mask; A second etching step of etching the first metal layer using the photoresist pattern and the hard mask remaining by the first etching step as a mask; Removing the photoresist pattern and etching the insulator film using the remaining hard mask as a mask; And forming an oxide film on the entire surface of the resultant product.

Preferably, the present invention comprises the steps of forming an interlayer insulating film on the entire surface of the resultant;

Etching the interlayer insulating layer to form at least two via holes; Embedding a conductive metal material in the at least two via holes to form a contact plug; And forming at least two or more upper metal interconnection layers on the resultant.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2D are cross-sectional views illustrating a method of forming a MIM capacitor according to an embodiment of the present invention.

Referring to FIG. 2A, first, the first metal film 200, the insulator film 202, the second metal film 204, and the hard mask 206 are sequentially formed on the semiconductor substrate.

The first metal film 200 has a structure of Ti / TiN / Al / Ti / TiN or TiN / Al / Ti / TiN on a semiconductor substrate, and the second metal film (not shown) is an upper electrode of a MIM capacitor. As a film for forming a film, a TiN film having a single structure is formed on the insulator film 202.

In addition, the second metal film (not shown) may be formed in a structure in which Ti / TiN, TiN, Al, W, and a specific metal are combined, and the single metal for each Ti / TiN, TiN, Al, W, and a specific metal. It may also be formed into a structure.

On the other hand, the insulator film 202 is formed using an oxide having a high dielectric constant, and is generally a film of silicon oxynitride (SiO _X N _Y ) and silicon nitride (Si ₃ N ₄ ) material or PECVD (Plasma-Enhanced) It is made of an oxide film formed by the Chemical Vapor Deposition method.

On the other hand, the hard mask 206 is for protecting the second metal film 204 during the etching of the second metal film 204 to be formed as the upper electrode of the MIM capacitor, it is formed using a nitride film.

Although not shown in the drawings, in order to electrically connect the semiconductor substrate on which the semiconductor device is integrated with the first metal film 200 through an interlayer insulating film, that is, a Pre Metal Dielectric (PMD) or an Inter Metal Dielectric (IMD). It should be noted that the contact plug is formed under the first metal film 200.

Next, a photoresist is applied on the second metal film 204 and then patterned to form a photoresist pattern 208 defining an upper electrode of the MIM capacitor.

Referring to FIG. 2B, the hard mask 206 is formed by using a photoresist pattern 208 formed on the second metal layer 204 as a mask and using a plasma activated by a combination of CHF ₃ / CF ₄ / Ar gases. Dry etch. At this time, in order to dry etch the hard mask 206, a gas mainly composed of 'C' and 'F', for example, C _X F such as CF ₄ , C ₂ F ₆ , C ₄ F ₈ , C ₅ F _8, and the like. _Y gas may be used, and one of N 2 / O 2 / He may be optionally added to the C _X F _Y gas. As a result, a part of the hard mask 206 remains on the second metal film 204.

Next, using the photoresist pattern 208 and the remaining hard mask (not shown) as a mask, the second metal film 204 is formed using a plasma activated by a combination of Cl ₂ / BCL ₃ / N ₂ gas. By dry etching, the upper electrode 204a of the MIM capacitor is formed.

Subsequently, the photoresist pattern 206 is removed, and then the remaining hard mask and the insulator film 202 are simultaneously etched by performing an etching process based on CF ₄ / O ₂ based on a downflow rather than a plasma. do. In FIG. 2B, reference numeral 202a denotes an insulator film remaining after the downflow etching process.

As described above, even when the insulator film 202 is etched by the downflow method, an under cut still exists under the upper electrode 204a.

Therefore, in the present invention, since the second metal film 204 is dry etched using the photoresist pattern and the hard mask as etch barriers, it is possible to prevent the upper electrode 204a of the MIM capacitor from being damaged.

Referring to FIG. 2C, the resultant is exposed to O ₂ or O ₃ to form an oxide film 210 on the entire surface of the resultant. At this time, an undercut existing under the upper electrode 204a is filled with an oxide film.

Although not shown in the drawing, the first metal film 200 is patterned and divided into a lower metal wiring region and a MIM capacitor region. As a result, the lower electrode 200a of the MIM capacitor is formed.

Referring to FIG. 2D, after forming the interlayer insulating film 212 on the entire surface of the resultant, planarizing the CMP interlayer insulating film 212, and then forming the lower electrode 200a and the upper electrode 204a of the MIM capacitor in a subsequent process. The interlayer insulating layer 212 is etched to electrically connect the upper metal wiring layer to be formed to form a via hole.

Next, a conductive material such as tungsten (W) or copper (Cu) is embedded in the via hole to form contact plugs 214a and 214b.

Then, the conductive metal material is deposited and patterned on the entire surface of the resultant to form upper metal wiring films 216a and 216b. Accordingly, the contact plugs 214a and 214b are electrically coupled to the corresponding upper metal wiring films 216a and 216b.

While specific embodiments of the present invention have been described and illustrated above, it will be apparent that the present invention may be modified and practiced by those skilled in the art. Such modified embodiments should not be individually understood from the technical spirit or the prospect of the present invention, but should fall within the claims appended to the present invention.

As described above, according to the present invention, the front surface of the upper electrode is surrounded by the oxide film and the undercut formed under the upper electrode is filled with the oxide film to electrically insulate the upper and lower electrodes of the MIM capacitor, thereby eliminating the occurrence of bridges. There is an effect that can prevent the leakage current.

Claims (7)

In the method of forming a capacitor of a semiconductor device having a metal-insulator-metal structure, Sequentially forming a first metal film, an insulator film, a second metal film, and a hard mask on the semiconductor substrate; Defining an upper electrode region by forming a photoresist pattern on the hard mask; A first etching step of etching the hard mask using the photoresist pattern as a mask; A second etching step of etching the first metal layer using the photoresist pattern and the hard mask remaining by the first etching step as a mask; Removing the photoresist pattern and etching the insulator film using the remaining hard mask as a mask; And Forming an oxide film on the entire surface of the resultant. The method of claim 1, The first etching step is dry etching using a plasma activated by a combination of CHF ₃ / CF ₄ / Ar gas. The method of claim 1, The first etching step is a dry etching method of the semiconductor device, characterized in that the dry etching using a plasma activated by C _X F _Y containing 'C' and 'F' as a main component. The method of claim 3, wherein The first etching step is dry etching using a plasma activated by the gas selectively added one of N2 / O2 / He to the C _X F _Y gas. The method of claim 1, The second etching step is dry etching using a plasma activated by a combination of Cl ₂ / BCL ₃ / N ₂ gas. The method of claim 1, The third etching step is a method of forming a capacitor of a semiconductor device, characterized in that for etching on the basis of CF ₄ / O ₂ based on the downflow method. The method of claim 1, Forming an interlayer insulating film on the entire surface of the resultant product; Etching the interlayer insulating layer to form at least two via holes; Embedding a conductive metal material in the at least two via holes to form a contact plug; And And forming at least two upper metal wiring films on the resultant.