KR20050008056A - TSOP stack package - Google Patents
TSOP stack package Download PDFInfo
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- KR20050008056A KR20050008056A KR1020030047741A KR20030047741A KR20050008056A KR 20050008056 A KR20050008056 A KR 20050008056A KR 1020030047741 A KR1020030047741 A KR 1020030047741A KR 20030047741 A KR20030047741 A KR 20030047741A KR 20050008056 A KR20050008056 A KR 20050008056A
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- solder paste
- shoulder portion
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1064—Electrical connections provided on a side surface of one or more of the containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체 패키지에 관한 것으로, 특히, 바텀 패키지의 쇼율더 부위에서 솔더 페이스가 흘러내리는 것을 방지한 TSOP 스택 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a TSOP stack package which prevents a solder face from flowing down at a portion of a bottom package.
전기/전자 제품의 고성능화가 진행됨에 따라 한정된 크기의 기판에 더 많은 수의 패키지를 실장하기 위한 많은 기술들이 제안 및 연구되고 있다. 그런데, 패키지는 하나의 반도체 칩이 탑재되는 것을 기본으로 하기 때문에 용량 증가에 한계가 있다.As the performance of electrical / electronic products is advanced, many technologies for mounting a larger number of packages on a limited size substrate have been proposed and studied. However, since the package is based on one semiconductor chip mounted there is a limit to the capacity increase.
여기서, 메모리 칩의 용량 증대, 즉, 고집적화를 이룰 수 있는 방법으로는 한정된 공간 내에 보다 많은 수의 셀을 제조해 넣는 기술이 일반적으로 알려져 있다. 그런데, 이와 같은 방법은 정밀한 미세 선폭을 요구하는 등, 고난도의 공정 기술과 많은 개발 시간을 필요로 한다. 따라서, 보다 용이하게 고집적화를 이룰 수 있는 방법으로서 스택킹(stacking) 기술이 개발되었고, 현재 이에 대한 연구가 활발히 진행되고 있다.Here, as a method of increasing the capacity of the memory chip, that is, high integration, a technique of manufacturing a larger number of cells in a limited space is generally known. However, such a method requires a high level of process technology and a lot of development time, such as requiring a precise fine line width. Therefore, a stacking technology has been developed as a method of achieving high integration more easily, and researches on this are being actively conducted.
반도체 업계에서 말하는 스택킹이란, 적어도 2개 이상의 반도체 칩을 스택하여 메모리 용량을 배가시키는 기술이다. 이러한 스택킹 기술에 의하면, 2개의 64M DRAM급 칩을 스택하여 128M DRAM급으로 구성할 수 있고, 또한, 2개의 128M DRAM급 칩을 스택하여 256M DRAM급으로 구성할 수 있다. 게다가, 스택킹 기술에 의하면, 실장 밀도 및 실장 면적 사용의 효율성 측면에서 잇점을 갖는다.Stacking as used in the semiconductor industry is a technique of stacking at least two or more semiconductor chips to double the memory capacity. According to such a stacking technology, two 64M DRAM chips can be stacked to form a 128M DRAM class, and two 128M DRAM chips can be stacked to be 256M DRAM class. In addition, the stacking technique has advantages in terms of mounting density and efficiency of mounting area use.
상기 2개의 반도체 칩을 스택하는 방법으로는 스택된 2개의 칩을 하나의 패키지 내에 내장시키는 방법과 패키징된 2개의 패키지를 스택하는 방법이 있다.Stacking of the two semiconductor chips includes a method of embedding two stacked chips in one package and stacking two packaged packages.
여기서, 패키징된 2개의 패키지, 예컨데, 2개의 TSOP(Thin Small Outline Package)을 스택함에 있어서, 도시하지는 않았으나, 종래에는 바텀 패키지의 봉지제 외측으로 돌출된 아우터리드의 쇼울더(shoulder) 부위에 솔더 페이스트(solderpaste)를 디스펜싱(dispensing)한 후, 이러한 바텀 패키지 상에 탑 패키지를 배치시킨 상태로 리플로우(Reflow)를 행하여 바텀 패키지의 아우터리드와 탑 패키지의 아우터리드간을 상호 연결하며, 이를 통해, TSOP 스택 패키지를 구현한다.Here, in stacking two packaged packages, for example, two thin small outline packages (TSOPs), although not shown in the related art, a solder paste is formed on a shoulder portion of an outer projecting projecting outside the encapsulant of the bottom package. After dispensing (solderpaste), reflow is performed with the top package placed on the bottom package to interconnect the outer package of the bottom package and the outer package of the top package. It implements the TSOP stack package.
그러나, 종래의 TSOP 스택 패키지는 바텀 패키지의 아우터리드 쇼울더 부위가 평탄한 것과 관련해서 이러한 쇼율더 부위에 디스펜싱한 솔더 페이스가 흘러내리는 현상이 발생되며, 이로 인해, 바텀 패키지의 아우터리드와 탑 패키지의 아우터리드간에 안정적인 전기적 연결이 이루어지지 못하는 문제점이 있다.However, in the conventional TSOP stack package, the solder face dispensed to the shodder portion flows in connection with the flatness of the outer shoulder portion of the bottom package, and thus, the bottom package of the outer package and the top package of the bottom package occurs. There is a problem that a stable electrical connection between the outers is not made.
또한, 바텀 패키지 상에의 탑 패키지 안착시, 별다른 고정 수단이 없으므로 상기 탑 패키지의 안착이 용이하지 못한 문제점이 있다.In addition, when mounting the top package on the bottom package, there is no problem in that the mounting of the top package is not easy because there is no fixing means.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 솔더 페이스트의 흘러내림을 방지한 TSOP 스택 패키지를 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a TSOP stack package which is designed to solve the above problems and prevents the solder paste from flowing out.
또한, 본 발명은, 솔더 페이스트의 흘러내림을 방지하는 것을 통해 바텀 패키지의 아우터리드와 탑 패키지의 아우터리드간에 안정적인 전기적 연결이 이루어지도록 한 TSOP 스택 패키지를 제공함에 그 다른 목적이 있다.In addition, another object of the present invention is to provide a TSOP stack package which allows stable electrical connection between the outer package of the bottom package and the outer package of the top package by preventing the solder paste from flowing down.
게다가, 본 발명은, 바텀 패키지 상에의 탑 패키지 안착이 용이하도록 한 TSOP 스택 패키지를 제공함에 그 또 다른 다른 목적이 있다.In addition, it is another object of the present invention to provide a TSOP stack package that facilitates top package mounting on a bottom package.
도 1은 본 발명에 따른 TSOP 스택 패키지를 도시한 단면도.1 is a cross-sectional view illustrating a TSOP stack package according to the present invention.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 TSOP 스택 패키지 제작방법을 설명하기 위한 단면도.2A to 2C are cross-sectional views illustrating a method of manufacturing a TSOP stack package according to an embodiment of the present invention.
도 3은 본 발명의 다른 실시예에 따른 TSOP 스택 패키지를 도시한 단면도.3 is a cross-sectional view illustrating a TSOP stack package according to another embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1 : 반도체 칩 2 : 리드프레임1 semiconductor chip 2 leadframe
2a : 다이패들 2b : 인너리드2a: die paddle 2b: inner lead
2c : 아우터리드 3 : 접착제2c: outer3 3: adhesive
4 : 금속와이어 5 : 봉지제4: metal wire 5: sealing agent
10 : 바텀 패키지 12 : 솔더 페이스트10 bottom package 12 solder paste
20 : 탑 패키지 S : 쇼울더 부위20: top package S: shoulder portion
상기와 같은 목적을 달성하기 위하여, 본 발명은, 봉지제의 외측으로 돌출된 아우터리드를 소정 형상으로 포밍한 TSOP 구조 바텀 패키지의 상기 아우터리드 쇼울더(shoulder) 부위에 솔더 페이스트를 디스펜싱하고, 상기 바텀 패키지 상에 TSOP 구조의 탑 패키지를 안착시며, 상기 솔더 페이스트를 리플로우시켜 바텀 패키지의 아우터리드들과 탑 패키지의 아우터리드들을 전기적으로 상호 연결한 TSOP 스택 패키지에 있어서, 상기 바텀 패키지의 아우터리드는 쇼울더에 해당하는 부위가 솔더 페이스트의 흘러내림이 방지되도록 하프 식각된 것을 특징으로 하는 TSOP 스택 패키지를 제공한다.In order to achieve the above object, the present invention, the solder paste is dispensed to the outer shoulder portion of the TSOP structure bottom package formed by forming an outer projecting outwardly of the encapsulant into a predetermined shape, A TSOP stack package in which a TSOP structure top package is seated on a bottom package and the solder paste is reflowed to electrically interconnect the outer packages of the bottom package and the outer packages of the top package, the outer package of the bottom package. Provides a TSOP stack package, wherein the portion corresponding to the shoulder is half etched to prevent the solder paste from flowing down.
또한, 본 발명은, 봉지제의 외측으로 돌출된 아우터리드를 소정 형상으로 포밍한 TSOP 구조 바텀 패키지의 상기 아우터리드 쇼울더(shoulder) 부위에 솔더 페이스트를 디스펜싱하고, 상기 바텀 패키지 상에 TSOP 구조의 탑 패키지를 안착시며, 상기 솔더 페이스트를 리플로우시켜 바텀 패키지의 아우터리드들과 탑 패키지의 아우터리드들을 전기적으로 상호 연결한 TSOP 스택 패키지에 있어서, 상기 바텀 패키지의 아우터리드는 쇼울더에 해당하는 부위가 솔더 페이스트의 흘러내림이 방지되도록 홈 형상으로 포밍된 것을 특징으로 하는 TSOP 스택 패키지를 제공한다.In addition, the present invention, the solder paste is dispensed on the outer shoulder portion of the TSOP structure bottom package formed by forming an outer projecting outwardly of the encapsulant into a predetermined shape, the TSOP structure of the TSOP structure on the bottom package A TSOP stack package in which the top package is seated and the solder paste is reflowed to electrically interconnect the bottom packages 'outerts and the top packages' outerts, wherein the outer parts of the bottom package correspond to shoulders. The present invention provides a TSOP stack package, which is formed into a groove shape to prevent the solder paste from flowing down.
본 발명에 따르면, 바텀 패키지의 아우터리드 쇼율더 부위를 하프 식각하거나, 홈 형상으로 포밍해 줌으로써 솔더 페이스트의 흘러내림을 방지할 수 있음은 물론 탑 패키지의 안착을 용이하게 할 수 있다.According to the present invention, by half-etching or forming a grooved outer portion of the bottom package or forming a groove shape, it is possible to prevent the flow of the solder paste and also to easily mount the top package.
(실시예)(Example)
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명의 실시예에 따른 TSOP 스택 패키지를 도시한 단면도이다.1 is a cross-sectional view illustrating a TSOP stack package according to an embodiment of the present invention.
도시된 바와 같이, 본 발명의 TSOP 스택 패키지는 TSOP 구조를 갖는 바텀 패키지(10)와 탑 패키지(20)를 스택함에 있어서 상기 바텀 패키지(10)의 봉지제 외측으로 돌출된 아우터리드 쇼울더 부위(S)를 하프 식각(half etch)한 상태로 솔더 페이스트(12)를 디스펜싱하여 후속 리플로우 공정시에 상기 솔더 페이스트(12)의 흘러내림을 방지한 것을 그 구조적 특징으로 한다.As shown, the TSOP stack package of the present invention is an outer shoulder portion (S) protruding outside the encapsulant of the bottom package 10 in stacking the bottom package 10 and the top package 20 having a TSOP structure The solder paste 12 is dispensed with half etched to prevent the solder paste 12 from flowing down during a subsequent reflow process.
여기서, 상기 바텀 패키지(10) 쇼울더 부위(S)에의 하프 식각은 리드프레임 제작시나 트림(Trim) 공정시, 바람직하게는, 트림 공정시에 수행한다.Here, the half etching to the shoulder portion S of the bottom package 10 is performed at the time of manufacturing the lead frame or at the trim process, preferably at the trim process.
이와 같이 하면, 바텀 패키지(10) 상에 탑 패키지(20)를 안착시킨 후의 리플로우 공정에서 상기 바텀 패키지(10)의 쇼울더 부위(S)에 디스펜싱된 솔더 페이스트(12)의 흘러내림이 방지되며, 그래서, 바텀 패키지(10)의 아우터리드(2c)와 탑 패키지(20)의 아우터리드(2c)간에 안정적인 전기적 연결을 이룰 수 있다.This prevents the flow of the solder paste 12 dispensed in the shoulder portion S of the bottom package 10 in the reflow process after the top package 20 is seated on the bottom package 10. Thus, a stable electrical connection may be achieved between the outer 2c of the bottom package 10 and the outer 2c of the top package 20.
또한, 바텀 패키지(10) 상에의 탑 패키지(20) 안착시, 하프 식각된 쇼울더 부위(S)에 의해 상기 탑 패키지의 일차적인 안착을 이룰 수 있기 때문에 상기 탑 패키지(20)의 안착을 보다 용이하게 할 수 있다.In addition, when the top package 20 is seated on the bottom package 10, since the top package 20 may be primarily seated by the half-etched shoulder portion S, the top package 20 may be seated more. It can be done easily.
도 2a 내지 도 2c는 전술한 TSOP 스택 패키지 제조방법을 설명하기 위한 공정별 단면도로서, 이를 설명하면 다음과 같다.2A through 2C are cross-sectional views illustrating processes for manufacturing the aforementioned TSOP stack package, which will be described below.
도 2a를 참조하면, 다이패들(2a)과 인너리드(2b) 및 아우터리드(2c)로 구분되는 리드프레임(2)과 공지의 반도체 제조공정에 따라 제조된 반도체 칩(1)을 마련한다. 상기 리드프레임(2)은 유니트(unit) 단위가 아닌 스트라이프(stripe) 단위로 제작한다.Referring to FIG. 2A, a lead frame 2 divided into a die paddle 2a, an inner lead 2b, and an outer lead 2c and a semiconductor chip 1 manufactured according to a known semiconductor manufacturing process are prepared. . The lead frame 2 is manufactured in stripe units rather than unit units.
그 다음, 상기 반도체 칩(1)을 LOC 테이프 또는 에폭시와 같은 접착제(3)를 이용해서 상기 리드프레임(2)의 다이패들(2a) 상에 부착한다. 그런다음, 상기 반도체 칩(1)의 본딩패드(도시안됨)와 리드프레임(2)의 인너리드(2a)를 와이어 본딩 공정에 따라 금속와이어(4)로 상호 연결한다.The semiconductor chip 1 is then attached onto the die paddle 2a of the leadframe 2 using an adhesive 3 such as LOC tape or epoxy. Then, the bonding pad (not shown) of the semiconductor chip 1 and the inner lead 2a of the lead frame 2 are interconnected with the metal wire 4 according to a wire bonding process.
이어서, 외부 충격으로부터 칩을 보호하기 위해 상기 반도체 칩(1) 및 이에 와이어 본딩된 리드프레임(2)의 인너리드(2b)를 포함한 공간적 영역을 EMC(Epoxy Molding Compound)와 같은 봉지제(5)로 밀봉한다.Subsequently, the encapsulant 5 such as EMC (Epoxy Molding Compound) is formed in the spatial region including the inner lead 2b of the semiconductor chip 1 and the lead frame 2 wire-bonded thereto to protect the chip from external impact. Seal with.
그리고나서, 트림(Trim) 공정으로 스트라이프 상태의 리드프레임(2)으로부터 각각의 리드들을 분리해준 후, 분리된 리드, 즉, 아우터리드(2c) 부분을 소정 형상으로의 포밍/싱귤레이션(Forming/Singulation)을 행하여 TSOP 구조를 갖는 바텀 패키지(10)와 탑 패키지(20)를 제작한다.Then, each lead is separated from the lead frame 2 in a stripe state by a trim process, and then the separated lead, that is, the portion of the outer 2c, is formed into a predetermined shape. Singulation is performed to fabricate the bottom package 10 and top package 20 having a TSOP structure.
이때, 상기 바텀 패키지(10)는, 예컨데, 트림 공정시 봉지제(5)의 외측으로 돌출된 아우터리드(2c)의 쇼울더 부위(S)를 하프 식각(half etching)해 준다. 또한, 상기 탑 패키지(20)는 그의 아우터리드 끝단이 바텀 패키지(10)의 아우터리드 쇼울더 부위(S)와 접할 수 있도록 포밍한다.In this case, the bottom package 10 may half-etch the shoulder portion S of the outer lid 2c protruding to the outside of the encapsulant 5 during the trimming process. In addition, the top package 20 is formed so that its outer end may be in contact with the outer shoulder portion S of the bottom package 10.
도 2b를 참조하면, 바텀 패키지(10)의 하프 식각된 쇼울더 부위(S)에 솔더 페이스트(12)를 디스펜싱한다.Referring to FIG. 2B, the solder paste 12 is dispensed into the half-etched shoulder portion S of the bottom package 10.
도 2c를 참조하면, 바텀 패키지(10) 상에 탑 패키지(20)을 대응하는 아우터리드들(2c)이 솔더 페이스트(12)의 개재하에 상호 접하도록 안착시킨다. 이때, 상기 탑 패키지(20)의 안착은 상기 바텀 패키지(10)의 하드 식각된 아우터리드 쇼울더 부위(S)를 이용해서 1차적으로 행한다.Referring to FIG. 2C, the top package 20 is seated on the bottom package 10 such that the corresponding outlets 2c are in contact with each other under the interposition of the solder paste 12. At this time, the mounting of the top package 20 is primarily performed using the hard-etched outer shoulder portion S of the bottom package 10.
그 다음, 솔더 페이스트(12)에 대한 리플로우를 수행하고, 이를 통해, 바텀 패키지(10)와 탑 패키지(20)의 대응하는 아우터리드들(2c)간을 전기적으로 상호 연결시킴과 동시에 바텀 패키지(10) 상에의 탑 패키지(20)의 완전한 안착을 이루며, 이 결과로서, 본 발명에 따른 TSOP 스택 패키지를 완성한다.Then, a reflow of the solder paste 12 is performed, thereby electrically interconnecting the bottom packages 10 and the corresponding outliers 2c of the top package 20 while simultaneously bottoming the packages. Complete settling of the top package 20 on (10) results in completing the TSOP stack package according to the present invention.
도 3은 본 발명의 다른 실시예에 따른 TSOP 스택 패키지를 도시한 단면도이다.3 is a cross-sectional view illustrating a TSOP stack package according to another embodiment of the present invention.
도시된 바와 같이, 이 실시예에 따른 TSOP 스택 패키지는 이전 실시예의 그것과 비교해서 바텀 패키지(10)의 아우터리드 쇼울더 부위(S)가 하프 식각됨이 없이 홈 형상을 갖도록 포밍된다.As shown, the TSOP stack package according to this embodiment is formed so that the outer shoulder portion S of the bottom package 10 has a groove shape as compared with that of the previous embodiment, without being half etched.
이 경우에도 마찬가지로 상기 쇼울더 부위(S)에 디스펜싱된 솔더 페이스트의 흘러내림은 방지되며, 그래서, 바텀 패키지(10)와 탑 패키지(20)의 아우터리드들간 전기적 연결을 안정적으로 이룰 수 있으며, 또한, 상기 바텀 패키지(10) 상에의 탑 패키지(20) 안착을 용이하게 할 수 있다.In this case as well, the flow of the solder paste dispensed in the shoulder portion S is prevented, so that the electrical connection between the outer packages of the bottom package 10 and the top package 20 can be stably established. The top package 20 may be easily seated on the bottom package 10.
이상에서와 같이, 본 발명은 바텀 패키지의 아우터리드 쇼율더 부위를 하프 식각하거나 홈 형상을 갖도록 포밍해 줌으로써 상기 쇼울더 부위에 디스펜싱된 솔더 페이스트의 흘러내림을 방지할 수 있으며, 이에 따라, 바텀 패키지 리드와 탑 패키지 리드간의 안정적인 전기적 연결을 이룰 수 있다.As described above, the present invention can prevent the solder paste dispensed in the shoulder portion from flowing down by forming the outer showr portion of the bottom package to have a half-etched or grooved shape, and thus, the bottom package. A stable electrical connection between the leads and the top package leads can be achieved.
또한, 바텀 패키지의 아우터리드 쇼율더 부위를 하프 식각하거나 홈 형상을갖도록 포밍해 줌으로써 이러한 바텀 패키지 상에의 탑 패키지 안착을 용이하게 할 수 있다.In addition, it is possible to facilitate mounting of the top package on the bottom package by half etching or forming a groove shape of the outer showr portion of the bottom package.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030047741A KR20050008056A (en) | 2003-07-14 | 2003-07-14 | TSOP stack package |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030047741A KR20050008056A (en) | 2003-07-14 | 2003-07-14 | TSOP stack package |
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| Publication Number | Publication Date |
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| KR20050008056A true KR20050008056A (en) | 2005-01-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1020030047741A KR20050008056A (en) | 2003-07-14 | 2003-07-14 | TSOP stack package |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100772098B1 (en) * | 2005-06-21 | 2007-11-01 | 주식회사 하이닉스반도체 | Stack type package |
| KR100825780B1 (en) * | 2006-09-29 | 2008-04-29 | 삼성전자주식회사 | Manufacturing method of leadframe type stack package using laser soldering |
-
2003
- 2003-07-14 KR KR1020030047741A patent/KR20050008056A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100772098B1 (en) * | 2005-06-21 | 2007-11-01 | 주식회사 하이닉스반도체 | Stack type package |
| KR100825780B1 (en) * | 2006-09-29 | 2008-04-29 | 삼성전자주식회사 | Manufacturing method of leadframe type stack package using laser soldering |
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