TWI435421B - Semiconductor package structure - Google Patents

Semiconductor package structure Download PDF

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Publication number
TWI435421B
TWI435421B TW101113483A TW101113483A TWI435421B TW I435421 B TWI435421 B TW I435421B TW 101113483 A TW101113483 A TW 101113483A TW 101113483 A TW101113483 A TW 101113483A TW I435421 B TWI435421 B TW I435421B
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Taiwan
Prior art keywords
wafer
lead frame
body portion
package structure
semiconductor package
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TW101113483A
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Chinese (zh)
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TW201344854A (en
Inventor
Chin Tien Yen
Ting Feng Su
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Powertech Technology Inc
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Priority to TW101113483A priority Critical patent/TWI435421B/en
Publication of TW201344854A publication Critical patent/TW201344854A/en
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Publication of TWI435421B publication Critical patent/TWI435421B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

半導體封裝結構Semiconductor package structure

本發明是有關於一種封裝結構，且特別是有關於一種半導體封裝結構。This invention relates to a package structure, and more particularly to a semiconductor package structure.

在現今資訊爆炸的時代，積體電路已與日常生活有密不可分的關係，無論在食衣住行育樂方面，都常會用到積體電路元件所組成之產品。隨著電子科技的不斷演進，更人性化、功能性更複雜之電子產品不斷推陳佈新，然而各種產品無不朝向輕、薄、短、小的趨勢設計，以提供更便利舒適的使用。In today's era of information explosion, integrated circuits have been inextricably linked to daily life, and products such as integrated circuit components are often used in food and clothing. With the continuous evolution of electronic technology, more humanized and more complex electronic products are constantly being introduced. However, various products are designed to be light, thin, short and small, in order to provide more convenient and comfortable use.

對一般的半導體記憶體而言，如動態隨機存取記憶體(Dynamic Random Access Memory，DRAM)，其晶片所使用之封裝的方式，目前主要有小型J型外引腳封裝(Small Outline J-Lead，SOJ)，與小型外引腳封裝(Thin Small Outline Package，TSOP)兩種。For general semiconductor memory, such as Dynamic Random Access Memory (DRAM), the way in which the chip is packaged is mainly a small J-type external lead package (Small Outline J-Lead). , SOJ), and the Thin Small Outline Package (TSOP).

然而，在小型J型外引腳封裝或小型外引腳封裝中，就導線架(lead frame)而言，又可區分為晶片上有導腳封裝(Lead On Chip，LOC)，主要做為動態隨機存取記憶體之封裝結構，其優點為傳輸速度快、散熱佳、以及結構小。圖1為習知之小型外引腳封裝架構剖面示意圖。如圖1所示，以習知晶片上有導腳封裝為例，其中晶片108係利用黏著層110固定於導腳109下，再覆蓋以封裝膠體(Epoxy Mold Compound，EMC)，具有上膠體106及下膠體102，以封裝成型。上膠體106具有厚度116，而下膠體102具有厚度114，而厚度116與厚度114之比例為1：3，封裝後會因上下膠體的厚度及體積不同，因此上膠體106與下膠體102在冷凝時收縮量亦不同，而導致整個封裝構件產生扭曲變形(warpage)。However, in a small J-type external lead package or a small external lead package, in terms of a lead frame, it can be divided into a lead on chip (LOC) on the wafer, mainly as a dynamic The package structure of the random access memory has the advantages of high transmission speed, good heat dissipation, and small structure. 1 is a schematic cross-sectional view of a conventional small outer lead package structure. As shown in FIG. 1 , a conventional lead package on a wafer is exemplified, wherein the wafer 108 is fixed under the lead 109 by an adhesive layer 110 and covered with an epoxy (Epoxy Mold Compound, EMC) having an upper colloid 106. And the lower colloid 102 is formed by packaging. The upper colloid 106 has a thickness 116, and the lower colloid 102 has a thickness 114, and the ratio of the thickness 116 to the thickness 114 is 1:3. After the package, the thickness and volume of the upper and lower colloids are different, so the upper colloid 106 and the lower colloid 102 are condensed. The amount of shrinkage also varies, resulting in warpage of the entire package member.

本發明提供一種半導體封裝結構，可防止封裝膠體在冷凝時因上下膠體收縮量不同而造成封裝結構扭曲變形。The invention provides a semiconductor package structure, which can prevent the package structure from being twisted and deformed due to different amounts of shrinkage of the upper and lower colloids during condensation.

本發明提出一種半導體封裝結構，包括一導線架、至少一晶片及一封裝膠體。晶片設置於導線架上並與導線架電性連接，其中導線架具有最遠離晶片之一第一表面，而晶片具有最遠離導線架之一第二表面。封裝膠體包覆晶片及部分導線架，其中導線架的第一表面與晶片的第二表面定義出一中心平面，封裝膠體以中心平面為界區分為一第一上膠體部及一第一下膠體部，且第一上膠體部與第一下膠體部的體積比值介於0.8至1.2之間，中心平面平行於第一表面及第二表面，且第一表面至第二表面的最短距離的中心點位於中心平面上。The invention provides a semiconductor package structure comprising a lead frame, at least one wafer and an encapsulant. The wafer is disposed on the lead frame and electrically connected to the lead frame, wherein the lead frame has a first surface farthest from the wafer, and the wafer has a second surface farthest from the lead frame. The encapsulating colloid covers the wafer and the partial lead frame, wherein the first surface of the lead frame defines a center plane with the second surface of the wafer, and the encapsulant is divided into a first upper colloid portion and a first lower colloid by a central plane And a volume ratio of the first upper body portion to the first lower body portion is between 0.8 and 1.2, the center plane is parallel to the first surface and the second surface, and the center of the shortest distance from the first surface to the second surface The point is on the center plane.

在本發明之一實施例中，上述之導線架包括一晶片座以及多個環繞晶片座的引腳，晶片配置於晶片座上，而各引腳區分為一內引腳部以及一外引腳部，封裝膠體包覆晶片、晶片座以及內引腳部，且暴露出外引腳部。In an embodiment of the invention, the lead frame includes a wafer holder and a plurality of pins surrounding the wafer holder. The wafer is disposed on the wafer holder, and the pins are divided into an inner lead portion and an outer lead. The encapsulant encapsulates the wafer, the wafer holder, and the inner lead portion, and exposes the outer lead portion.

在本發明之一實施例中，上述之半導體封裝結構更包括一黏著層，配置於晶片與導線架之晶片座之間，用以黏著晶片及導線架。In one embodiment of the invention, the semiconductor package structure further includes an adhesive layer disposed between the wafer and the wafer holder of the lead frame for bonding the wafer and the lead frame.

在本發明之一實施例中，上述之各外引腳部具有平行中心平面的一第一延伸部與一第二延伸部以及垂直封裝膠體之側壁的一第三延伸部，第三延伸部位於第一延伸部與第二延伸部之間，且第一延伸部連接封裝膠體。In an embodiment of the invention, each of the outer lead portions has a first extension portion and a second extension portion parallel to the central plane and a third extension portion of the sidewall of the vertical encapsulant, and the third extension portion is located The first extension portion and the second extension portion are connected to each other, and the first extension portion is connected to the encapsulant.

在本發明之一實施例中，上述之外引腳部的第一延伸部高於中心平面，而晶片配置於導線架的下方，且第一延伸部定義出一參考平面，以將封裝膠體區分為一第二上膠體部以及一第二下膠體部，第二上膠體部與第二下膠體部的體積比為1：2.25。In an embodiment of the invention, the first extension of the outer lead portion is higher than the center plane, and the wafer is disposed under the lead frame, and the first extension defines a reference plane to distinguish the encapsulation colloid For a second upper body portion and a second lower body portion, the volume ratio of the second upper body portion to the second lower body portion is 1:2.25.

在本發明之一實施例中，上述之導線架為一上凹式導線架。In an embodiment of the invention, the lead frame is a recessed lead frame.

在本發明之一實施例中，上述之外引腳部的第一延伸部對齊中心平面，而晶片配置於導線架的上方，且第一延伸部定義出一參考平面，以將封裝膠體區分為一第三上膠體部以及一第三下膠體部，第三上膠體部與第三下膠體部的體積比為1：1。In an embodiment of the invention, the first extension of the outer lead portion is aligned with the center plane, and the wafer is disposed above the lead frame, and the first extension defines a reference plane to distinguish the encapsulant into a third upper body portion and a third lower body portion, and the volume ratio of the third upper body portion to the third lower body portion is 1:1.

在本發明之一實施例中，上述之導線架為一下凹式導線架。In an embodiment of the invention, the lead frame is a recessed lead frame.

在本發明之一實施例中，上述之晶片之數量為多個晶片，晶片彼此交錯堆疊於導線架上，且最遠離導線架的晶片具有第二表面。In one embodiment of the invention, the number of wafers described above is a plurality of wafers, the wafers are interleaved with each other on the leadframe, and the wafer furthest from the leadframe has a second surface.

在本發明之一實施例中，上述之半導體封裝結構更包括至少一銲線，連接於晶片與導線架之間，其中晶片透過銲線與導線架電性連接，而封裝膠體包覆銲線。In one embodiment of the invention, the semiconductor package structure further includes at least one bonding wire connected between the wafer and the lead frame, wherein the wafer is electrically connected to the lead frame through the bonding wire, and the encapsulant covers the bonding wire.

在本發明之一實施例中，上述之各晶片的表面積至少大於140mm2 。In one embodiment of the invention, each of the wafers described above has a surface area of at least greater than 140 mm 2 .

基於上述，本發明利用導線架最遠離晶片之第一表面，以及晶片最遠離導線架之第二表面定義出一中心平面，封裝膠體以中心平面為界，區分為上膠體部及下膠體部，且上膠體部及下膠體部的體積比介於0.8至1.2之間，使上膠體部與下膠體部之體積比例平衡，在冷凝時收縮量相似，故可防止半導體封裝結構之扭曲變形。因此，本發明可確實提升半導體封裝結構之封裝良率。Based on the above, the present invention utilizes a first surface of the lead frame farthest from the wafer, and a second plane defined by the second surface of the wafer farthest from the lead frame. The encapsulant is divided into a top body portion and a lower gel portion by a center plane. Moreover, the volume ratio of the upper colloid portion and the lower colloid portion is between 0.8 and 1.2, so that the volume ratio of the upper colloid portion to the lower colloid portion is balanced, and the amount of shrinkage is similar when condensed, so that distortion of the semiconductor package structure can be prevented. Therefore, the present invention can surely improve the package yield of the semiconductor package structure.

為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.

圖2為本發明一實施例之半導體封裝結構之剖面示意圖。請參考圖2，在本實施例中，半導體封裝結構100包括一導線架110、至少一晶片120及一封裝膠體130。晶片120設置於導線架110上並與導線架110電性連接。晶片120可為動態隨機存取記憶體(DRAM)、唯讀記憶體(ROM)、靜態隨機存取記憶體(SRAM)、快閃記憶體(flash memory)、邏輯電路晶片(LOPIC)或類比晶片(ANALOG)等各種積體電路晶片。其中，導線架110具有最遠離晶片120之一第一表面112，而晶片120具有最遠離導線架110之一第二表面122。在本實施例中，晶片120的數量為兩個，在本發明之其他實施例中，晶片120的數量可為多個，例如：兩個、四個或六個，彼此交錯堆疊於導線架110上，且最遠離導線架110的晶片120具有第二表面122。2 is a cross-sectional view showing a semiconductor package structure according to an embodiment of the present invention. Referring to FIG. 2 , in the embodiment, the semiconductor package structure 100 includes a lead frame 110 , at least one wafer 120 , and an encapsulant 130 . The wafer 120 is disposed on the lead frame 110 and electrically connected to the lead frame 110. The wafer 120 can be a dynamic random access memory (DRAM), a read only memory (ROM), a static random access memory (SRAM), a flash memory, a logic chip (LOPIC) or an analog wafer. Various integrated circuit chips such as (ANALOG). Wherein, the leadframe 110 has a first surface 112 that is furthest from the wafer 120, and the wafer 120 has a second surface 122 that is furthest from the leadframe 110. In the present embodiment, the number of the wafers 120 is two. In other embodiments of the present invention, the number of the wafers 120 may be plural, for example, two, four or six, which are alternately stacked on the lead frame 110. The wafer 120, which is the uppermost and farthest from the leadframe 110, has a second surface 122.

承上述，封裝膠體130包覆晶片120及部分導線架110，其中導線架110的第一表面112與晶片120的第二表面122定義出一中心平面CP。其中，中心平面CP平行於第一表面112及第二表面122，且第一表面112至第二表面122的最短距離D的中心點位於中心平面CP上。封裝膠體130以中心平面CP為界，區分為一第一上膠體部132及一第一下膠體部134，且第一上膠體部132與第一下膠體部134的體積比值介於0.8至1.2之間。封裝膠體130的材料可為環氧樹脂(epoxy)等絕緣材質，而第一上膠體部132與第一下膠體部134的體積比值介於0.8至1.2之間可使其在冷凝時收縮量相似，而防止半導體封裝結構100於冷凝的過程中扭曲變形。需說明的是，在本實施例中，封裝膠體130的中心線CL(即封裝膠體130之上表面131與下表面133所定義出的中心線CL)不等於在此所定義之中心平面CP，如圖2所示中心線CL高於中心平面CP。In the above, the encapsulant 130 covers the wafer 120 and a portion of the lead frame 110, wherein the first surface 112 of the lead frame 110 and the second surface 122 of the wafer 120 define a center plane CP. The central plane CP is parallel to the first surface 112 and the second surface 122, and the center point of the shortest distance D of the first surface 112 to the second surface 122 is located on the central plane CP. The encapsulant 130 is divided into a first upper body portion 132 and a first lower body portion 134 by a center plane CP, and the volume ratio of the first upper body portion 132 to the first lower body portion 134 is 0.8 to 1.2. between. The material of the encapsulant 130 may be an insulating material such as epoxy, and the volume ratio of the first upper body portion 132 to the first lower body portion 134 is between 0.8 and 1.2, so that the shrinkage amount is similar when condensing. And preventing the semiconductor package structure 100 from being distorted during condensation. It should be noted that, in this embodiment, the center line CL of the encapsulant 130 (ie, the center line CL defined by the upper surface 131 and the lower surface 133 of the encapsulant 130) is not equal to the center plane CP defined herein. The center line CL is higher than the center plane CP as shown in FIG.

詳細而言，導線架110包括一晶片座114及多個環繞晶片座114的引腳116。晶片120配置於晶片座114上，而各引腳116區分為一內引腳部116a以及一外引腳部116b，封裝膠體130則包覆晶片120、晶片座114及內引腳部116a，且暴露出外引腳部116b，使半導體封裝結構100可透過外引腳部116b與其他電子元件電性連接。半導體封裝結構100更包括至少一銲線150及一黏著層140，銲線150連接於晶片120與導線架110之間，而晶片120即透過銲線150與導線架110電性連接，且封裝膠體130包覆銲線150。其中，銲線150可為金線、鋁線或其他金屬線。黏著層140配置於晶片120與導線架110之晶片座114之間，用以黏著晶片120及導線架110。值得注意的是，在各晶片120的表面積至少大於140mm2 的條件下，晶片120之間及晶片120與導線架110之間具有較好的表面結合度。In detail, the leadframe 110 includes a wafer holder 114 and a plurality of pins 116 surrounding the wafer holder 114. The chip 120 is disposed on the wafer holder 114, and each of the pins 116 is divided into an inner lead portion 116a and an outer lead portion 116b. The encapsulant 130 covers the wafer 120, the wafer holder 114 and the inner lead portion 116a, and The outer lead portion 116b is exposed to electrically connect the semiconductor package structure 100 to other electronic components through the outer lead portion 116b. The semiconductor package structure 100 further includes at least one bonding wire 150 and an adhesive layer 140. The bonding wire 150 is connected between the wafer 120 and the lead frame 110, and the wafer 120 is electrically connected to the lead frame 110 through the bonding wire 150, and the encapsulant is encapsulated. 130 is coated with a bonding wire 150. The bonding wire 150 may be a gold wire, an aluminum wire or other metal wires. The adhesive layer 140 is disposed between the wafer 120 and the wafer holder 114 of the lead frame 110 for bonding the wafer 120 and the lead frame 110. It should be noted that, under the condition that the surface area of each wafer 120 is at least greater than 140 mm 2 , there is good surface bonding between the wafers 120 and between the wafers 120 and the lead frame 110.

圖3為本發明另一實施例之半導體封裝結構之剖面示意圖。請參考圖3，實際而言，各外引腳116b部具有平行中心平面CP的一第一延伸部162與一第二延伸部164以及平行封裝膠體130之側壁的一第三延伸部166，第三延伸部166位於第一延伸部162與第二延伸部164之間並連接第一延伸部162與第二延伸部164，且第一延伸部162連接封裝膠體130。在本實施例之半導體封裝結構300中，導線架310為一上凹式導線架，意即，外引腳部116b的第一延伸部162高於中心平面CP，而晶片120配置於導線架310的下方，且第一延伸部162定義出一參考平面RP，以將封裝膠體130區分為一第二上膠體部172以及一第二下膠體部174，第二上膠體部172與第二下膠體部174的體積比為1：2.25。3 is a cross-sectional view showing a semiconductor package structure according to another embodiment of the present invention. Referring to FIG. 3 , in actuality, each outer lead 116b has a first extension 162 and a second extension 164 parallel to the central plane CP and a third extension 166 of the sidewall of the parallel encapsulation 130. The three extensions 166 are located between the first extension 162 and the second extension 164 and connect the first extension 162 and the second extension 164 , and the first extension 162 is connected to the encapsulant 130 . In the semiconductor package structure 300 of the present embodiment, the lead frame 310 is a recessed lead frame, that is, the first extension portion 162 of the outer lead portion 116b is higher than the center plane CP, and the wafer 120 is disposed on the lead frame 310. The second extension portion 162 defines a reference plane RP to distinguish the encapsulant 130 into a second upper body portion 172 and a second lower body portion 174, and the second upper body portion 172 and the second lower colloid portion. The volume ratio of the portion 174 is 1:2.25.

圖4為本發明另一實施例之半導體封裝結構之剖面示意圖。請參考圖4，在本發明之另一實施例之半導體封裝結構400中，導線架410為一下凹式導線架，意即，外引腳部116b的第一延伸部162對齊中心平面CP，而晶片120配置於導線架410的上方，且第一延伸部162定義出一參考平面RP，以將封裝膠體130區分為一第三上膠體部176以及一第三下膠體部178，第三上膠體部與該第三下膠體部的體積比為1：1。由於本實施例之第一延伸部162對齊中心平面CP，故參考平面RP對齊於中心平面CP，而第三上膠體部176與第三下膠體部178的體積比亦近似於第一上膠體部132與第三下膠體部134的體積比。4 is a cross-sectional view showing a semiconductor package structure according to another embodiment of the present invention. Referring to FIG. 4, in the semiconductor package structure 400 of another embodiment of the present invention, the lead frame 410 is a recessed lead frame, that is, the first extension portion 162 of the outer lead portion 116b is aligned with the center plane CP, and The wafer 120 is disposed above the lead frame 410, and the first extending portion 162 defines a reference plane RP to divide the encapsulant 130 into a third upper body portion 176 and a third lower body portion 178. The third upper colloid is formed. The volume ratio of the portion to the third lower body portion is 1:1. Since the first extension portion 162 of the embodiment is aligned with the center plane CP, the reference plane RP is aligned with the center plane CP, and the volume ratio of the third upper body portion 176 to the third lower body portion 178 is also similar to the first upper body portion. The volume ratio of 132 to the third lower body portion 134.

如此配置，以中心平面CP將封裝膠體130區分為體積相似的第一上膠體部132及第一下膠體部134，使本發明之半導體封裝結構100、300、400可適用於一般的導線架110、上凹式導線架310及下凹式導線架410，而不會因導線架的型式不同而改變上膠體部132及下膠體部134的體積比值，造成其在冷凝的過程中因上膠體部132及下膠體部134的收縮量不等而導致半導體封裝結構100、300、400的扭曲變形。So, the package body 130 is divided into the first upper body portion 132 and the first lower body portion 134 having a similar volume by the center plane CP, so that the semiconductor package structure 100, 300, 400 of the present invention can be applied to the general lead frame 110. The concave lead frame 310 and the recessed lead frame 410 are not changed by the type of the lead frame, and the volume ratio of the upper body portion 132 and the lower body portion 134 is changed, so that the upper colloid portion is in the process of condensation. The amount of shrinkage of the 132 and the lower body portion 134 is unequal, resulting in distortion of the semiconductor package structures 100, 300, 400.

綜上所述，本發明利用導線架最遠離晶片之第一表面，以及晶片最遠離導線架之第二表面定義出一中心平面，封裝膠體以此中心平面為界，區分為上膠體部及下膠體部，且上膠體部及下膠體部的體積比介於0.8至1.2之間，使上膠體部與下膠體部在冷凝時收縮量相似，故可防止半導體封裝結構之扭曲變形。因此，本發明可確實提升半導體封裝結構之封裝良率。In summary, the present invention utilizes a lead frame that is furthest from the first surface of the wafer, and a second plane defined by the second surface of the wafer farthest from the lead frame. The encapsulant is defined by the center plane as the upper colloid portion and the lower portion. In the colloid portion, and the volume ratio of the upper colloid portion and the lower colloid portion is between 0.8 and 1.2, the amount of shrinkage of the upper colloid portion and the lower colloid portion is similar when condensed, so that distortion of the semiconductor package structure can be prevented. Therefore, the present invention can surely improve the package yield of the semiconductor package structure.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100、300、400．．．半導體封裝結構100, 300, 400. . . Semiconductor package structure

110、310、410．．．導線架110, 310, 410. . . Lead frame

112．．．第一表面112. . . First surface

114．．．晶片座114. . . Wafer holder

116．．．引腳116. . . Pin

116a．．．內引腳部116a. . . Inner pin

116b．．．外引腳部116b. . . Outer pin

120．．．晶片120. . . Wafer

122．．．第二表面122. . . Second surface

130．．．封裝膠體130. . . Encapsulant

131．．．上表面131. . . Upper surface

132．．．第一上膠體部132. . . First upper body

133．．．下表面133. . . lower surface

134．．．第一下膠體部134. . . First lower body part

140．．．黏著層140. . . Adhesive layer

150．．．銲線150. . . Welding wire

162．．．第一延伸部162. . . First extension

164．．．第二延伸部164. . . Second extension

166．．．第三延伸部166. . . Third extension

172．．．第二上膠體部172. . . Second upper body

174．．．第二下膠體部174. . . Second lower body part

176．．．第三上膠體部176. . . Third upper body

178．．．第三下膠體部178. . . Third sub-colloid

CP．．．中心平面CP. . . Center plane

CL．．．中心線CL. . . Center line

D．．．最短距離D. . . Shortest distance

RP．．．參考平面RP. . . Reference plane

圖1為習知之小型外引腳封裝架構剖面示意圖。1 is a schematic cross-sectional view of a conventional small outer lead package structure.

圖2為本發明一實施例之半導體封裝結構之剖面示意圖。2 is a cross-sectional view showing a semiconductor package structure according to an embodiment of the present invention.

圖3為本發明另一實施例之半導體封裝結構之剖面示意圖。3 is a cross-sectional view showing a semiconductor package structure according to another embodiment of the present invention.

圖4為本發明另一實施例之半導體封裝結構之剖面示意圖。4 is a cross-sectional view showing a semiconductor package structure according to another embodiment of the present invention.

100．．．半導體封裝結構100. . . Semiconductor package structure

110．．．導線架110. . . Lead frame

112．．．第一表面112. . . First surface

114．．．晶片座114. . . Wafer holder

116．．．引腳116. . . Pin

116a．．．內引腳部116a. . . Inner pin

116b．．．外引腳部116b. . . Outer pin

120．．．晶片120. . . Wafer

122．．．第二表面122. . . Second surface

130．．．封裝膠體130. . . Encapsulant

131．．．上表面131. . . Upper surface

132．．．第一上膠體部132. . . First upper body

133．．．下表面133. . . lower surface

134．．．第一下膠體部134. . . First lower body part

140．．．黏著層140. . . Adhesive layer

150．．．銲線150. . . Welding wire

CP．．．中心平面CP. . . Center plane

CL．．．中心線CL. . . Center line

D．．．最短距離D. . . Shortest distance

Claims (11)

一種半導體封裝結構，包括：一導線架；至少一晶片，設置於該導線架上並與該導線架電性連接，其中該導線架具有最遠離該晶片之一第一表面，而該晶片具有最遠離該導線架之一第二表面；以及一封裝膠體，包覆該晶片及部分該導線架，其中該導線架的該第一表面與該晶片的該第二表面定義出一中心平面，該封裝膠體以該中心平面為界區分為一第一上膠體部及一第一下膠體部，且該第一上膠體部與該第一下膠體部的體積比值介於0.8至1.2之間，該中心平面平行於該第一表面及該第二表面，且該第一表面至該第二表面的最短距離的中心點位於該中心平面上。A semiconductor package structure comprising: a lead frame; at least one wafer disposed on the lead frame and electrically connected to the lead frame, wherein the lead frame has a first surface farthest from the wafer, and the wafer has the most a second surface away from the one of the lead frames; and an encapsulant covering the wafer and a portion of the lead frame, wherein the first surface of the lead frame defines a center plane with the second surface of the wafer, the package The colloid is divided into a first upper body portion and a first lower body portion by the center plane, and the volume ratio of the first upper body portion to the first lower body portion is between 0.8 and 1.2. The plane is parallel to the first surface and the second surface, and a center point of the shortest distance from the first surface to the second surface is located on the center plane. 如申請專利範圍第1項所述之半導體封裝結構，其中該導線架包括一晶片座以及多個環繞該晶片座的引腳，該晶片配置於該晶片座上，而各該引腳區分為一內引腳部以及一外引腳部，該封裝膠體包覆該晶片、該晶片座以及該些內引腳部，且暴露出該些外引腳部。The semiconductor package structure of claim 1, wherein the lead frame comprises a wafer holder and a plurality of pins surrounding the wafer holder, the wafer is disposed on the wafer holder, and each of the pins is divided into one The inner lead portion and the outer lead portion enclose the wafer, the wafer holder and the inner lead portions, and expose the outer lead portions. 如申請專利範圍第2項所述之半導體封裝結構，更包括一黏著層，配置於該晶片與該導線架之該晶片座之間，用以黏著該晶片及該導線架。The semiconductor package structure of claim 2, further comprising an adhesive layer disposed between the wafer and the wafer holder of the lead frame for bonding the wafer and the lead frame. 如申請專利範圍第2項所述之半導體封裝結構，其中各該外引腳部具有平行該中心平面的一第一延伸部與一第二延伸部以及平行該封裝膠體之側壁的一第三延伸部，該第三延伸部位於該第一延伸部與該第二延伸部之間，且該第一延伸部連接該封裝膠體。The semiconductor package structure of claim 2, wherein each of the outer lead portions has a first extension and a second extension parallel to the central plane and a third extension parallel to the sidewall of the encapsulant The third extension is located between the first extension and the second extension, and the first extension is connected to the encapsulant. 如申請專利範圍第4項所述之半導體封裝結構，其中該些外引腳部的該些第一延伸部高於該中心平面，而該晶片配置於該導線架的下方，且該些第一延伸部定義出一參考平面，以將該封裝膠體區分為一第二上膠體部以及一第二下膠體部，該第二上膠體部與該第二下膠體部的體積比為1：2.25。The semiconductor package structure of claim 4, wherein the first extensions of the outer lead portions are higher than the center plane, and the wafer is disposed under the lead frame, and the first The extension defines a reference plane to divide the encapsulant into a second upper body portion and a second lower body portion, and the volume ratio of the second upper body portion to the second lower body portion is 1: 2.25. 如申請專利範圍第5項所述之半導體封裝結構，其中該導線架為一上凹式導線架(upset leadframe)。The semiconductor package structure of claim 5, wherein the lead frame is an upset leadframe. 如申請專利範圍第4項所述之半導體封裝結構，其中該些外引腳部的該些第一延伸部對齊該中心平面，而該晶片配置於該導線架的上方，且該些第一延伸部定義出一參考平面，以將該封裝膠體區分為一第三上膠體部以及一第三下膠體部，該第三上膠體部與該第三下膠體部的體積比為1：1。The semiconductor package structure of claim 4, wherein the first extensions of the outer lead portions are aligned with the center plane, and the wafer is disposed above the lead frame, and the first extensions The portion defines a reference plane to divide the encapsulant into a third upper body portion and a third lower body portion, and the volume ratio of the third upper body portion to the third lower body portion is 1:1. 如申請專利範圍第7項所述之半導體封裝結構，其中該導線架為一下凹式導線架(downset leadframe)。The semiconductor package structure of claim 7, wherein the lead frame is a downset leadframe. 如申請專利範圍第1項所述之半導體封裝結構，其中該至少一晶片之數量為多個晶片，該些晶片彼此交錯堆疊於該導線架上，且最遠離該導線架的該晶片具有該第二表面。The semiconductor package structure of claim 1, wherein the at least one wafer is a plurality of wafers, the wafers are alternately stacked on the lead frame, and the wafer farthest from the lead frame has the first Two surfaces. 如申請專利範圍第1項所述之半導體封裝結構，更包括至少一銲線，連接於該晶片與該導線架之間，其中該晶片透過該銲線與該導線架電性連接，而該封裝膠體包覆該銲線。The semiconductor package structure of claim 1, further comprising at least one bonding wire connected between the wafer and the lead frame, wherein the wafer is electrically connected to the lead frame through the bonding wire, and the package is The gel coats the wire. 如申請專利範圍第1項所述之半導體封裝結構，其中各該晶片的表面積至少大於140mm2 。The semiconductor package structure of claim 1, wherein each of the wafers has a surface area of at least greater than 140 mm 2 .
TW101113483A 2012-04-16 2012-04-16 Semiconductor package structure TWI435421B (en)

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