KR20050006890A - Plasma display panel sustain driver for clamping surge voltage and method thereof - Google Patents

Abstract

PURPOSE: An apparatus and a method for driving a plasma display panel sustain to clamp surge voltage are provided to prevent the surge voltage from being applied to the semiconductor devices. CONSTITUTION: An apparatus for driving a plasma display panel sustain to clamp surge voltage includes a power recovery circuit(321), a switching circuit(341) and a clamping circuit(331). The power recovery circuit charges, sustains and discharges the plasma display panel during a predetermined time. The switching circuit supplies the current path flowing between the power recovery circuit and the plasma display panel. And, the clamping circuit clamps the surge voltage generated at the power recovery circuit.

Description

Plasma display panel sustain driver for clamping surge voltage and method

The present invention relates to a plasma display panel sustain driving apparatus and method, and more particularly, to a plasma display panel sustain driving apparatus and method for reducing voltage stress and clamping surge voltage.

In general, a plasma display panel (PDP) is a next-generation flat panel display device that displays characters or images by using plasma generated by gas discharge. In the plasma display panel, dozens or millions of pixels are matrixed according to their size. It is arranged in (matrix) form.

1 is a circuit diagram of conventional plasma display panel sustain driving apparatuses 101 and 102 connected to a plasma display panel 111. 1 is identical to the AC-PDP sustain discharge circuit proposed by Webber. Referring to FIG. 1, the plasma display sustain driving apparatuses 101 and 102 include MOS transistors Sa1Sa2, Sb1, and Sb2, diodes Da1, Da2, and Db1, Db2, and Dc1 to Dc4, and inductors Lc1 and Lc2. And switching elements Sx1, Sx2, Sy1, and Sy2, and capacitors Cc1 and Cc2.

In the case of the AC-PDP, the plasma display panel 111 may be assumed to be a load having a panel capacitance Cp.

FIG. 2 shows waveforms and timings of signals of the plasma display panel sustain driving apparatuses 101 and 102 shown in FIG. 1. That is, FIG. 2 shows control signals according to the switching sequence of the plasma display panel sustain driving devices 101 and 102, and currents flowing through the output voltage Vp and the inductors Lc1 and Lc2 of the plasma display panel 111. The waveform of IL2 is shown.

Referring to FIG. 2, the operation of the conventional plasma display panel sustain driving apparatus 101 will be described. The plasma display panel sustain driving apparatus 101 may be displayed in the first to fourth modes as follows according to the switching sequence.

Just before the MOS transistor Sa1 is turned on in the first mode, the MOS transistor Sx2 is turned on and the voltage Vp of both ends of the plasma display panel 111 is maintained at 0 [V]. The operation of the first mode is started when the MOS transistor Sa1 is turned on at t0. During this period, the LC resonant circuit is formed in the path of Cc1-Sa1-Da1-Lc1-Cp, so that the resonant current flows in the inductor Lc1 and the plasma display panel voltage Vp increases. At t1, the current of the inductor Lc1 becomes 0 [V] and the plasma display panel voltage Vp becomes + Vpk.

In the second mode, MOS transistor Sa1 is turned off at t1 and MOS transistor Sy1 is turned on. At this time, the voltage at both ends of the MOS transistor Sy1 has a step change by tpk from t1 to generate a switching loss. The plasma display panel voltage Vp is maintained at + Vs and the plasma display panel 111 maintains discharge during the second mode period.

In the third mode, the MOS transistor Sa2 is turned on and the MOS transistor Sy1 is turned off at t2. The LC resonant circuit is formed in the path of Cp-Lc1-Da2-Sa2-Cc1 during the third mode period, so that the resonant current flows in the inductor Lc1 and the plasma display panel voltage Vp decreases. At t3, the current of the inductor Lc2 is 0 [A] and the plasma display panel voltage Vp is -Vpk.

In the fourth mode, the MOS transistor Sa2 is turned off and the MOS transistor Sy2 is turned on at t3. At this time, since the voltage across both of the MOS transistors Sy2 is -Vpk at t3, switching loss occurs. The plasma display panel voltage Vp is maintained at 0 [V] during the fourth mode period. At t0, when the MOS transistor Sx2 is turned off and the MOS transistor Sb1 is turned on, the MOS transistor Sx2 is turned on for another half period.

Referring to the voltage stress of the conventional plasma display panel sustain driving apparatus 101 as described above, the voltage stress of the MOS transistors Sy1, Sy2, Sx1, and Sx2 is + Vs, and the MOS transistors Sa1, Sa2, Sb1, and Sb2. ), The voltage stress of + Vs / 2, and the voltage stress of the diodes Da1, Da2, Db1, Db2, Dc1 to Dc4 become + Vs / 2. Considering that the plasma display panel 111 operates at a voltage Vs in the range of 160 to 190 [V], the semiconductor devices included in the plasma display panel sustain driving apparatus 101 are not only expensive but also parasitic resistance. And parasitic capacitance increases, power consumption increases, switching losses increase during high frequency operation, and EMI and noise increase.

An object of the present invention is to provide a plasma display panel sustain driving apparatus for protecting a semiconductor device provided therein by reducing voltage stress and clamping an internal surge voltage.

1 is a circuit diagram of a conventional plasma display panel sustain driving apparatus connected to a plasma display panel.

FIG. 2 shows waveforms and timings of signals of the plasma display panel sustain driving devices shown in FIG. 1.

3 is a circuit diagram of a plasma display panel sustain driving apparatus according to a first embodiment of the present invention connected to a plasma display panel.

4 illustrates waveforms and timings of signals of the plasma display panel sustain driving apparatus shown in FIG. 3.

5A to 5H are circuit diagrams showing current paths in various modes according to a switching sequence of the plasma display panel sustain driving apparatus shown in FIG. 3 in bold lines.

6A through 6D are circuit diagrams showing paths of parasitic currents for clamping surge voltages generated in various modes according to the switching sequence of the plasma display panel sustain driving apparatus shown in FIG.

7 is a circuit diagram of a plasma display panel sustain driving apparatus according to a second embodiment of the present invention.

8 is a circuit diagram of a plasma display panel sustain driving apparatus according to a third embodiment of the present invention.

The present invention to achieve the above technical problem

An apparatus for driving a plasma display panel, comprising: a power recovery unit for charging, maintaining, and discharging the plasma display panel for a predetermined time, and a switching unit for providing a passage of current flowing between the power recovery unit and the plasma display panel; And a clamping part for clamping a surge voltage generated in the power recovery part.

Preferably, the plasma display panel sustain driving device is

First to fourth capacitors connected in series between a power supply voltage Vs and a ground voltage; First and second MOS transistors receiving (1/4) Vs from the fourth capacitor and connected in parallel with each other; First and second diodes connected to the first and second MOS transistors, respectively; A first inductor commonly connected to the first and second diodes; Third and fourth MOS transistors receiving (3/4) Vs from the third capacitor and connected in parallel to each other; Third and fourth diodes connected to the third and fourth MOS transistors, respectively; A second inductor commonly connected to the third and fourth diodes; Fifth and sixth diodes connected to the first and second inductors and supplied with (1/2) Vs from the second capacitor to an interconnection point; First to fourth clamping diodes connected to the first to fourth diodes, respectively, for clamping parasitic currents generated by the first to fourth diodes; And a plurality of MOS transistors connected between the first and second inductors and the plasma display panel, and switching the passage of current flowing therebetween.

Preferably, the plasma display panel sustain driving device is

First to fourth capacitors connected in series between a power supply voltage Vs and a ground voltage; First and second MOS transistors (1/4) Vs supplied from the fourth capacitor and connected in series with each other; First and second diodes connected in parallel to the first and second MOS transistors, respectively; A first inductor connected to the second MOS transistor; Third and fourth MOS transistors receiving (3/4) Vs from the third capacitor and connected in series with each other; Third and fourth diodes connected in parallel to the third and fourth MOS transistors, respectively; A second inductor connected to the fourth MOS transistor; Fifth and sixth diodes connected to the first and second inductors and supplied with (1/2) Vs from the second capacitor to an interconnection point; First to fourth clamping diodes connected to the first to fourth diodes, respectively, for clamping parasitic currents generated by the first to fourth diodes; And a plurality of MOS transistors connected between the first and second inductors and the plasma display panel, and switching the passage of current flowing therebetween.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram of the plasma display panel sustain driving apparatus 301 according to the first embodiment of the present invention connected to the plasma display panel 311. Referring to FIG. 3, the plasma display panel sustain driving device 301 includes a power recovery unit 321, a clamping unit 331, and a switching unit 341. The plasma display panel 311 is connected to the switching unit 341.

The power recovery unit 321 charges, maintains, and discharges the plasma display panel 311 for a predetermined time. That is, the power recovery unit 321 may include a first charging mode (pre-charging mode), a second charging mode (post-charging mode), and a first discharge corresponding to the power recovery sequence of the plasma display panel sustain driving device 301. The plasma display panel 311 is charged and discharged while sequentially performing a mode (pre-discharging mode) and a second discharge mode (post-discharging mode).

The power recovery unit 321 may include the first to fourth capacitors Cd1, Cd2, Cu1, and Cu2 and the first capacitor Cd1 connected in series between the power supply voltage Vs and the ground voltage GND. 4) The first and second diodes Dr1 and Sr1 connected to the first and second MOS transistors Sr1 and Sf1 and the first and second MOS transistors Sr1 and Sf1 respectively connected in parallel to each other with Vs supplied thereto. Df1) and the seventh and eighth diodes Dr11 and Df11 and the first and second diodes Dr1 and Df1 that are connected in parallel to the first and second MOS transistors Sr1 and Sf1, respectively. Third and fourth MOS transistors Sr2 and Sf2 and third and fourth MOS transistors (3/4) Vs supplied from the first inductor L1 and the third capacitor Cu2 and connected in parallel to each other ( Third and fourth diodes Dr2 and Df2 connected to Sr2 and Sf2, and ninth and tenth diodes Dr22 and Df22 connected in parallel to third and fourth MOS transistors Dr2 and Df2, respectively. , Third and fourth diodes Dr2 and Df2 Fifth and fifth connected to the second inductor L2 and the first and second inductors L1 and L2 which are commonly connected, and (1/2) Vs is supplied to the mutual connection point from the second capacitor Cd2. 6 diodes Dd and Du.

The switching unit 341 provides a passage for current flowing between the power recovery unit 321 and the plasma display panel 311. The switching unit 341 includes four MOS transistors Sd1, Sd2, Su2, and Su1 connected in series between the power supply voltage Vs and the ground voltage GND.

The clamping unit 331 clamps the surge voltage generated in the power recovery unit 321. The clamping unit 331 does not apply a surge voltage higher than the rated voltage of the semiconductor devices provided in the power recovery unit 321, for example, the voltage set to (1/4) Vs, to the semiconductor devices. Accordingly, it is possible to select semiconductor devices having a lower rated voltage, thereby enabling the use of smaller semiconductor devices.

The clamping part 331 includes clamping diodes Dc1 to Dc4.

4 illustrates waveforms and timings of signals of the plasma display panel sustain driving apparatus 301 shown in FIG. 3. In Fig. 4, the hatched portion is a period in which the conduction and blocking of the gate signal are not related. For convenience of analysis, it is assumed that voltages at both ends of the capacitors Cd1, Cd2, Cu1, and Cu2 are maintained at (1/4) Vs, respectively, and the inductors L1 and L2 have the same inductance value.

5A through 5H are circuit diagrams showing current paths in bold lines in various modes according to the switching sequence of the plasma display panel sustain driving apparatus 301 shown in FIG. 3, and FIGS. 6A to 6D are shown in FIG. 3. FIG. 1 is a circuit diagram showing a path of a parasitic current for clamping a surge voltage generated in various modes according to a switching sequence by the plasma display panel sustain driving device 301 in bold lines.

An operation of the plasma display panel sustain driving apparatus 301 illustrated in FIG. 3 will be described with reference to FIGS. 4, 5A through 5H, and FIGS. 6A through 6D.

(1) first mode (t0-t1; pre-charging mode)

Before the initial stage, that is, t0, the MOS transistors Sd1 and Sd2 are turned on to maintain the plasma display panel voltage Vp at 0 [V]. When the MOS transistor Sd1 is turned off at the t0 and the first MOS transistor Sr1 is turned on, as shown in FIG. 5A, the plasma passes through the resonance path of Cd1-Sr1-Dr1-L1-Sd2-Cp. The display panel 311 is charged and the plasma display panel voltage Vp is changed from 0 [V] to ( ), And the plasma display panel current ip is limited to the maximum value of {Vs / (4 × Z _n )}. Here, dV is the voltage drop due to the parasitic resistance in the power recovery unit 321, Zn is represented by the following equation (1).

Where L is the inductance of the first inductor L1.

(2) second mode (t1-t2; Vs / 2 mode)

At t1, the MOS transistor Sud2 is turned off, and the MOS transistor Su2 is turned on, and as shown in FIG. 5B, the plasma display panel voltage Vp is + (+) through the resonance path of Cd1-Cd2-Du-Su2-Cp. Vs / 2). The gate signal is designed to be as short as possible in the second mode section for high frequency operation. Here, the parasitic current is generated by the reverse recovery characteristic of the first diode Dr1 due to the voltage change by dV, and the third clamp diode Dc3 is turned on. The parasitic current is clamped through the path of Sd1-L1-Dd2-Cd2-Cd1 as shown in FIG. 6A. Therefore, a surge voltage is not applied to the semiconductor devices provided in the power recovery unit 321. In addition, the voltage across the first inductor L1 becomes (Vs / 4), and the parasitic current is reduced by the slope of-(Vs / 2L1).

(3) third mode (t2-t3; post-charging mode)

At t2, the third MOS transistor Sr2 is turned on, and the plasma display panel voltage Vp becomes (Vs−) by the resonance path of Cd1-Cd2-Cu2-Sr2-Dr2-L2-Su2-Cp as shown in FIG. 5C. dV), and the plasma display panel current ip is limited to the maximum value of {Vs / (4 × Z _n )} as in the first mode. The duration of the first mode section and the third mode section is the same.

(4) fourth mode (t3-t4; panel light emitting mode)

At t3, the MOS transistor Su1 is turned on at a zero voltage switching condition so that the plasma display panel voltage Vp is maintained at the power supply voltage Vs by the resonance path of Su1-Su2-Cp as shown in FIG. 5D. The sustain discharge current of the display panel 311 flows. The fourth mode section is determined according to the discharge properties of the plasma display panel 311 and usually has a value of 1.3 to 1.7 [us]. The parasitic current is generated by the reverse recovery characteristic of the third diode Dr2 due to the voltage change by dV, so that the first clamp diode Dc1 is turned on. The parasitic current is clamped in the path of Su1-L2-Du1 as shown in FIG. 6B so that the surge voltage is not applied to the semiconductor devices of the power recovery unit 321. The voltage Vf at both ends of the second inductor L2 is about 1.7 [V], and the parasitic current is reduced by the slope of-(Vf / L2). The voltage Vf at both ends of the second inductor L2 is the sum of the forward voltage drop (normally 0.7 volts) of the first clamp diode Dc1 and the voltage drop caused by the parasitic resistance (about 1 volt).

(5) fifth mode (t4-t5; pre-discharging mode)

At t4, the MOS transistor Su1 is turned off, the fourth MOS transistor Sf2 is turned on, and as shown in FIG. 5E, the plasma display is performed through the resonance path Cp-Su2-L2-Df2-Sf2-Cu2-Cd2-Cd1. The panel 311 discharges. The plasma display panel voltage Vp is reduced from the power supply voltage Vs to {(Vs / 2) + dV}, and the discharge current of the plasma display panel 311 is limited to {Vs / (4 × Zn)}. . Zn is equal to Equation 1.

(6) 6th mode (t5-t6; + Vs / 2 mode)

At t5, MOS transistor Su2 is turned off, and MOS transistor Sud2 is turned on under a zero voltage switching condition. As shown in FIG. 5F, the plasma display panel voltage Vp is maintained at + Vs / 2 through the resonance paths Cd1-Cd2-Dd-Sd2-Cp. As in the second mode, the gate signal is designed to be as short as possible in the second mode section for high frequency operation. Here, the parasitic current is generated by the reverse recovery characteristic of the diode Df2 due to the voltage change by dV, so that the second clamp diode Dc2 is turned on. As shown in FIG. 6C, the parasitic current is clamped through the path of Cd 1 -Cd 2 -Dc 2 -L 2 -Su to prevent the surge voltage from being applied to the semiconductor devices provided in the power recovery unit 321. The voltage across the second inductor L2 becomes (Vs / 2) so that the parasitic current decreases with a slope of-(Vs / 2L2).

(7) seventh mode (t6-t7; post-discharging mode)

When the second MOS transistor Sf1 is turned on at t6, the seventh mode is started. As shown in FIG. 5G, the plasma display panel voltage Vp drops to 0 at + Vs / 2 through the resonance paths Cp-Sd2-L1-Df1-Sf1-Cd1. The seventh mode section has the same duration as the fifth mode section.

(8) eighth mode (t7-t8; ground mode)

As shown in Fig. 5H, the MOS transistor Sd1 is turned on at the zero voltage switching condition at t7, and the plasma display panel voltage Vp becomes 0 [V]. Here, the parasitic current is generated by the reverse recovery characteristic of the second diode Df1 due to the voltage change by dV, and the fourth clamp diode Dc4 is turned on. The parasitic current is clamped through the path of Dc4-L1-Sd1 to prevent surge voltages from being applied to the semiconductor devices provided in the power recovery unit 321 as shown in FIG. 6D. The voltage Vf at both ends of the first inductor L1 becomes 1.7 [V] so that the parasitic current decreases with a slope of − (Vf / L1).

During the next half cycle, the plasma display panel sustain driving device 301 connected to the other electrode 313 of the plasma display panel 311 repeats the eighth mode in the first mode to apply a high frequency AC voltage to the plasma display panel 311. Done.

As such, the voltages of the semiconductor devices provided in the power recovery unit 321 are clamped to (Vs / 4) by the first to fourth clamp diodes Dc1 to Dc4. The rated voltage of the first to fourth clamping diodes Dc1 to Dc4 is (Vs / 2).

7 is a circuit diagram of the plasma display panel sustain driving apparatus 701 according to the second embodiment of the present invention. The plasma display panel sustain driving device 701 shown in FIG. 7 is similar in configuration to the plasma display panel sustain driving device 301 shown in FIG. 3, except that the clamp diodes Dc1 to Dc4 are connected to each other. different. As shown in FIG. 7, even when the clamp diodes Dc1 to Dc4 are connected, surge voltages are not applied to the semiconductor devices provided in the power recovery unit, and the rated voltage of the semiconductor devices is clamped at (Vs / 4). do.

8 is a circuit diagram of the plasma display panel sustain driving apparatus 801 according to the third embodiment of the present invention. The plasma display panel sustain driving device 801 shown in FIG. 8 is similar to the plasma display panel sustain driving device 301 shown in FIG. 3, except that the MOS transistors Sf1 and Sr1 and the MOS transistors Sf2, Sr2) is connected in series with each other, and the connection portions of the clamp diodes Dc1 and Dc3 are different from those of FIG. Missing The effect is the same as the circuit shown in FIG.

The best embodiments have been disclosed in the drawings and the specification. Those skilled in the art may have various modifications and equivalent other embodiments, and the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

As described above, according to the present invention, the plasma display panel sustain driving apparatuses 301, 701, and 801 are configured to form different resonance paths in the first to eighth modes, respectively. The voltage stress applied to the N / A is reduced by half, so that a high performance low-cost semiconductor device can be used, and a clamping part can be used to prevent surge voltages from being applied to the semiconductor devices provided in the power recovery part. It is possible to select semiconductor elements.

Claims (5)

An apparatus for driving a plasma display panel, A power recovery unit for charging, maintaining and discharging the plasma display panel for a predetermined time; A switching unit providing a passage of current flowing between the power recovery unit and the plasma display panel; And And a clamping unit for clamping a surge voltage generated in the power recovery unit. The method of claim 1, wherein the power recovery unit includes a plurality of MOS transistors and a plurality of diodes connected to the MOS transistors, and the clamping unit includes a plurality of other clamping clamping parasitic currents generated by the plurality of diodes. A plasma display panel sustain drive device comprising diodes. The plasma display panel sustain driving apparatus of claim 2, wherein the MOS transistors, the diodes, and the clamping diodes are respectively four. The method of claim 1, wherein the plasma display panel sustain driving device First to fourth capacitors connected in series between a power supply voltage Vs and a ground voltage; First and second MOS transistors receiving (1/4) Vs from the fourth capacitor and connected in parallel with each other; First and second diodes connected to the first and second MOS transistors, respectively; A first inductor commonly connected to the first and second diodes; Third and fourth MOS transistors receiving (3/4) Vs from the third capacitor and connected in parallel to each other; Third and fourth diodes connected to the third and fourth MOS transistors, respectively; A second inductor commonly connected to the third and fourth diodes; Fifth and sixth diodes connected to the first and second inductors and supplied with (1/2) Vs from the second capacitor to an interconnection point; First to fourth clamping diodes connected to the first to fourth diodes, respectively, for clamping parasitic currents generated by the first to fourth diodes; And And a plurality of MOS transistors connected between the first and second inductors and the plasma display panel, and configured to switch a passage of current flowing therebetween. The method of claim 1, wherein the plasma display panel sustain driving device First to fourth capacitors connected in series between a power supply voltage Vs and a ground voltage; First and second MOS transistors (1/4) Vs supplied from the fourth capacitor and connected in series with each other; First and second diodes connected in parallel to the first and second MOS transistors, respectively; A first inductor connected to the second MOS transistor; Third and fourth MOS transistors receiving (3/4) Vs from the third capacitor and connected in series with each other; Third and fourth diodes connected in parallel to the third and fourth MOS transistors, respectively; A second inductor connected to the fourth MOS transistor; Fifth and sixth diodes connected to the first and second inductors and supplied with (1/2) Vs from the second capacitor to an interconnection point; First to fourth clamping diodes connected to the first to fourth diodes, respectively, for clamping parasitic currents generated by the first to fourth diodes; And And a plurality of MOS transistors connected between the first and second inductors and the plasma display panel, and configured to switch a passage of current flowing therebetween.