KR20050006241A - Integrated circuit with internal impedance matching circuit - Google Patents

Integrated circuit with internal impedance matching circuit Download PDF

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Publication number
KR20050006241A
KR20050006241A KR10-2004-7018046A KR20047018046A KR20050006241A KR 20050006241 A KR20050006241 A KR 20050006241A KR 20047018046 A KR20047018046 A KR 20047018046A KR 20050006241 A KR20050006241 A KR 20050006241A
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KR
South Korea
Prior art keywords
integrated circuit
transmission line
package
die
lead
Prior art date
Application number
KR10-2004-7018046A
Other languages
Korean (ko)
Inventor
노베르트 에이. 슈미즈트
리처드 제이. 지아치노
웨인 엠. 스트러블
Original Assignee
엠/에이-컴, 인크.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/142,250 external-priority patent/US6828658B2/en
Priority claimed from US10/427,330 external-priority patent/US6903447B2/en
Application filed by 엠/에이-컴, 인크. filed Critical 엠/에이-컴, 인크.
Publication of KR20050006241A publication Critical patent/KR20050006241A/en

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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
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    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
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    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
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    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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    • H01L2924/30105—Capacitance
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Abstract

집적 회로 패키지(100)는 내부 정합(106)을 구비한 집적 회로(104)를 형성하기 위해 다이를 하우징하고 이에 전기적으로 연결된다. 이러한 패키지는 적어도 하나의 전송선과, 다이 패들과, 적어도 하나의 입력 리드 및 적어도 하나의 출력 리드(102)를 구비하는 리드 프레임을 포함한다. 본드 와이어는 상기 적어도 하나의 전송선을 따라 있는 선택 위치를 적어도 하나의 출력 리드에 관련된 임피던스 정합망(106)을 통해 접지에 연결시킨다. 또한, 패키지는 다이 패들과 입출력 리드는 노출시키면서 리드 프레임을 실질적으로 인캡슐레이트한다.The integrated circuit package 100 houses and electrically connects the die to form an integrated circuit 104 having an internal match 106. This package includes a lead frame having at least one transmission line, a die paddle, at least one input lead and at least one output lead 102. A bond wire connects the selected location along the at least one transmission line to ground via an impedance matching network 106 associated with the at least one output lead. In addition, the package substantially encapsulates the lead frame while exposing the die paddle and input / output leads.

Description

내부 임피던스 정합 회로를 구비한 집적 회로{Integrated circuit with internal impedance matching circuit}Integrated circuit with internal impedance matching circuit

본 발명은 반도체 장치 분야에 관한 것으로, 좀더 구체적으로는 내부 임피던스 정합을 구비한 집적 회로에 관한 것이다.TECHNICAL FIELD The present invention relates to the field of semiconductor devices, and more particularly to an integrated circuit having an internal impedance match.

셀룰러 전화에서, 무선 주파수(RF) 전력 증폭기(power amplifier: PA)는 낮은 출력 임피던스(예, 2 오옴 이하)를 갖는 반도체 장치(예, 실리콘 또는 갈륨 비소)를 이용하여 구축된다. 이러한 임피던스는 무선기의 나머지 부분의 필터, 스위치, 디플렉서 및 안테나에 연결시키기 위해 좀더 높은 임피던스 값(예, 50오옴)으로 변환될 필요가 있다. 이러한 임피던스 변환망이 전형적으로 "출력정합"으로 지칭된다.In cellular telephones, radio frequency (RF) power amplifiers (PAs) are built using semiconductor devices (eg, silicon or gallium arsenide) with low output impedance (eg, 2 ohms or less). This impedance needs to be converted to higher impedance values (eg 50 ohms) to connect to the filters, switches, deplexers and antennas of the rest of the radio. This impedance conversion network is typically referred to as "output matching".

2 오옴의 임피던스를 50 오옴의 임피던스로 변환시키는 것에 부가하여, 출력 정합은 셀룰러 전화기의 효율성 및 배터리 수명(예, 통화시간)을 증가시키기 위한 고조파 주파수로 전형적으로 동조된다. 이러한 고조파 주파수는 6 기가헤르쯔까지 확장된다. 이 주파수에서, 커패시터와 출력 정합을 구성하기 위해 사용되는 다른 패시브 요소들간의 거리가 중요한데, 예를 들어, 0.001??의 거리도 중요한 의미를 갖는다. 예를 들어, 벤더는 출력 정합망의 커패시터와 다른 패시브 요소들간에 천분의 일 인치의 정확도로 0.062?? 및 0.416?? 거리를 규정할 수 있다.In addition to converting 2 ohm impedance to 50 ohm impedance, output matching is typically tuned to harmonic frequencies to increase the efficiency and battery life (eg talk time) of cellular telephones. These harmonic frequencies extend up to 6 gigahertz. At this frequency, the distance between the capacitor and the other passive elements used to construct the output match is important, for example a distance of 0.001 ?? For example, a vendor may need to measure 0.062? With an accuracy of one thousandth of an inch between the capacitors of the output matching network and the other passive elements. And 0.416 ?? You can specify the distance.

고조파 주파수는 제2의 문제점을 제시한다. 커패시터들은 고조파 주파수에서 중요한 기생값을 갖는다. 기생값들이 제조업자들마다 다르기 때문에, 동일한 값의 요소에 대한 벤더를 변경하면 상이한 결과를 낳을 것이다.Harmonic frequencies present a second problem. Capacitors have important parasitic values at harmonic frequencies. Since parasitic values vary from manufacturer to manufacturer, changing the vendor for an element of the same value will produce different results.

다량(예, 1년당 30,000,000)을 산출하는데 있어서, 단일 벤더에 대한 이러한 종속성 및 0.001??의 오차허용도는 관리하기에 매우 까다롭다. 따라서, 임피던스 정합망을 제공하는 개선된 기술이 필요하다.In calculating large quantities (e.g., 30,000,000 per year), this dependency on a single vendor and tolerances of 0.001 ?? are very difficult to manage. Thus, there is a need for an improved technique for providing impedance matching networks.

도 1은 RF 출력 신호의 종래 정합 회로 구성의 기능 블럭도를 도시한다.1 shows a functional block diagram of a conventional matching circuit configuration of an RF output signal.

도 2는 제1 플라스틱 패키지내에 제1 다이와 제2 다이를 포함하는 제1 집적 회로의 상부 절단도를 도시한다.2 shows a top cutaway view of a first integrated circuit including a first die and a second die in a first plastic package.

도 3은 도 2에 도시된 제1 다이에 연관된 내부 정합망의 기능 블럭도이다.3 is a functional block diagram of an internal matching network associated with the first die shown in FIG.

도 4는 적어도 하나의 출력 신호를 제공하는 제2 집적 회로의 리드 프레임의 상부 절단도이다.4 is a top cutaway view of a lead frame of a second integrated circuit providing at least one output signal.

도 5는 도 4의 선 A-A을 따라 있는 섹션을 도시한다.FIG. 5 shows a section along line A-A of FIG. 4.

도 6은 도 4의 제2 플라스틱 패키지의 하부도를 도시한다.6 shows a bottom view of the second plastic package of FIG. 4.

도 7은 도 6의 패키지의 측면도를 도시한다.7 shows a side view of the package of FIG. 6.

도 8은 다이내에 위치한 내부 정합 회로를 포함하는 제3 집적 회로의 리드 프레임의 상부 절단도이다.8 is a top cutaway view of a lead frame of a third integrated circuit including an internal matching circuit located within the die.

도 9는 그물선으로 도시된 도 8의 리드 프레임의 상부도이다.FIG. 9 is a top view of the lead frame of FIG. 8 shown in a mesh.

도 10은 그물선으로 도시된 리드 프레임의 노출 섹션과 함께 도 8의 리드 프레임의 하부도이다.FIG. 10 is a bottom view of the lead frame of FIG. 8 with exposed sections of the lead frame shown in mesh lines. FIG.

도 11은 다이 패들과 전송선상의 제1 선택 위치간에 위치한 내부의 정합 네트워크를 포함하는 제4의 집적 회로의 리드 플레임의 상부 절단도이다.11 is a top cutaway view of a lead frame of a fourth integrated circuit including an internal matching network located between a die paddle and a first selected location on a transmission line.

도 12는 다이와 전송선상의 제1 선택 위치 사이에 위치한 제1의 내부 정합망과, 다이 패들과 전송선상의 제2 선택 위치사이에 위치한 제2의 내부 정합망을 포함하는 제5 집적 회로의 리드 프레임의 상부 절단도이다.12 is a lead of a fifth integrated circuit including a first internal matching network located between a die and a first selection location on a transmission line and a second internal matching network located between a die paddle and a second selection location on a transmission line. Top cutaway view of the frame.

도 13은 도 12의 집적 회로와 연관된 내부의 정합망의 기능 블록도이다.FIG. 13 is a functional block diagram of an internal matching network associated with the integrated circuit of FIG. 12.

도 14는 전송선상의 제1 선택 위치와 접지핀사이에 위치한 내부의 정합망을 포함하는 제6 집적 회로의 리드 프레임의 상부 절단도이다.FIG. 14 is a top cutaway view of a lead frame of a sixth integrated circuit including an internal matching network located between a first selected position on a transmission line and a ground pin.

간략히, 본 발명의 일실시예에 따르면, 집적 회로는 패키지내에 하우징되고 전기적으로 연결된 다이(die)를 포함한다. 패키지는 전송선과, 적어도 하나의 입력 신호 리드와, 전송선에 연결되는 적어도 하나의 출력 신호 리드를 포함하는 리드 프레임을 구비한다. 다이는 전송선에 대한 출력 신호를 제공한다. 전송선을 따라 있는 적어도 하나의 선택 위치가 집적회로 패키지내의 출력정합회로를 통해 제1 전극 노드에 연결되고, 상기 임피던스 정합 회로는 출력 신호 리드와 연관되어 있다.Briefly, in accordance with one embodiment of the present invention, an integrated circuit includes a die housed in an package and electrically connected. The package includes a lead frame including a transmission line, at least one input signal lead, and at least one output signal lead connected to the transmission line. The die provides an output signal for the transmission line. At least one selection position along the transmission line is connected to the first electrode node via an output matching circuit in the integrated circuit package, the impedance matching circuit being associated with the output signal lead.

임피던스 정합 회로는 집적 회로내에 위치할 수 있다. 예를 들어, 일실시예에서, 임피던스 정합 회로는 전송선을 따라 있는 적어도 하나의 선택 위치와 리드 프레임의 핀사이에 연결되어 있을 수 있다.The impedance matching circuit can be located in an integrated circuit. For example, in one embodiment, the impedance matching circuit may be connected between at least one selected position along the transmission line and the pin of the lead frame.

일실시예에서, 전송선을 따라 있는 적어도 하나의 선택 위치가 커패시터에 와이어 본딩되어 있다. 소정의 정합 회로(즉, 출력 임피던스)를 제공하기 위해 커패시터의 커패시터값과 전송선의 치수가 선택된다.In one embodiment, at least one selection location along the transmission line is wire bonded to the capacitor. The capacitor value of the capacitor and the dimensions of the transmission line are selected to provide the desired matching circuit (ie output impedance).

전송선을 리드 프레임에 통합시킴으로써 정합망을 집적 회로의 외부에 배치하여야 하는 상황을 피할 수 있다. 예를 들어, 전송선을 제공하기 위해 리드 프레임을 에칭 및/또는 절반 에칭하고 임피던스 변환 정합 회로의 요소들(예, 커패시터, 인덕터 등)을 집적 회로상에 배치하고 전송선상의 선택 위치들과 제1 전기 노드(예, 접지)사이에 요소들을 연결시키는 것은 비교적 비용이 적다.By integrating the transmission lines into the lead frame, the situation of having to place the matching network outside of the integrated circuit can be avoided. For example, the lead frame is etched and / or half etched to provide a transmission line, the elements of the impedance conversion matching circuit (e.g., capacitors, inductors, etc.) are placed on the integrated circuit and selected locations on the transmission line and the first Connecting elements between electrical nodes (eg, ground) is relatively inexpensive.

본 발명의 전술하거나 그외의 목적, 특징 및 장점들은 첨부된 도면에 도시된 바와 같이, 바람직한 실시예에 대한 이하의 상세한 설명에 따라 더욱 명백해질 것이다.The above and other objects, features and advantages of the present invention will become more apparent according to the following detailed description of the preferred embodiment, as shown in the accompanying drawings.

도 1은 선(102)상에 출력 신호를 제공하는 예시적인 종래의 정합 회로 구성(100)의 기능 블록도를 도시한다. 일실시예에서, 선(102)상의 출력 신호는 집적 회로(104)내의 RF 전력 증폭기(PA)로부터 발생한 것이다. 집적 회로(104)는 라인(102)상의 출력 신호를 임피던스 변환망(106)(본명세서에서, "정합망"이라고도 지칭됨)으로 제공하고, 임피던스 변환망(106)은 선(108)상에 정합된 출력 신호를 제공한다. 예를 들어, 선(108)상의 임피던스 정합 출력 신호는 예를 들어, 50 오옴의 출력 임피던스를 가질 수 있는 반면에, 선(102)상 신호의 임피던스는 예를 들어 2 오옴일 수 있다. 임피던스 정합망(106)은 요구되는 임피던스 변환 및 고조파 필터링을 제공하기 위해 정확하게 배치되는 복수의 커패시터, C1(110), C2(112)를 포함한다. 예를 들어, 커패시터 C1(110)은 집적 회로(104)의 모서리(114)로부터 (예를 들어, 0.001??의 오차 정확도로) 정확하게 배치되어 있으며, 커패시터 C1(110)와 C2(112)사이의 거리 또한 정확하게 제어된다. 전술한 바와 같이, 이러한 배치 제약은 집적 회로(104)의 외부에 존재하는 문제를 일으킬 소지가 있고 비용면에서도 상당히 비싼 정합망의 결과를 낳는다.1 shows a functional block diagram of an exemplary conventional matching circuit arrangement 100 for providing an output signal on line 102. In one embodiment, the output signal on line 102 is from an RF power amplifier PA in integrated circuit 104. Integrated circuit 104 provides an output signal on line 102 to impedance conversion network 106 (also referred to herein as " matching network "), and impedance conversion network 106 is on line 108. Provide a matched output signal. For example, the impedance matched output signal on line 108 may have an output impedance of 50 ohms, for example, while the impedance of the signal on line 102 may be 2 ohms, for example. Impedance matching network 106 includes a plurality of capacitors, C1 110 and C2 112, which are correctly positioned to provide the required impedance conversion and harmonic filtering. For example, capacitor C1 110 is accurately positioned (eg, with an error accuracy of 0.001 ??) from edge 114 of integrated circuit 104, and is located between capacitor C1 110 and C2 112. Is also accurately controlled. As discussed above, such placement constraints can result in a problem existing outside of the integrated circuit 104 and result in a matching network that is quite expensive in terms of cost.

도 2는 플라스틱 패키지내에 제1 다이(202)와 제2 다이(204)를 포함하는 상부 절단도이다. 제1 다이(202)는 본드 와이어(206, 208)를 통해 리드 프레임(예, 에칭된 구리)상에 위치한 제1 전송선(210)으로 출력 신호를 제공한다. 제2 다이(204)는 본드 와이어(212, 214)를 통해 리드 프레임상에 위치한 제2 전송선(216)에 출력 신호를 제공한다. 리드 프레임은 복수의 입출력 리드들(예, 218-222)을 또한 포함한다. 본드 와이어는 다이상의 본딩 패드와 입출력 리드를 상호접속시킨다.2 is a top cutaway view including a first die 202 and a second die 204 in a plastic package. The first die 202 provides an output signal through the bond wires 206 and 208 to the first transmission line 210 located on the lead frame (eg, etched copper). The second die 204 provides an output signal to the second transmission line 216 located on the lead frame via bond wires 212 and 214. The lead frame also includes a plurality of input and output leads (eg, 218-222). The bond wires interconnect the bonding pads on the die and the input / output leads.

본 발명의 일측면에 따르면, 리드 프레임은 내부 정합을 갖는 집적 회로를 제공하기 위해 집적 회로내의 회로 요소들과 협력하는 적어도 하나의 전송선(예, 비-노출 영역내의 0.1mm 두께 및 노출 영역내의 0.2mm 두께)을 또한 포함한다. 구체적으로, 이러한 실시예에서, 제1 다이(202)상에 위치한 커패시터 및/또는 인덕터(미도시)와 같은 정합 회로 요소들은 제1 전송선(210)에 연결되어 있다. 예를 들어, 제1 다이(202)상에 위치한 제1 커패시터는 본드 와이어(230, 231)에 의해 전송선(210)쌍의 제1 선택 위치에 연결된다. 이 실시예에서, 전류 처리를 위해 2개의본드 와이어가 도시되어 있다. 그러나, 당업자라면, 요구되는 전류 처리에 따라, 다이상의 정합 회로 요소들을 전송선에 연결시키기 위해 그보다 많거나 적은 수의 본드 와이어가 사용될 수 있음도 당연히 인식할 것이다. 또한, 제2 커패시터(미도시)가 다이(202)상에 위치하여 도 1에 도시된 회로(106)에 기능적으로 유사한 정합 회로를 제공하기 위해 본드 와이어(미도시)에 의해 전송선(210)상의 제2 위치(예, 위치(240))에 연결될 수 있다. 그러나, 도 2의 실시예의 경우에, 정합망은 집적 회로에 위치한다. 즉, 도 2의 집적 회로는 내부 정합을 포함한다.According to one aspect of the present invention, a lead frame includes at least one transmission line (e.g., 0.1 mm thick in non-exposed areas and 0.2 in exposed areas) that cooperates with circuit elements within the integrated circuit to provide an integrated circuit with internal matching. mm thickness). Specifically, in this embodiment, matching circuit elements such as capacitors and / or inductors (not shown) located on the first die 202 are connected to the first transmission line 210. For example, a first capacitor located on the first die 202 is connected to the first select location of the pair of transmission lines 210 by bond wires 230, 231. In this embodiment, two bond wires are shown for current processing. However, those skilled in the art will naturally appreciate that more or fewer bond wires may be used to connect the matching circuit elements on the die to the transmission line, depending on the current processing required. In addition, a second capacitor (not shown) is positioned on die 202 to provide a matching circuit that is functionally similar to the circuit 106 shown in FIG. 1 by a bond wire (not shown) on transmission line 210. It may be connected to a second location (eg, location 240). However, in the case of the embodiment of FIG. 2, the matching network is located in the integrated circuit. That is, the integrated circuit of FIG. 2 includes an internal match.

제2 다이(204)는 제2 다이(204)내의 정합 회로 요소들을, 예를 들어, 본드 와이어(242, 24)를 통해 전송선(216)에 연결시킴으로써 확립되는 내부 정합망을 또한 포함할 수 있다.The second die 204 may also include an internal matching network established by connecting the matching circuit elements in the second die 204 to the transmission line 216, for example, via bond wires 242, 24. .

도 3은 도 2에 도시된 제1 다이(202)와 연관된 내부 정합망의 기능 블록도이다. 예를 들어, 다이(202)상에 위치한 출력 증폭기(246)는 전송선(210)에 의해 전도된 출력 신호를 입출력 리드(248)에 제공한다. 다이(202)상에 위치한 커패시터(252)의 제1 리드는 본드 와이어(230,231)를 통해 전송선(210)상의 제1 선택 위치(254)에 연결되어 있다. 커패시터(252)의 제2 리드는 제1 전위(예, 접지)에 연결되어 있다. 의미적으로, 이는 집적 회로(200)내에 위치한 임피던스 정합 회로(258)를 제공한다.3 is a functional block diagram of an internal matching network associated with the first die 202 shown in FIG. For example, the output amplifier 246 located on the die 202 provides the input and output leads 248 with an output signal conducted by the transmission line 210. The first lead of the capacitor 252 located on the die 202 is connected to the first selected location 254 on the transmission line 210 via bond wires 230, 231. The second lead of the capacitor 252 is connected to a first potential (eg, ground). Semantically, this provides an impedance matching circuit 258 located within integrated circuit 200.

도 4는 다이(도 4에는 도시되어 있지 않음)를 포함하는, 즉, 복수개의 입출력 리드(예, 308-314)를 포함하는 리드 프레임(306, 예, 에칭된 구리)의 다이 패들(302)상으로 배치된 제2 집적 회로(300)의 상부 절단도이다. 다이상에 위치한 상호연결 본딩 패드는 예를 들어 본드 와이어를 통해 입출력 리드들에 접속된다. 리드 프레임(306)은 그물선으로 도시된 제1 전송선(320)을 또한 포함한다. 이러한 실시예에서, 패키지는 패키지의 외부상으로 노출되지 않는 제2 전송선(320)을 또한 포함한다. 제1 전송선(320)은 패키지로부터의 제1 출력 신호와 연관되어 있는 반면에, 제2 전송선은 패키지로부터의 제2 출력 신호에 연관된어 있다. 다이상에 위치하며 제1 출력 신호와 연관되어 있는 커패시터 및/또는 인덕터(미도시)와 같은 정합 회로 요소들은 제1 전위(예, 접지)와 제1 전송선(320)상의 적어도 하나의 선택 위치 사이에 연결되어 있다.4 illustrates a die paddle 302 of a lead frame 306 (eg, etched copper) that includes a die (not shown in FIG. 4), that is, includes a plurality of input / output leads (eg, 308-314). Top cutaway view of a second integrated circuit 300 disposed thereon. The interconnect bonding pads located on the die are connected to the input and output leads, for example via bond wires. The lead frame 306 also includes a first transmission line 320 shown as a mesh. In this embodiment, the package also includes a second transmission line 320 that is not exposed to the outside of the package. The first transmission line 320 is associated with the first output signal from the package, while the second transmission line is associated with the second output signal from the package. Matching circuit elements, such as capacitors and / or inductors (not shown) located on the die and associated with the first output signal, may be disposed between a first potential (eg, ground) and at least one selected location on the first transmission line 320. Is connected to.

도 5는 도 4의 A-A를 따라 취해진 절단면을 도시한다. 다이(402)는 패들(302)상에 위치하며, 적어도 하나의 본드 와이어(404)는 리드(313)와 다이(402)상의 본드 패드(미도시)를 접속시킨다. 도 6은 제2 집적 회로의 하부도를 도시한다. 도시된 바와 같이, 리드 프레임은 패들(302)과 복수의 입출력 리드(예, 308-314)를 포함한다. 도 5 및 5을 참조하면, 패키지는 정합 회로 요소들이 접속될 수 있는 전송선을 따라 있는 선택 위치를 나타내는 복수의 노출된 와이어 본드 지지 구조물(510-517)을 또한 포함한다. 예를 들어, 일 실시예에서, 이러한 지지 구조물(예, 에칭된 구리)들은 다이상의 정합 요소들과 패키지의 리드 프레임내의 전송선들 사이의 본드 와이어들에 대한 접속 지점들이다. 예를 들어, 본딩 와이어(도 5의 430)는 다이(402)쌍의 정합 요소(예, 커패시터)와지지 구조물(511, 즉, 전송선(320)상의 선택 위치) 사이를 지난다.FIG. 5 shows a cut plane taken along A-A of FIG. 4. Die 402 is located on paddle 302, and at least one bond wire 404 connects lead 313 and bond pads (not shown) on die 402. 6 shows a bottom view of a second integrated circuit. As shown, the lead frame includes a paddle 302 and a plurality of input and output leads (eg, 308-314). 5 and 5, the package also includes a plurality of exposed wire bond support structures 510-517 that represent selected locations along the transmission line to which the matching circuit elements can be connected. For example, in one embodiment, such support structures (eg, etched copper) are connection points for bond wires between mating elements on the die and transmission lines in the lead frame of the package. For example, the bonding wire 430 of FIG. 5 passes between the matching element (eg, capacitor) of the pair of die 402 and the support structure 511 (ie, the selected location on the transmission line 320).

도 7은 도 5의 패키지의 측면도이다.7 is a side view of the package of FIG. 5.

도 8은 다이(802)와 제3 플라스틱 패키지의 리드 프레임(804)를 포함하는 제3 집적 회로(800)의 상부 절단도이다. 도 9는 그물선으로 도시된 도 8의 리드 프레임(804)의 상부도이다. 리드 프레임(804)은 다이 패들(806)과 복수개의 입출력 리드들(808-823)를 포함한다. 또한, 리드 프레임은 다이(802)상의 출력부(828)를 선택된 입출력 리드들(808-812)에 연결시키는 전송선(826)을 포함한다. 이러한 실시예에서, 다이 출력부(828)는 복수개의 본드 와이어(831)에 의해 전송선(826)에 접속된다. 다이(802)는 임피던스 정합/변환망의 적어도 하나의 요소(예, 커패시터, 인덕터 등)를 포함한다. 다이내의 망정합 요소는 전송선(826)을 따라 있는 제1 선택 위치(830)에 접속된다. 그 결과, 도 3에 도시된 바와 같은 회로 구성이 제공된다.8 is a top cutaway view of a third integrated circuit 800 including a die 802 and a lead frame 804 of a third plastic package. FIG. 9 is a top view of the lead frame 804 of FIG. 8 shown in a mesh. The lead frame 804 includes a die paddle 806 and a plurality of input and output leads 808-823. The lead frame also includes a transmission line 826 connecting the output 828 on the die 802 to the selected input and output leads 808-812. In this embodiment, die output 828 is connected to transmission line 826 by a plurality of bond wires 831. Die 802 includes at least one element (eg, capacitor, inductor, etc.) of an impedance matching / conversion network. The network registration element in the die is connected to a first selected location 830 along the transmission line 826. As a result, a circuit configuration as shown in FIG. 3 is provided.

임피던스 정합 및 필터링 요구사항에 따라, 다이(802)내의 정합 회로 요소는, 상기 선택된 위치(830) 대신에, 전송선을 따라 있는 복수개의 선택 위치들(832-836)중 하나에서 전송선(826)에 접속될 수 있다. 도 8의 실시예에서, 집적 회로(800)는 4mm x 4mm이다(즉, L(850)은 4㎝와 동일하다). 도 8에 도시된 바와 같이, 전송선(826)의 경로 길이는 정합 회로 요소가 접속되는 선택 위치(예, 830)에 따라 달라질 것이다.Depending on the impedance matching and filtering requirements, the matching circuit element in die 802 may be connected to transmission line 826 at one of a plurality of selected locations 832-836 along the transmission line, instead of the selected location 830. Can be connected. In the embodiment of FIG. 8, integrated circuit 800 is 4 mm x 4 mm (ie, L 850 is equal to 4 cm). As shown in FIG. 8, the path length of the transmission line 826 will depend on the selected location (eg, 830) to which the matching circuit element is connected.

도 10은 그물선으로 도시된 도 8의 리드 프레임의 하부도이다. 이 도면에서, 전송선(도 9의 826)을 따라 있는 선택 위치(836)와 연관된 지지 구조물은 집적회로(800)의 하면상에 노출된다.FIG. 10 is a bottom view of the lead frame of FIG. 8 shown in a mesh. In this figure, the support structure associated with the selection location 836 along the transmission line 826 in FIG. 9 is exposed on the bottom surface of the integrated circuit 800.

도 11은 다이(1102)와, 제4 플라스틱 패키지의 리드 프레임(1104)을 포함하는 제4 집적 회로(1100)의 상부 절단도이다. 이 실시예는 도 8-10에 예시된 실시예와 실질적으로 동일하며, 주요한 상이점은 내부 정합망 요소(1106, 예, 커패시터)가 다이 패들(1108)과 전송선(826)상의 제1 선택 위치(1110) 사이에 위치한다는 점이다. 즉, 내부 정합회로 요소가 다이상에 위치하지 않는다. 그러나, 내부 정합 회로는 여전히 집적회로내에 존재하여 내부 정합을 제공한다.11 is a top cutaway view of a fourth integrated circuit 1100 that includes a die 1102 and a lead frame 1104 of a fourth plastic package. This embodiment is substantially the same as the embodiment illustrated in FIGS. 8-10, the main difference being that the internal matching network element 1106 (eg, a capacitor) has a first selected position (1) on the die paddle 1108 and the transmission line 826. 1110). That is, no internal matching circuit element is located on the die. However, internal matching circuits still exist within the integrated circuit to provide internal matching.

도 12는 다이(1202)와, 제5 플라스틱 패키지의 리드 프레임(1204)을 포함하는 제5 집적 회로(1200)의 상부 절단도이다. 이 실시예는 도 8-10 및 도 11에 예시된 실시예와 실질적으로 동일하며, 주요한 상이점은 제1 내부 정합망 요소(1206, 예, 커패시터)가 다이 패들(1208)과, 전송라인(826)상의 제1 선택 위치(1210)사이에 위치하고, 제2 내부 정합망 요소(미도시)가 다이(1202)내에 위치하고 전송선상의 제2 선택 위치(1212)에 연결되어 있다는 점이다.12 is a top cutaway view of fifth integrated circuit 1200 including die 1202 and lead frame 1204 of a fifth plastic package. This embodiment is substantially the same as the embodiment illustrated in FIGS. 8-10 and 11, the main difference being that the first internal matching network element 1206 (eg, a capacitor) is the die paddle 1208 and the transmission line 826. Is located between the first selection location 1210 on the top of the box, and a second internal matching network element (not shown) is located in the die 1202 and connected to the second selection location 1212 on the transmission line.

도 13은 도 12의 집적 회로와 연관된 내부 정합망의 기능 블록도이다. 예를 들어, 다이(1202)상에 위치한 출력 증폭기(1302)는 입출력 리드(808)로 전송선(826)에 의해 전도되는 출력 신호를 제공한다. 다이(1202)상에 위치한 커패시터(1306)의 제1 리드는 본드 와이어(1314)를 통해 전송선(826)상의 제2 선택 위치(1212)에 연결된다. 다이상의 커패시터(1306)상의 제2 리드는 제1 전위, 예를 들어, 접지에 연결되어 있다. 커패시터(1206)의 제1 리드는 전송라인(826)상의 제1 선택 위치(1210)에 연결되어 있는 반면에, 커패시터(1206)의 제2 리드는 다이 패들(즉, 접지)에 연결되어 있다.FIG. 13 is a functional block diagram of an internal matching network associated with the integrated circuit of FIG. 12. For example, an output amplifier 1302 located on die 1202 provides an output signal that is conducted by transmission line 826 to input / output leads 808. The first lead of capacitor 1306 located on die 1202 is connected to second selected location 1212 on transmission line 826 via bond wire 1314. The second lead on capacitor 1306 on the die is connected to a first potential, for example ground. The first lead of the capacitor 1206 is connected to the first selected location 1210 on the transmission line 826, while the second lead of the capacitor 1206 is connected to the die paddle (ie, ground).

도 14는 다이(1402)와, 제 6 패키지의 리드 프레임(1404)을 포함하는 제6 집적 회로(1400)의 상부 절단도이다. 이 실시예는 도 8-10 및 도 11 및 도 12에 예시된 실시예와 실질적으로 동일하며, 주요한 상이점은 제1 내부 정합망 요소(1406)가 접지 핀(1408)을 포함하는 제1 전위와 전송라인(1426)상의 선택 위치(1410) 사이에 위치한다는 것이다. 도 14에서, 내부 정합망 요소가 커패시터로 예시되어 있지만, 이외의 다른 적합한 요소, 예를 들면, 인덕터도 이용될 수 있음을 이해할 것이다. 이전 실시예들과 관련하여 전술한 바와 유사하게, 본 발명의 패키지는, 예를 들어, 임의의 소정의 물질(예, 플라스틱과 같은 전형적인 열경화성 또는 열가소성 물질(예, 플라스틱 몰드 화합물)을 이용하는 오버-몰딩(over-molding) 공정에 의해, 원하는 집적 회로의 부분을 실질적으로 인캡슐레이트(encapsulate)할 수 있디(또는 인케이스(encase))할 수 있다. 예를 들어, 본 발명의 다른 실시예들과 마찬가지로, 상기 실시예의 집적회로의 특정 부분, 예를 들어, 리드프레임이 실질적으로 인캡슐레이트될 수 있으며, 다른 특정 부분들, 예를 들면, 다이 패들 및 입출력 리드가 노출된 채로 남아 있을 수 있다.14 is a top cutaway view of a sixth integrated circuit 1400 including a die 1402 and a lead frame 1404 of a sixth package. This embodiment is substantially the same as the embodiment illustrated in FIGS. 8-10 and 11 and 12, the main difference being that the first internal matching network element 1406 includes a first potential with the ground pin 1408. It is located between the selected position 1410 on the transmission line 1426. In FIG. 14, while the internal matching network element is illustrated as a capacitor, it will be appreciated that other suitable elements, such as inductors, may also be used. Similar to what has been described above in connection with the previous embodiments, the package of the present invention can be used, for example, using any desired material (e.g., a typical thermoset or thermoplastic material such as plastic, e.g., a plastic mold compound). By over-molding process, it is possible to substantially encapsulate (or encase) a portion of the desired integrated circuit, for example, other embodiments of the invention. Similarly, certain portions of the integrated circuit of this embodiment, for example leadframes, may be substantially encapsulated, and other specific portions, such as die paddles and input / output leads, may remain exposed. .

도 14에 도시된 내부 정합망 요소(1406)는 필요하다면 위치(1410) 이외의 위치에서 전송선(1426)에 다른 실시예로 연결될 수 있다. 유사하게, 다른 실시예에서, 내부 정합망 요소(1406)는 접지핀(1408) 이외의 부분에 연결될 수 있다. 부가하여, 다른 실시예에서, 예를 들어, 도 8 내지 10 및 도12에 도시된 실시예들에 예시된 바와 같이, 필요하다면 복수의 정합망 요소들이 이용될 수 있다.The internal matching network element 1406 shown in FIG. 14 may be connected in another embodiment to the transmission line 1426 at locations other than the location 1410, if desired. Similarly, in other embodiments, internal matching network element 1406 may be connected to portions other than ground pin 1408. In addition, in other embodiments, a plurality of matching network elements may be used if desired, as illustrated, for example, in the embodiments shown in FIGS. 8-10 and 12.

유익하게, 본 발명의 실시예들은 내부 정합을 위한 집적 회로 및 패키지를 제공함으로써, 예를 들어, 핸드셋 제조업자(예, 보드 제조업자)들이임피던스 변환정합 회로를 위한 여분을 제공하여야 할 필요가 없도록 해준다. 부가하여, 본 발명의 실시예들은, 습기 또는 기타 바람직하지 못한 물질의 침투를 방지할 수 있는 장벽(barrier)을 제공하기 위하여, 집적 회로를 실질적으로 인캡슐레이팅하는 부재를 정의하는 패키지를 제공할 수 있다. 부가하여, 본 발명의 실시예들은 집적 회로의 전체 구조내에 에칭되거나 절반-에칭된 피처들을 이용할 수 있다. 예를 들어, 도 5에 도시된 바와 같이, 요소(313 및 314)들은 절반 에칭된 피처의 예들이며, 이들은 특정 요소들의 인터록킹(interlocking)을 위해 필요하다면 활용될 수 있다.Advantageously, embodiments of the present invention provide an integrated circuit and package for internal matching so that, for example, handset manufacturers (eg, board manufacturers) do not have to provide extra for an impedance conversion matching circuit. Do it. In addition, embodiments of the present invention may provide a package that defines a member that substantially encapsulates an integrated circuit to provide a barrier that can prevent penetration of moisture or other undesirable materials. Can be. In addition, embodiments of the present invention may utilize etched or half-etched features within the overall structure of an integrated circuit. For example, as shown in FIG. 5, elements 313 and 314 are examples of half etched features, which may be utilized if necessary for interlocking of certain elements.

본 발명은 무선 핸드셋의 전력 증폭기 관점에서 설명되었지만, 그 외의 다수의 어플리케이션들에서, 전형적으로 회로 보드상에서 또는 럼프형(lumped) 요소 컴포넌트들로서 수행되던 임피던스 정합을 필요로 하는 어플리케이션들을 집적 회로내에 포함된 정합 회로로 대체하는 것이 바람직함을 이해할 것이다. 유익하게, 이는 정합 회로의 요소들을 정확하게 배치하기 위한 것과 관련된 여러 가지의 제조상의 문제점들을 없앤다. 또한, 정합망 요소들은 전송선과 접지사이에 연결되어 있지만, 제1 전위가 반드시 접지일 필요는 없다.Although the present invention has been described in terms of power amplifiers in wireless handsets, in many other applications, applications requiring impedance matching, typically performed on circuit boards or as lumped element components, are included in integrated circuits. It will be appreciated that replacement with a matching circuit is desirable. Advantageously, this eliminates various manufacturing problems associated with correctly placing the elements of the matching circuit. The matching network elements are also connected between the transmission line and ground, but the first potential does not necessarily have to be ground.

본 발명은 여러 가지 바람직한 실시예와 관련하여 도시되고 설명되었지만, 이러한 바람직한 실시예들의 형태 및 상세부분에 다양한 변경, 생략 및 추가가 본 발명의 정신 및 범위를 벗어나지 않는 범주내에서 이루어질 수 있다.While the present invention has been shown and described with reference to various preferred embodiments, various modifications, omissions and additions in the form and details of these preferred embodiments may be made without departing from the spirit and scope of the invention.

Claims (37)

내부 정합 집적 회로에 있어서,In an internal matching integrated circuit, 적어도 하나의 입력 신호 리드와, 적어도 하나의 출력 신호 리드와, 상기 적어도 하나의 출력 신호 리드에 연결된 적어도 하나의 전송선을 포함하는 리드 프레임을 구비하는 패키지와,A package having a lead frame comprising at least one input signal lead, at least one output signal lead, and at least one transmission line connected to the at least one output signal lead; 상기 패키지에 전기적으로 연결되고 상기 패키지내에 하우징되며(housed) 상기 적어도 하나의 전송라인상으로 신호를 제공하는 다이를 포함하고,A die electrically connected to the package and housed in the package and providing a signal on the at least one transmission line, 상기 적어도 하나의 전송선을 따라 있는 선택 위치가 상기 집적 회로상에 위치한 임피던스 정합 회로를 통해 제1 전위에 전기적으로 연결되는 내부 정합 집적 회로.And a selection location along the at least one transmission line is electrically connected to a first potential via an impedance matching circuit located on the integrated circuit. 제1항에 있어서, 상기 전송선을 따라 있는 상기 선택 위치와 상기 임피던스 정합 회로는 적어도 하나의 본드 와이어를 통해 연결되는 내부 정합 집적 회로.The internal matched integrated circuit of claim 1, wherein the selected position along the transmission line and the impedance matching circuit are connected through at least one bond wire. 제2항에 있어서, 상기 임피던스 정합 회로는 커패시터를 포함하는 내부 정합 집적 회로.3. The internal matched integrated circuit of claim 2, wherein the impedance matching circuit comprises a capacitor. 제2항에 있어서, 상기 임피던스 정합 회로는 인덕터를 포함하는 내부 정합 집적 회로.3. The internal matched integrated circuit of claim 2, wherein the impedance matching circuit comprises an inductor. 제2항에 있어서, 상기 다이는 갈륨비소(GaAs) 소자를 포함하는 내부 정합 집적 회로.3. The internal matched integrated circuit of claim 2, wherein the die comprises a gallium arsenide (GaAs) device. 제2항에 있어서, 상기 다이는 실리콘 다이를 포함하는 내부 정합 집적 회로.3. The internal matched integrated circuit of claim 2, wherein the die comprises a silicon die. 제1항에 있어서, 상기 제1 전위는 접지핀을 포함하는 내부 정합 집적 회로.2. The internal matched integrated circuit of claim 1, wherein the first potential comprises a ground pin. 제1항에 있어서, 상기 패키지는 상기 리드 프레임을 실질적으로 싸는(encase) 내부 정합 집적 회로.The integrated circuit of claim 1, wherein the package substantially encases the lead frame. 제1항에 있어서, 상기 패키지는 플라스틱인 내부 정합 집적 회로.The internal matched integrated circuit of claim 1, wherein the package is plastic. 제1항에 있어서, 상기 다이는 상기 적어도 하나의 전송라인상으로 입력신호 또는 출력신호중 적어도 하나를 제공하는 내부 정합 집적 회로.2. The internal matched integrated circuit of claim 1, wherein the die provides at least one of an input signal or an output signal on the at least one transmission line. 제1항에 있어서, 상기 임피던스 정합 회로는 상기 다이상에 위치하는 내부 정합 집적 회로.2. The internal matched integrated circuit of claim 1, wherein the impedance matching circuit is located on the die. 내부 정합 집적 회로에 있어서,In an internal matching integrated circuit, 적어도 하나의 전송선과, 다이 패들(die paddle)과, 적어도 하나의 입력 신호 리드와, 상기 적어도 하나의 전송선으로 연결되는 적어도 하나의 출력 신호 리드를 포함하는 리드 프레임을 구비하는 패키지와,A package including a lead frame comprising at least one transmission line, a die paddle, at least one input signal lead, and at least one output signal lead connected to the at least one transmission line; 상기 패키지에 전기적으로 연결되며 상기 패키지내에 하우징되고 상기 적어도 하나의 전송선상으로 신호를 제공하는 다이를 포함하고,A die electrically connected to the package and housed in the package and providing a signal on the at least one transmission line, 상기 적어도 하나의 전송선상의 적어도 하나의 선택 위치는 임피던스 정합 회로를 통해 제1 전위에 전기적으로 연결되는At least one selected position on the at least one transmission line is electrically connected to a first potential via an impedance matching circuit. 내부 정합 집적 회로.Internal matching integrated circuit. 제12항에 있어서, 상기 임피던스 정합 회로는 상기 전송선을 따라 있는 상기 선택 위치에 연결되는 제1 리드와 상기 제1 전위에 연결되는 제2 리드를 구비하는 커패시터를 포함하는 내부 정합 집적 회로.13. The internal matched integrated circuit of claim 12, wherein the impedance matching circuit includes a capacitor having a first lead connected to the selected position along the transmission line and a second lead connected to the first potential. 제12항에 있어서, 상기 임피던스 정합 회로는 상기 전송선을 따라 있는 상기 선택 위치에 연결되는 제1 리드와, 상기 제1 전위에 연결되는 제2 리드를 구비하는 인덕터를 포함하는 내부 정합 집적 회로.13. The internal matched integrated circuit of claim 12, wherein the impedance matching circuit includes an inductor having a first lead connected to the selected position along the transmission line and a second lead connected to the first potential. 제12항에 있어서, 상기 임피던스 정합 회로는 상기 전송선을 따라 있는 상기 선택 위치에 연결되는 제1 리드와 상기 제1 전위에 연결되는 제2 리드를 포함하는 내부 정합 집적 회로.13. The internal matched integrated circuit of claim 12, wherein the impedance matching circuit includes a first lead connected to the selected position along the transmission line and a second lead connected to the first potential. 제12항에 있어서, 상기 전송선은 최소한 1 밀리미터 길이를 갖는 내부 정합 집적 회로.13. The internal matched integrated circuit of claim 12, wherein the transmission line has a length of at least 1 millimeter. 제12항에 있어서, 상기 제1 전위는 접지핀을 포함하는 내부 정합 집적 회로.13. The internal matched integrated circuit of claim 12, wherein the first potential comprises a ground pin. 제12항에 있어서, 상기 제1 전위는 상기 다이 패들을 포함하는 내부 정합 집적 회로.13. The internal matched integrated circuit of claim 12, wherein the first potential comprises the die paddle. 제12항에 있어서, 상기 패키지는 상기 리드 프레임을 실질적으로 싸는 내부 정합 집적 회로.13. The internal matched integrated circuit of claim 12, wherein the package substantially surrounds the lead frame. 제12항에 있어서, 상기 패키지는 플라스틱인 내부 정합 집적 회로.13. The internal matched integrated circuit of claim 12, wherein the package is plastic. 제12항에 있어서, 상기 다이는 상기 적어도 하나의 전송선상으로 입력 신호 또는 출력 신호중 적어도 하나를 제공하는 내부 정합 집적 회로.13. The internal matched integrated circuit of claim 12, wherein the die provides at least one of an input signal or an output signal on the at least one transmission line. 제12항에 있어서, 상기 다이는 갈륨 비소 또는 실리콘중 적어도 하나를 포함하는 내부 정합 집적 회로.13. The internal matched integrated circuit of claim 12 wherein the die comprises at least one of gallium arsenide or silicon. 내부 정합을 구비한 집적 회로를 형성하기 위해 다이를 하우징하고 이에 전기적으로 연결되는 집적 회로 패키지에 있어서, 상기 패키지는,An integrated circuit package housing and electrically connected to a die to form an integrated circuit with an internal match, the package comprising: 전송선과, 다이 패들과, 복수의 입력 리드와, 복수의 출력 리드를 포함하는 리드 프레임 - 상기 복수의 출력 리드중 적어도 하나는 상기 전송선에 연결되고, 상기 전송선을 따라 있는 적어도 하나의 선택 위치는 상기 패키지내에 포함된 임피던스 정합 회로를 통해 제1 전위에 전기적으로 연결되어 상기 전송선에 연결된 상기 적어도 하나의 출력 리드에 연관된 임피던스 정합망을 제공함-과,A lead frame comprising a transmission line, a die paddle, a plurality of input leads, and a plurality of output leads, wherein at least one of the plurality of output leads is connected to the transmission line and at least one selected position along the transmission line is Providing an impedance matching network electrically connected to a first potential via an impedance matching circuit contained in the package and associated with the at least one output lead connected to the transmission line; 상기 다이 패들과 상기 입력 리드와 상기 출력 리드는 노출시키면서, 상기 리드 프레임을 실질적으로 싸는 부재A member substantially enclosing the lead frame while exposing the die paddle, the input lead and the output lead 를 포함하는 집적 회로 패키지.Integrated circuit package comprising a. 제23항에 있어서, 상기 전송선은 에칭 또는 절반-에칭된 구리중 적어도 하나를 포하하는 집적 회로 패키지.24. The integrated circuit package of claim 23, wherein the transmission line contains at least one of etched or half-etched copper. 제23항에 있어서, 상기 임피던스 정합 회로는 커패시터를 포함하는 집적 회로 패키지.24. The integrated circuit package of claim 23 wherein the impedance matching circuit comprises a capacitor. 제23항에 있어서, 상기 임피던스 정합 회로는 인덕터를 포함하는 집적 회로 패키지.24. The integrated circuit package of claim 23, wherein the impedance matching circuit comprises an inductor. 제23항에 있어서, 상기 임피던스 정합 회로는 상기 집적 회로상에 위치하는 집적 회로 패키지.24. The integrated circuit package of claim 23 wherein the impedance matching circuit is located on the integrated circuit. 제23항에 있어서, 상기 제1 전기적 노드는 핀을 포함하고, 상기 임피던스 정합 회로는 상기 핀에 연결된 제1 리드를 구비한 커패시터와 상기 전송선상의 상기 선택 위치에 연결된 제2 리드를 포함하는 집적 회로 패키지.24. The integrated circuit of claim 23, wherein the first electrical node comprises a pin and the impedance matching circuit comprises a capacitor having a first lead connected to the pin and a second lead connected to the selected location on the transmission line. Circuit package. 제23항에 있어서, 상기 임피던스 정합 회로는 상기 다이 패들상에 탑재된 다이내에 위치하는 집적 회로 패키지.24. The integrated circuit package of claim 23, wherein the impedance matching circuit is located within a die mounted on the die paddle. 제23항에 있어서, 상기 제1 전기적 노드는 상기 다이 패들상에 위치하고, 상기 임피던스 정합 회로는 상기 다이 패들에 연결된 제1 리드와 상기 전송선상의 상기 선택 위치에 연결된 제2 리드를 구비하는 커패시터를 포함하는 집적 회로 패키지.24. The capacitor of claim 23 wherein the first electrical node is located on the die paddle and the impedance matching circuit comprises a capacitor having a first lead coupled to the die paddle and a second lead coupled to the selected location on the transmission line. An integrated circuit package that includes. 내부 정합 집적 회로에 있어서,In an internal matching integrated circuit, 복수개의 입력 신호 리드와, 복수개의 출력 신호 리드와, 상기 적어도 하나의 출력 신호 리드에 연결된 적어도 하나의 전송선을 포함하는 리드 프레임을 구비하는 패키지와,A package having a lead frame comprising a plurality of input signal leads, a plurality of output signal leads, and at least one transmission line connected to the at least one output signal lead; 상기 패키지에 전기적으로 연결되고 상기 패키지내에 하우징되며(housed) 상기 적어도 하나의 전송라인상으로 신호를 제공하는 다이를 포함하고,A die electrically connected to the package and housed in the package and providing a signal on the at least one transmission line, 상기 적어도 하나의 전송선을 따라 있는 선택 위치가 상기 집적 회로내에 위치한 임피던스 정합 회로를 통해 제1 전위에 전기적으로 연결되는 내부 정합 집적 회로.And a selection location along the at least one transmission line is electrically connected to a first potential via an impedance matching circuit located within the integrated circuit. 제31항에 있어서, 상기 패키지는 상기 리드 프레임을 실질적으로 싸는(encase) 내부 정합 집적 회로.32. The integrated circuit of claim 31, wherein the package substantially encases the lead frame. 제31항에 있어서, 상기 패키지는 플라스틱인 내부 정합 집적 회로.32. The integrated circuit of claim 31 wherein the package is plastic. 제31항에 있어서, 상기 다이는 상기 적어도 하나의 전송라인상으로 적어도 입력신호 또는 출력신호중 적어도 하나를 제공하는 내부 정합 집적 회로.32. The internal matched integrated circuit of claim 31 wherein the die provides at least one of an input signal or an output signal on the at least one transmission line. 제31항에 있어서, 상기 다이는 갈륨비소(GaAs)인 내부 정합 집적 회로.32. The internal matched integrated circuit of claim 31 wherein the die is gallium arsenide (GaAs). 제31항에 있어서, 상기 전송선은 에칭 또는 절반 에칭된 구리중 적어도 하나를 포함하는 내부 정합 집적 회로.The internal matched integrated circuit of claim 31 wherein the transmission line comprises at least one of etched or half etched copper. 제31항에 있어서, 상기 제1 전위는 접지핀을 포함하는 내부 정합 집적 회로.32. The internal matched integrated circuit of claim 31 wherein the first potential comprises a ground pin.
KR10-2004-7018046A 2002-05-09 2003-05-08 Integrated circuit with internal impedance matching circuit KR20050006241A (en)

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US10/142,250 US6828658B2 (en) 2002-05-09 2002-05-09 Package for integrated circuit with internal matching
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US10/427,330 US6903447B2 (en) 2002-05-09 2003-05-01 Apparatus, methods and articles of manufacture for packaging an integrated circuit with internal matching
US10/427,330 2003-05-01
PCT/US2003/014893 WO2003096439A1 (en) 2002-05-09 2003-05-08 Integrated circuit with internal impedance matching circuit

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