JP3208119B2 - High frequency semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency semiconductor device in which an FET used for mobile communication and the like is provided on a substrate such as GaAs, and more particularly to a measure for enabling a reduction in chip size. is there.

[0002]

2. Description of the Related Art In recent years, various mobile communication systems have been studied in various countries around the world, and a transmission power amplifying device corresponding to each system has been demanded.

Conventionally, as a power amplifying device for transmission in this field, a module using GaAs MESFET, JFET or HBT, an integrated integrated circuit (hereinafter referred to as MM)
Various types of configuration examples have been reported. For example, in the structure of a general MMIC, a transistor and a diode are formed on a GaAs substrate by utilizing the fact that a GaAs band gap is wide and the electrical conductivity of intrinsic GaAs is low even at room temperature, so that a semi-insulating GaAs substrate can be obtained. , And passive elements such as a spiral inductor, an interdigital capacitor, an MIM capacitor, a transmission line, and a thin film resistor are integrated and integrally formed. Also,
As disclosed in IEEE GaAs IC sympo. Tech. Digest pp. 53-56 1993, a module (multi-chip IC) in which an MMIC incorporating the above-described active and passive elements is formed inside a package and mounted on a substrate. Have been reported. Then, the MMIC or module is mounted on a substrate and applied to various uses. In other words, when assembled using a single transistor and individual components, as the operating frequency increases, large variations in microwave characteristics occur due to errors in the mounting positions of the components and variations in the characteristics of the components themselves, and the manufacturing yield is reduced. Although it is lowered, by configuring such an MMIC or module, predetermined characteristics can be stably exhibited.

[0004]

However, on the other hand,
The conventional MMICs and modules have the following problems. That is, since these are designed so as to be adapted only to a specific system, satisfactory characteristics may not be obtained when used at different operating frequencies. Further, the operation bias point or operation class (for example, class A, class B, etc.) of the FET cannot be changed from outside. For example, the above-mentioned IEEE GaAs IC sympo. Tech. Di.
In the module shown in gest. pp. 53-56 1993, it was impossible to change the operating frequency and the operating bias point from the outside because all the circuit blocks were formed inside the package.

In particular, in MMICs and modules, G
Since the area occupied by passive elements such as capacitors and inductances mounted on the aAs substrate is large, the chip size of an expensive GaAs substrate or the like generally used for high-frequency semiconductor devices becomes large, and it is difficult to reduce the manufacturing cost. There was a problem.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and a main object of the present invention is to provide a high frequency semiconductor device which often uses an expensive substrate by effectively utilizing the area of the substrate. An object of the present invention is to reduce the size and the manufacturing cost.

[0007]

The first high-frequency semiconductor device of the present invention, in order to solve the problem] is the high-frequency semiconductor device equipped with Integrated Circuit on a substrate, a gate electrode provided in the integrated circuit,
And F ET ing from the drain electrode and the source electrode, and a matching circuit for matching an RF signal passing through the FET provided in the integrated circuit, distributing near the four corners of the FET
And four source pads connected to the FET
And the end of the FET is close to the end of the substrate.
You .

Thus, the source pad occupying a large area is disposed in the region located at both ends in the longitudinal direction of the gate electrode of the FET and at the side of the substrate, so that a large space is created in the central region of the substrate. It becomes possible to close. That is, even if the area of the substrate is reduced, a space for arranging a matching circuit composed of a larger inductor or the like is secured, so that an expensive compound semiconductor substrate such as a semi-insulating GaAs substrate used for a high-frequency semiconductor device is consumed. Costs are reduced. Also, since the connection length between the wire and the wire used for grounding the source is shortened,
The source inductor is reduced, and the characteristics of the FET are improved.
In addition, by providing the source pads near the four corners of the FET, the locations of the source pads are dispersed, so that the space on the substrate is more effectively utilized.

[0009]

[0010]

In the first high-frequency semiconductor device, the matching circuit has a capacitor , and the capacitor of the matching circuit is connected to the source pad.

Thus, since the capacitor of the matching circuit connected to the ground of the substrate is arranged in the region adjacent to the source pad, the high-frequency signal of the matching circuit can escape to the ground via the source pad. . Therefore, there is no need to provide a separate ground for the capacitor, and space is saved.

[0013]

[0014]

[0015]

[0016]

[0017]

Embodiments of the present invention will be described below.

First Embodiment First, a two-stage power amplifier according to a first embodiment will be described with reference to FIGS.

FIG. 1 is a block diagram showing the configuration of the two-stage power amplifier according to the first embodiment. As shown in the figure, in the two-stage power amplifier according to the present embodiment, an MMIC 110 is mounted on a mounting substrate 100, and a drain bias circuit unit 101 and a gate bias circuit unit 102 are mounted on the mounting substrate 100. It is formed. This is a feature of the present embodiment.

In the MMIC 110, an input matching circuit 111, a front-stage FET 112, an interstage matching circuit 113, a rear-stage FET 114, an output matching circuit 115, a front-stage FET gate bias resistor 116, and a rear-stage FET gate bias resistor 117 are provided. Are arranged. It should be noted that all of these elements and circuit parts originally contribute to the matching and become a part of the matching circuit part. However, in order to clarify the effect here, they will be referred to as such. Also, each code 12
1, 122, 123, 124, 125, 126, 127
Are the first-stage FET drain voltage supply terminal, the second-stage FET drain voltage supply terminal, and the first-stage FET of the MMIC 110, respectively.
Gate voltage supply terminal, post-stage FET gate voltage supply terminal,
Indicates a ground terminal, signal input terminal, and signal output terminal.

Here, the configuration of each of the above matching circuits is as shown in FIGS. 6A, 6B and 6C as described later.

In the conventional module and MMIC, since these elements and circuit portions are all integrated in the package, it is difficult to externally adjust the operating frequency and the operating bias point. Then, as described below, they can be easily performed.

For example, the impedance of the drain bias circuit section 101 is a factor that affects the load impedance or the source impedance for the FET. Therefore, the operating frequency can be changed by changing the impedance of the drain bias circuit unit 101.

On the other hand, if such a process is performed using, for example, a single FET having no matching circuit, there is a possibility that the matching condition needs to be changed to change the entire matching circuit.
However, in the present embodiment, the drain bias circuit unit 10
Since the three matching circuit sections 111, 113, and 115 are designed in consideration of the impedance change amount of 1 in advance,
By simply changing the impedance of the drain bias circuit unit 101, it is possible to easily use the drain bias circuit unit 101 at a different frequency.

An example of a configuration for setting the impedance so as to satisfy the matching condition in accordance with the selection of the operating frequency will be described below.

FIGS. 2A and 2B are diagrams showing examples of the configuration of the drain bias circuit section 101 of the present embodiment.

In the example shown in FIG. 2A, the strip line 20 is a transmission line configured to transmit a high-frequency signal.
The drain bias circuit 101 is configured using the bypass capacitors 202 and 204 and the bypass capacitors 202 and 204. One end of each of the strip lines 201 and 203 has a drain power supply Vd.
d and the other end is the FE before and after the MMIC 110.
They are connected to T drain voltage supply terminals 121 and 122, respectively. The strip line 201 is provided with a capacitor mounting portion which is exposed in advance without being covered with a skin serving as a protective film, and according to an operating frequency when the MMIC 110 is used, the bypass capacitors 202 and 2 are provided.
The mounting position is determined so that the mounting position is determined and the mounting position is satisfied. Specifically, the impedance of the drain bias circuit 101 is MMIC1
It is determined by the strip line lengths L1 and L2 (see FIG. 2A) from 10 to the bypass capacitors 202 and 204, and these can be easily changed by changing the installation positions of the bypass capacitors 202 and 204.

In the example shown in FIG. 2B, the chip inductors 205 and 207 and the bypass capacitor 2 are respectively provided.
06 and 208 are arranged one by one to constitute the drain bias circuit 101. Each chip inductor 20
5 and 207 are configured to be attachable so that one end is connected to the drain power supply Vdd and the other end is connected to the front-stage or rear-stage FET drain voltage supply terminals 121 and 122 of the MMIC 110. Further, the chip inductor 205,
An inductor mounting portion for mounting bypass capacitors 206 and 208 is provided between the drain power supply side end of 207 and the ground. In this example, the impedance of the drain bias circuit 101 is
Is determined by the inductance value of 5,207,
The matching condition can be satisfied by attaching a chip inductor having an inductance value suitable for the operating frequency when the MMIC 110 is used.

The bypass capacitor 2 used here
Numerals 06 and 208 are inserted so that the impedance of the drain power supply Vdd or its fluctuation does not affect the FET inside the MMIC 110.
By designing the MMIC 110 such that the influence on the FET falls within an allowable range in consideration of the impedance of dd and its fluctuation, the bypass capacitors 206 and 208 can be omitted.

As described above, in the present embodiment, the following effects can be obtained by forming the drain bias circuit 101 not in the MMIC 110 but in the mounting substrate 100.

First, the process of changing the operating frequency, which has been difficult to integrate inside the MMIC 110, can be easily performed by forming the drain bias circuit portion 101 on the mounting substrate 100.

The drain bias circuit section 101 is set to M
By moving from the inside of the MIC 110 to the mounting substrate 100, the chip area of the MMIC 110 using an expensive GaAs substrate can be reduced, and the cost of the MMIC 110 itself can be reduced.

Further, the parasitic resistance of the drain bias circuit 101
The power supply voltage is applied to the drain electrode of the FET without being subjected to a voltage drop by the drain bias circuit 101 because the power supply voltage is greatly reduced as compared with the case where the power supply voltage is formed inside the internal circuit 110. Therefore, the deterioration of the saturation output characteristic is suppressed, and the decrease in gain and efficiency is suppressed as compared with the conventional MMIC.
The characteristics are improved on average, and the yield of the MMIC 110 is also improved.

In the present embodiment, the drain bias circuits 101 of each stage of the two-stage power amplifier are formed on the mounting substrate 100. However, the present invention is not limited to such an embodiment, and at least one of the two embodiments. Is the mounting board 100
What is necessary is just to be formed on the top. In an amplifier having one or three or more amplification stages, the same effect can be obtained even if one or several arbitrary portions are formed on a mounting substrate.

The same effect can be obtained by combining a drain bias circuit using a strip line and a bypass capacitor and a drain bias circuit using only a chip inductor and a bypass capacitor or a chip inductor in an amplifier having two or more stages.

Incidentally, the gate bias circuit 102 shown in FIG. 1 also affects the matching conditions similarly to the drain bias circuit section 101. However, not only the drain bias circuit section 101 but also the gate bias circuit section 102 needs to be adjusted at a high frequency. On the other hand, the necessity of performing the operation may lead to complicated processing. Thus, in the present embodiment, the gate bias circuit unit 102 performs only DC adjustment, and forms and arranges the gate bias resistors 116 and 117 inside the MMIC and separates them in high frequency so as not to affect high frequencies. By doing so, the effect can be ignored. In the configuration shown in FIG. 1, the gate bias resistor 11
6 and 117 are connected to the gate electrodes of the FETs 112 and 114, but are not directly connected to the gate electrodes but are connected to inductors or resistors connected to the gate electrodes.
The effect of transmitting a direct current and separating a high frequency is naturally obtained.

On the other hand, in the two-stage power amplifier having such a configuration, the FET gate voltage supply terminal 12
By applying a desired voltage to 3,124, the operating bias point can be changed. However, it may be cumbersome to prepare a variable voltage source only for gate bias adjustment and to adjust two adjustment points individually as in the first embodiment. Therefore, next, a configuration of a voltage source for supplying a fixed voltage and a gate bias circuit that can simultaneously adjust the operation bias points of two FETs by adjusting the resistance value at one location will be described below.

FIG. 3 is an electric circuit diagram of the gate bias circuit section 102 shown in FIG. As shown in the figure, fixed resistors 301 and 302 and a variable resistor 303 are arranged in series between a ground and a gate power supply Vgg, and a resistance division potential of this potential difference is applied to a gate voltage supply terminal 1 of the MMIC 110.
23 and 124. Here, the gate power supply Vgg is the second gate power supply according to claim 8, the variable resistor 303 is a second resistance member, the ground is the first gate power supply, and the fixed resistor 301 (or 302) is used. ) Corresponds to the first resistance member.

Next, in the present embodiment, the gate bias circuit 102 is provided not in the MMIC 110 but in the mounting substrate 100.
The following effects can be obtained by forming the inside.

For example, when the FET in the MMIC 110 is a depletion type FET and the gate power supply Vgg supplies a negative potential, the variable resistor 303 is used when the threshold value of the FET varies to the negative side. The drain current when no signal is input (hereinafter referred to as idle current) by setting the gate bias potential to the negative side by reducing the value of
Can be kept constant. The effect on the yield by keeping the idle current constant will be described later.

The bias point can be easily changed by the variable resistor 303 even for FETs having the same threshold value, for example, class A operation (50% Idss bias) and B level.
Class operation (0% Idss bias) in front stage FET, rear stage F
It is also possible to set ET individually. This means can be realized by a variable resistor.
It is difficult to form it inside, and it can be realized only by mounting it on a mounting board as in this embodiment.

In this embodiment, the variable resistor 303 is arranged in the gate bias circuit section 102. However, the present invention is not limited to this embodiment. MM as resistor mounting part
When the IC 110 is mounted on the mounting board 100, a fixed resistor having a resistance value suitable for the operating frequency to be used may be attached. With such a configuration, the same effect as that of the present embodiment can be obtained, but this can also be realized only by mounting the gate bias circuit unit 102 on the mounting substrate 100.

In this embodiment, since the three matching circuit portions 111, 113, and 115 are designed in consideration of the amount of change in the impedance of the FET due to the change in the gate bias, it is possible to easily use them under different gate bias conditions. It is possible.

Note that the same effect can be obtained in a power amplifier having one or three or more amplification stages for a gate bias circuit for applying a gate potential by resistance division. Also, it is not necessary to form and mount all the circuit elements constituting the gate bias circuit on the mounting board. At least the mounting section of the variable resistor or the fixed resistor is formed and mounted on the mounting board. MMI element
The same effect can be obtained even if it is configured to be formed on C. Further, in a power amplifier having a multi-stage configuration, a similar effect can be obtained by providing a gate bias circuit section for arbitrary several gate bias terminals.

Next, the effect of this embodiment will be described with reference to FIGS.
This will be described with reference to FIG.

FIG. 4 is a frequency characteristic diagram showing operating frequency variability when the strip line length of the preceding-stage drain bias circuit is changed. In FIG. 4, the horizontal axis represents the frequency (GH
z), and the vertical axis indicates forward gain S21 (dB), respectively.
Note that the input power is about 0 dBm. As shown in FIG. 4, when the strip line length of the pre-stage drain bias circuit 101 is 18 mm, the maximum point of the forward gain S21 is 1.8.
The maximum point of the forward gain S21 was changed to 2.10 by changing the strip line length to 2 mm.
It can be seen that the frequency shifts to GHz. This operation is the same in the subsequent-stage drain bias circuit. Therefore,
By using the power amplifier of the present invention, the high frequency characteristics of the power amplifier can be adjusted on the mounting board, so that the operating frequency can be changed without changing the mounting board or the MMIC. In other words, high-frequency adjustment can be performed after the MMIC and the mounting board are completed.
Even if a problem occurs due to deviation from 0Ω or insufficient grounding, it is possible to quickly respond. Also, the design margin of the MMIC and the mounting board at the time of designing the power amplifier increases,
It can be put to practical use in a short time.

FIG. 5 shows that the sum of the idle currents of the front-stage FET 112 and the rear-stage FET 114 is constant (150 m) using a variable resistor 303 for an MMIC having 23 samples.
FIG. 6 is a diagram illustrating a variation in operating current of the power amplifier when adjustment is performed to satisfy A) and a variation in operating current of the power amplifier when this process is not performed. The output power is 22 dBm. As shown in FIG. 5, by adjusting one portion of the variable resistor 303 of the gate bias circuit 102, the variation is reduced, the yield of the MMIC and the power amplifier is improved, and the cost is reduced. Needless to say, the operation class of the FET can be easily changed.

As described above, the respective effects can be obtained by providing the drain bias circuit portion 101 and the gate bias circuit portion 102 on the mounting substrate. However, a new effect can be obtained by having both of them. Occurs. For example, in a Japanese digital cordless telephone system called PHS used in the 1.9 GHz band, an FET is used in an operation close to class A because waveform distortion is a problem. On the other hand, in a digital cordless telephone system used in Europe called DECT which is used in the range of 1.88 GHz to 1.9 GHz, the waveform distortion is not so problematic, and is used in operation close to class B with good efficiency. Therefore, if both the drain bias circuit section and the gate bias circuit section are provided on the mounting substrate, it is possible to cope with both systems having different operation frequencies and operation classes.

As described in detail above, the effects of the power amplifier of the present embodiment are that the frequency can be adjusted on the mounting board, the characteristic deterioration due to the voltage drop is improved, the chip area of the MMIC is reduced, and the power is reduced. Increased amplifier yield, FE
The operation bias point of T is changed to increase the margin in the design of the mounting board. Table 1 shows a comparison with the case where the conventional MMIC and module are used.

[0050]

[Table 1]

Here, the conventional module indicates a module having a substrate on which a pattern for mounting individual components such as a chip component and an FET is formed in a package.

The same effect can be obtained with FETs other than GaAs MESFETs.

Here, the voltage of the power supply used in this embodiment,
The element values and characteristics of each element constituting the mounting substrate, the drain bias circuit section, the gate bias circuit section, and the MMIC are summarized below.

The voltage Vdd of the drain power supply shown in FIG. 2 is 3.5V. Further, the voltage Vg of the gate power supply shown in FIG.
g is -4.7V.

The mounting substrate 100 shown in FIG.
6. A 1 mm thick Teflon substrate.

The bypass capacitors 202 and 2 shown in FIG.
04, 206, and 208 are chip capacitors of 100 pF, and the strip lines 201 and 203 have a line width of 0.5.
mm, and the chip inductors 206, 208
A 6 mm × 0.8 mm type chip inductor was used.

The fixed resistors 301 and 302 shown in FIG. 3 use chip resistors of 2.2 kΩ and 150 Ω, respectively, and the variable range of the variable resistor 303 is 300 Ω to 5 kΩ.

The first-stage FET 112 and the second-stage FE shown in FIG.
T is a GaAs MESFET whose threshold value is-
3.0V, the gate width is 1mm for the first-stage FET, and the second-stage FE
At T, it is 4 mm. The gate bias resistor 116 of the front-stage FET 112 is 1 kΩ, and the gate bias resistor 117 of the rear-stage FET 114 is 2 kΩ.

The details of the input matching circuit 111, the interstage matching circuit 113, and the output matching circuit 115 shown in FIG.
A, FIG. 6B, and FIG. 6C, respectively, between the signal input terminal 126 and the pre-stage FET gate electrode 611, and the pre-stage FET drain electrode 612 and the post-stage FET gate electrode 6, respectively.
13, after-stage FET drain electrode and signal output terminal 127
The capacitor 601 is 1 pF, the inductor 602 is 6 nH, the capacitors 603 and 604 are 3 pF and 6 pF, respectively, the inductor 605 is 5 nH, the inductor 606 is 3 nH, and the capacitor 607 is 2 pF.

Although not shown because they do not contribute to the matching, an input coupling capacitor and an output coupling capacitor of 100 pF are mounted on the mounting board, respectively, as shown in FIGS.
Was measured.

(Second Embodiment) Next, a second embodiment will be described.

FIG. 7 is a diagram for explaining the arrangement of source pads of an MMIC which is a high-frequency semiconductor device used in the present invention.
FIG. 8 is a plan view of the MIC 700, and FIG.
7 shows details of the ESFET 702. Pre-stage FET, two MESFETs on a semi-insulating GaAs substrate
701 and a rear-stage FET 702 are arranged. Further, an input matching circuit 703 is arranged between the front-stage FET and the input pad 706, and the front-stage FET 701 and the rear-stage FET 7 are arranged.
02, an interstage matching circuit 704 is provided,
An output matching circuit 705 is provided between the ET 702 and the output pad 707.

The FETs 701 and 702 are provided with gate bias pads 711 and 721, drain pads 712 and 722, and source pads 713 and 723, respectively. The matching circuits 703, 704, 7
05 are spiral inductors 731 and 74, respectively.
1,751, MIM capacitors 732, 742, 74
3,752 and the like.

Here, the feature of the present embodiment is that
The source pad 723 of the ET 702 is arranged at two locations at both ends of the latter-stage FET 702 and at both ends of the semi-insulating GaAs substrate after a source wiring is drawn out in a direction substantially perpendicular to the longitudinal direction of the gate electrode. By arranging in this manner, the wire bonding operation can be performed smoothly, the grounding can be reliably performed, and the source inductance is reduced by shortening the connection length between the wiring and the wire used for grounding. Therefore, FET7
02 can be improved. Further, by disposing the source pad 723 near the corner of the semi-insulating GaAs substrate, an inductor having a large occupied area can be reduced.
It is possible to provide a margin for being arranged inside the As substrate, and it is possible to reduce the area by effectively using the semi-insulating GaAs substrate.

Further, each of the capacitors 732, 742, 74
By connecting 3,752 to the source pads 713,723, respectively, space can be saved.

Further, since the drain pad 722 for taking out an output from the drain to the outside is removed from the path from the drain of the subsequent-stage FET 702 to the output pad 127, the power supply voltage can be reduced without causing a voltage drop due to passing through the inductor 751. There is an advantage that a reduction in the level of the voltage applied to the drain electrode and input to the drain electrode can be suppressed as much as possible.

As shown in FIG. 8, the rear FET 702 has a source electrode 7 on a gate electrode 725.
26, and a drain electrode 727 is further stacked thereon, but the gate electrode 725 and the source electrode 726 have the same leading direction. By drawing the gate electrode 725 to the source side in this manner, deterioration of characteristics due to an increase in gate-drain capacitance is avoided.

(Third Embodiment) Next, a two-stage power amplifier according to a third embodiment will be described.

FIG. 9 is an electric circuit diagram showing the configuration of the two-stage power amplifier according to the present embodiment. The gate bias setting FET is provided in the MMIC 110 according to the first embodiment shown in FIG.
911 is added, and further, a gate terminal 921, a source terminal 922, and a drain terminal 923 are provided, mounted on the mounting substrate 100, and the configuration of the gate bias circuit unit 902 formed is changed. here,
Elements and circuit portions denoted by the same reference numerals as those shown in FIG. 1 are the same as the above-described elements and circuit portions, and have the same configurations and functions.

The gate bias setting FET 902 in the present embodiment comprises a front-stage FET 112 and a rear-stage FET 11
4 is manufactured on the same chip under the same diffusion conditions as that of Example 4, and thus has the same variation as the variation of the idle current of the front-stage FET 112 and the rear-stage FET 114 due to the variation of the threshold value and the mutual conductance (gm). . The same applies to the temperature dependency. That is, the first-stage FE
If the idle current of T112 and the subsequent FET 114 is larger than the set target value, the gate bias setting FET 90
When the idle currents of the front-stage FET 112 and the rear-stage FET 114 are smaller than the set target value, the idle current of the gate bias setting FET 911 also becomes small. That is, using this correlation,
As will be described below, in addition to the effects described in the first embodiment, the first-stage FET 112
In addition, the variation in the idle current of the rear-stage FET 114 is suppressed.

FIG. 10 shows the configuration of the gate bias circuit 902 shown in FIG.
FIG. 9 is an electric circuit diagram showing a connection relationship with a gate bias setting FET 911 in C110. Gate terminal 921 and source terminal 92 of gate bias setting FET 911
2 is connected to the negative power supply Vgg, and the drain terminal 923 is grounded via the fixed resistor 1002 and the variable resistor 1001. Also, the first-stage FET gate voltage supply terminal 1
Reference numeral 23 is connected to the drain terminal 923 of the gate bias setting FET 911, and the latter-stage FET drain voltage supply terminal 124 is connected to a signal line between the fixed resistor 1002 and the variable resistor 1001. Here, the gate power supply Vgg is the first gate power supply according to claim 8, the gate bias setting FET 911 is a first resistance member (see claim 18), the ground is the second gate power supply, The variable resistor 1001 corresponds to a second resistance member.

With this configuration, the first-stage FET 1
When the idle currents of the FET 12 and the subsequent FET 114 are excessive, a large drain current of the FET 911 for setting the gate bias also flows. And the respective idle currents decrease. Therefore, variation in idle current can be suppressed. On the other hand, even when the idle current is too small, the idle current increases due to the reverse operation, so that variations in the idle current can be suppressed.

The effect of suppressing the variation of the idle current as described above is specifically described in the gate bias setting FET 9.
11 can be realized by appropriately setting the values of the drain current, the fixed resistor 1002, and the variable resistor 1001.

The first-stage FET 112 and the second-stage FET 11
In order to individually apply the gate voltages of
2, the fixed resistor 1002 may be omitted if the idle current is set at the same gate voltage. If the operation class is not changed, the variable resistor 1001 may be a fixed resistor.

Further, the gate bias setting FET 9
11 and the front-stage FET gate voltage supply terminal 123 and the rear-stage F
The arrangement relationship with the ET gate voltage supply terminal 124 is shown in FIG.
It is not limited to the arrangement relationship shown in
The source / drain of the gate bias setting FET 911 is connected between the gate voltage supply terminal 124 and the second gate power supply unit (that is, the FET 911 is interposed), and the pre-stage FET voltage supply terminal 123 is connected via a variable resistor. It may be connected to the second gate power supply.

(Fourth Embodiment) Next, a fourth embodiment will be described with reference to FIG.

As shown in FIG. 11, the configuration of the MMIC 110 of the two-stage power amplifier according to the present embodiment is the same as the configuration of the MMIC 110 in the third embodiment. In the present embodiment, in the gate bias circuit section, the third
In addition to the same configuration as the embodiment, the gate bias setting FE
A fixed resistor 1101 is inserted in the source of T911.

Generally, there is an upper limit to the current value that can be passed to the negative power supply Vgg. However, if the gate width of the gate bias setting FET 911 is too large, the third value shown in FIG.
In the configuration of the gate bias circuit unit in the embodiment, there is a possibility that a current exceeding the upper limit value flows into the negative power supply Vgg.

However, in the configuration shown in FIG. 11 of the present embodiment, the source voltage of the gate bias setting FET 911 can be made higher than the gate voltage by utilizing the voltage drop by the fixed resistor 1101. Therefore, the drain current can be reduced, and the current flowing to the negative power supply Vgg can be reduced, thereby ensuring reliability.

In the basic configuration shown in FIG. 9, the gate terminal 921, the source terminal 922 and the drain terminal 923 of the gate bias setting FET 911 are
Since all of the gate voltage supply terminal 123 and the latter-stage FET gate voltage supply terminal 124 are formed on the mounting substrate 100 outside the MMIC 110, an arbitrary circuit can be configured by the gate bias circuit unit 902, It is possible to set the current value of the gate bias setting FET and the resistance value of each resistor while checking the operation of
The design margin of the MMIC is increased.

By the way, in mobile communication equipment, there are many cases where it is desired to reduce the number of components on a mounting board for miniaturization. In such a case, FIG. 12 and FIG.
3, the configuration of the fifth, sixth, and seventh embodiments shown in FIG.

(Fifth Embodiment) FIG. 12 is an electric circuit diagram showing a configuration of a part of an MMIC 110 and a gate bias circuit according to a fifth embodiment. In the present embodiment, the arranged members are the same as the circuit configuration shown in FIG. 10 of the fourth embodiment, except that the gate electrode and the source electrode of the gate bias setting FET 911 are connected inside the MMIC 110. With this configuration, the work for connecting them on the mounting board 100 becomes unnecessary, and the MM
Since the number of pads on the IC 110 is reduced by one, the MMIC
The chip size of the chip 110 can be reduced.

(Sixth Embodiment) FIG. 13 is an electric circuit diagram showing a configuration of a part of an MMIC 110 and a gate bias circuit section according to a sixth embodiment. In the present embodiment, FIG.
In the circuit shown in FIG. 2, the fixed resistor 1002 mounted on the mounting substrate 100 is integrated in the MMIC 110, and the front-stage FET gate voltage supply terminal and the rear-stage FET gate voltage supply terminal are integrated in the MMIC 110. This configuration eliminates the need for mounting and connecting them on the mounting board 100, and further reduces the number of pads on the MMIC 110 by two.
The number of locations can be reduced.

(Seventh Embodiment) FIG. 14 is an electric circuit diagram showing a configuration of a part of an MMIC 110 and a gate bias circuit section according to a seventh embodiment. In the present embodiment, FIG.
In the circuit shown in FIG. 1, the fixed resistors 1002 and 1101 mounted on the mounting substrate 100 are integrated on the MMIC, and the first-stage FET gate voltage supply terminal and the second-stage FET gate voltage supply terminal are integrated in the MMIC. With this configuration, it is not necessary to mount and connect them on the mounting board, and the number of pads on the MMIC can be reduced by three as compared with the configuration of FIG.

The variable resistor 1001 needs to be mounted on the mounting substrate 100 in order to change the operation class of the FET. For example, in the fourth to seventh embodiments, the variable resistor 1001 has an Since there is an effect of suppressing the current fluctuation, if the operation class is not changed, it may be formed of a fixed resistor and mounted on the mounting substrate 100 or integrated in the MMIC 110.

(Eighth Embodiment) FIG. 15 is an electric circuit diagram showing a configuration of a two-stage power amplifier according to an eighth embodiment.
In the present embodiment, the gate bias circuit unit is configured as the MMIC 11
It is accumulated in 0. That is, since it is assumed that the operation class is not changed, no variable resistor is provided. The two fixed resistors 12 are connected between the drain of the gate bias setting FET 911 and the ground terminal 125.
01, 1202 and each fixed resistor 1201,
It has a configuration in which a subsequent-stage FET gate voltage supply terminal is connected to a signal line between 1202.

In the present embodiment, the gate bias circuit section has a standard specification and is incorporated in the MMIC 110, and the drain bias circuit section 101 has a configuration that can be changed as in the first embodiment, so that the minimum required Only the part needs to be mounted on the mounting board 100, and there is an advantage that a simple configuration is sufficient.

(Ninth Embodiment) FIG. 16 is an electric circuit diagram showing a configuration of a two-stage power amplifier according to a ninth embodiment.
In the present embodiment, the gate bias circuit section is integrated in the MMIC 110 as in the eighth embodiment, and a fixed resistor is connected to the source of the gate bias setting FET 911 as in the configuration shown in FIG. 11 of the fourth embodiment. Vessel 110
1 is inserted. Therefore, in the present embodiment, there is an advantage that variations in idle current can be more reliably suppressed with a simple configuration.

In the third to ninth embodiments, the chip size is 1 mm × 2 mm. The gate widths of the date bias setting FETs are two types, 50 μm and 5 μm.

[0090]

According to the high frequency semiconductor device of the present invention,
By devising the arrangement of each member in the MMIC, it is possible to reduce the cost of an expensive compound semiconductor substrate such as a semi-insulating GaAs substrate used for a high-frequency semiconductor device.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a power amplifier according to a first embodiment.

FIG. 2 is an electric circuit diagram of a drain bias circuit unit according to the first embodiment.

FIG. 3 is an electric circuit diagram of a gate bias circuit unit according to the first embodiment. .

FIG. 4 is a frequency characteristic diagram showing operating frequency variability in the first embodiment.

FIG. 5 is a characteristic distribution diagram showing yield improvement in the first embodiment.

FIG. 6 is an electric circuit diagram of an input matching circuit unit, an interstage matching circuit unit, and an output matching circuit unit according to the first embodiment.

FIG. 7 is a plan view of an MMIC according to a second embodiment.

FIG. 8 illustrates an ME included in the MMIC according to the second embodiment.
It is a top view of SFET.

FIG. 9 is a block diagram illustrating a configuration of a power amplifier according to a third embodiment.

FIG. 10 is an electric circuit diagram of a gate bias circuit unit according to a third embodiment.

FIG. 11 is an electric circuit diagram of a gate bias circuit section according to a fourth embodiment.

FIG. 12 is an electric circuit diagram of a gate bias circuit section according to a fifth embodiment.

FIG. 13 is an electric circuit diagram of a gate bias circuit section according to a sixth embodiment.

FIG. 14 is an electric circuit diagram of a gate bias circuit section according to a seventh embodiment.

FIG. 15 is a block diagram illustrating a configuration of a power amplifier according to an eighth embodiment.

FIG. 16 is a block diagram illustrating a configuration of a power amplifier according to a ninth embodiment.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 Mounting substrate 101 Drain bias circuit section 102 Gate bias circuit section 110 MMIC 111 Input matching circuit section 112 Pre-stage FET 113 Interstage matching circuit section 114 Post-stage FET 115 Output matching circuit section 116 Gate bias resistor 117 Gate bias resistor 121 Front-stage FET Drain voltage supply terminal 122 Second-stage FET drain voltage supply terminal 123 First-stage FET gate voltage supply terminal 124 Second-stage FET gate voltage supply terminal 125 Ground terminal 126 Signal input terminal 127 Signal output terminal

────────────────────────────────────────────────── ─── Continuation of the front page (72) Osamu Ishikawa, Inventor 1006, Oazadoma, Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (56) References JP-A-60-87502 (JP, A) JP-A-1- 228302 (JP, A) Fully open 1988-165,631 (JP, U) Fully open, 60-192513 (JP, U) Fully open, 62-95325 (JP, U) Really open, 61-75625 (JP, U) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03F 3/60

Claims (3)

(57) [Claims] To 1. A substrate in the high-frequency semiconductor device equipped with Integrated Circuit, said integrated circuit gate electrode provided in a F ET ing from the drain electrode and the source electrode, the FET provided in the integrated circuit A matching circuit for matching a high-frequency signal passing through the FET, and a matching circuit arranged near four corners of the FET and connected to the FET.
A high-frequency semiconductor device comprising four source pads, wherein an end of the FET and an end of the substrate are close to each other . 2. The high-frequency semiconductor device according to claim 1 , wherein a source electrode of said FET is grounded via a ground of said source pad. 3. The high-frequency semiconductor device according to claim 2, wherein the matching circuit has a capacitor , and the capacitor of the matching circuit is connected to the source pad.
High-frequency semiconductor device characterized by being.