JP3438953B2 - Bias circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bias circuit for applying a bias voltage to a signal processing circuit which processes a signal having a predetermined frequency.

[0002]

2. Description of the Related Art Mobile communication continues to be in the limelight for the future, as car telephones have come into commercial use all over the world. Mobile communication occupies a very wide field, and there are various types such as car phones, commercial radios, multi-channel access (MCA), and personal radios, and each of them has been rapidly developing in recent years. For this reason, radio waves of a very large number of frequencies are required for these communications, and the frequency of radio waves used in mobile communication is 800 to
It is moving from 900 MHz to the quasi-microwave band. Therefore, a signal processing circuit such as an amplifier and a mixer used in the portable device is composed of a microwave integrated circuit. In a microwave integrated circuit, an active element and a passive element are formed on a dielectric substrate made of semiconductor or the like. The active element includes a field effect transistor (hereinafter referred to as FET) and the like, and the passive element includes a distributed constant circuit such as wiring and a lumped constant circuit such as an inductor and a capacitor.

In any of the above communications,
From the viewpoint of improving convenience, portable devices have been made smaller, lighter, and have lower power consumption. Along with this, the batteries used as power sources for portable devices are becoming smaller and lighter. Therefore, it is desired that signal processing circuits such as amplifiers and mixers used in portable devices operate at low voltage.

However, a personal handyphone system (hereinafter referred to as PHS) using a frequency of 1.9 GHz or a personal digital cellular (hereinafter referred to as PDC) using a frequency of 1.5 GHz has a large transmission output, and a PDC has a transmission output of 0. It is defined as 0.8 W, and in PHS, it is defined as 80 mW in peak power. Therefore, when the amplifier or the mixer is operated at a low voltage, the current consumption increases in order to obtain the transmission output as described above.

In general, a bias circuit of an active element used in an amplifier or a mixer is composed of an inductor and a resistor having a considerably large value. For example, in an amplifier that processes a signal having a frequency of 1.9 GHz, an inductor of 68 nH or a resistor of 3 kΩ is used, for example.

In particular, when the operating current increases with a decrease in the voltage, if the bias circuit is composed of a resistor, the decrease in the bias voltage due to the voltage drop increases. for that reason,
It is necessary to construct the bias circuit with a large value inductor instead of a resistor.

A conventional bias circuit will be described by taking a three-stage power amplifier as an example. FIG. 4 is a circuit diagram showing a configuration of a three-stage power amplifier for PHS transmission including a conventional bias circuit. This power amplifier has a frequency of 1.9 GHz
Power amplification of the signal.

In FIG. 4, an input signal is applied to the input terminal 21, and an amplified output signal is obtained from the output terminal 22. A gate bias voltage V _GG of -1V is applied to the gate bias application terminal 23, and a drain bias voltage V _DD of 3V is applied to the drain bias application terminal 24.

The input terminal 21 is connected to the gate (node A) of the first-stage FET 1 via the capacitor C1 and the inductor L1. The gate of FET1 is inductor L2
And to the ground terminal via the capacitor C2.
The capacitors C1 and C2 and the inductors L1 and L2 form an input matching circuit. Inductor L2 and capacitor C
The node between 2 and 2 is connected to the gate bias applying terminal 23 via the resistor R1. The drain (node A ′) of FET1 is connected to the external terminal 25, and the source is connected to the ground terminal.

The drain of the first-stage FET 1 and the second-stage FE
A DC cut capacitor C3 is connected between the gate of T2 (node B). The gate of FET2 is a resistor R
2 and the biasing capacitor C4 to be connected to the ground terminal. A node between the resistor R2 and the capacitor C4 is connected to the gate bias applying terminal 23. FET
The drain (node B ') of 2 is connected to the external terminal 26, and the source is connected to the ground terminal.

The drain of the second-stage FET 2 and the third-stage F
A DC cut capacitor C5 is connected between the gate (node C) of ET3. The gate of the FET3 is connected to the ground terminal via the resistor R3 and the bias capacitor C6. A node between the resistor R3 and the capacitor C6 is connected to the gate bias applying terminal 23. FE
The drain (node C ′) of T3 is connected to the external terminal 27, and the source is connected to the ground terminal.

The drain of the third-stage FET 3 is connected to the output terminal 22 via the inductor L3. Output terminal 22
Is connected to the ground terminal via the capacitor C7. The inductor L3 and the capacitor C7 form an output matching circuit. The above circuit elements are formed on the chip 20.

External chip inductors Lc1, Lc2 and Lc3 are connected between the external terminals 25, 26 and 27 and the drain bias applying terminal 24, respectively. An external chip capacitor Cs1 is connected between the gate bias applying terminal 23 and the ground terminal, and an external chip capacitor Cs2 is connected between the drain bias applying terminal 24 and the ground terminal.

The resistors R1, R2 and R3 form a gate bias circuit, and apply the gate bias voltage V _GG applied to the gate bias applying terminal 23 to the gates of the FETs 1, 2, 3 respectively. External chip inductors Lc1, L
c2 and Lc3 form a drain bias circuit, and the drain bias voltage V _DD applied to the drain bias application terminal 24 is applied to the drains of the FETs 1, 2, and 3, respectively.

[0015]

In the above three-stage power amplifier, since the input impedances of the FETs 1, 2 and 3 are very large, the gate bias circuit has a resistor R1 having a high resistance value (for example, 2.5 KΩ or more). , R2, R
3 can be used. As a result, the impedance of the gate bias circuit seen from the nodes A, B, C becomes very large. As a result, high-frequency signals do not leak to the gate bias circuit, and FET1,
It will be input to a few gates.

On the other hand, in a normal analog circuit, its operating current flows through the drain of the FET as it is. That is,
In the power amplifier of FIG. 4, operating currents flow through the drains of FETs 1, 2, and 3 as they are. Therefore, FET
1, 2, 3 drains and drain bias application terminals 24
If a resistor is used between and, power will be consumed by the resistor, so the resistor cannot be used in the drain bias circuit. Therefore, as shown in FIG. 4, the drain bias circuit is configured using the external chip inductors Lc1, Lc2, and Lc3.

When the impedance of the drain bias circuit viewed from the nodes A ', B', C'is formed by an inductor, the impedance Z is expressed by the following equation. Z = 2πfL Here, L represents the value of the inductor, and f represents the frequency. Therefore, the lower the frequency, the higher the value of the inductor required to obtain a given impedance.
For example, in a PHS using a frequency of 1.9 GHz,
At least 10 to obtain an impedance of 1.2 KΩ
An inductor of 0 nH is needed.

As a result, the chip size of each inductor becomes very large, and further, if there are three active elements like the power amplifier of FIG. 4, three inductors are required. Therefore, the drain bias circuit requires a large occupied area and cannot be monolithic with the power amplifier.

FIG. 5 is a diagram showing an example of a layout when the three-stage power amplifier of FIG. 4 is monolithically mounted and mounted on a printed circuit board. The three-stage power amplifier and gate bias circuit of FIG. 4 are monolithicized on chip 20,
It is sealed in the resin mold package 28. An input terminal 21, an output terminal 22, a gate bias applying terminal 23, a drain bias applying terminal 24, and a ground terminal GND are formed on the printed circuit board 200. An external chip capacitor Cs1 is connected between the gate bias applying terminal 23 and the ground terminal GND, and the drain bias applying terminal 2
An external chip capacitor Cs2 is connected between 4 and the ground terminal GND. In addition, the resin mold package 2
External chip inductors L between the external terminals 25, 26 and 27 of FIG.
c1, Lc2 and Lc3 are connected.

Since the gate bias circuit is composed of the resistors R1, R2 and R3 as described above, it can be formed in the chip 20. Therefore, the gate bias application terminal 23 may be connected to one external terminal of the resin mold package 28.

On the other hand, the drain bias circuit is
As described above, it is composed of three large inductors of 100 nH or more. For example, the value of the inductor that can be built in on the GaAs substrate is 10 nH, and even in this case, 3
Occupy an area of 00 × 300 μm ² . Therefore, in the three-stage power amplifier of FIG.
Since it cannot be formed on the upper side, the drain bias applying terminal 24 has three external chip inductors Lc.
1, Lc2 and Lc3 are connected to three external terminals 25, 26 and 27 of the resin mold package 28, respectively. That is, in order to apply the drain bias voltage V _DD , the three external terminals 2 are provided on the resin mold package 28.
5, 26, 27 are required.

As described above, since the drain bias circuit cannot be monolithic together with the three-stage power amplifier, the mounting area on the printed circuit board becomes large and the number of parts also increases. As a result, there is a problem in that the electronic device cannot be downsized and the reliability cannot be improved.

An object of the present invention is to provide a bias circuit which occupies a small area and can be formed on the same chip as a signal processing circuit.

[0024]

A bias circuit according to the present invention is a bias circuit for applying a bias voltage to a signal processing circuit for processing a signal of a predetermined frequency by a plurality of active elements. A plurality of filter means for blocking passage of a signal having a predetermined frequency are connected in series to the voltage applying terminal, and each active element is connected to the predetermined filter means.

The filter means may consist of a parallel resonant circuit including an inductor and a capacitor. In a bias circuit for applying a bias voltage to an amplifier that amplifies a signal of a predetermined frequency by a plurality of stages of active elements,
Multiple parallel resonance circuits corresponding to multiple stages of active elements are connected in series between the active element of the first stage and the voltage application terminal to which the bias voltage is applied, and the active elements of each stage are connected to the corresponding parallel resonance circuit. It is preferable to connect.

[0026]

In the bias circuit according to the present invention, a plurality of filter means are connected in series to the voltage application terminal to which the bias voltage is applied. As a result, the impedance when the voltage applying terminal side is viewed from the input end of each filter means becomes larger as the filter means is farther from the voltage applying terminal. Therefore, each active element can be connected to a desired filter means according to its impedance so that the signal current does not leak from each active element to the voltage application terminal.
Therefore, it becomes possible to apply a desired bias voltage to each of the plurality of active elements with a minimum of filter means. As a result, the occupied area of the bias circuit is reduced,
The bias circuit can be formed on the same chip as the signal processing circuit.

When each filter means is composed of a parallel resonant circuit including an inductor and a capacitor, a desired impedance can be realized with a small inductor and a small capacitor. Therefore, in this case, the occupied area of each parallel resonant circuit is particularly reduced, and the bias circuit can be formed on the same chip as the signal processing circuit.

In particular, in an amplifier including a plurality of stages of active elements, the input impedance of each active element increases as it approaches the first stage and decreases as it approaches the final stage. Therefore, a plurality of parallel resonant circuits corresponding to a plurality of stages of active elements are connected in series between the first stage active element and the voltage application terminal,
By connecting the active elements in each stage to the corresponding parallel resonant circuits, desired impedances can be obtained between each active element and the voltage application terminal. Therefore,
Each parallel resonant circuit can be configured with a small inductor and capacitor, and the area occupied by each parallel resonant circuit is reduced. As a result, the bias circuit can be formed on the same chip as the amplifier.

[0029]

1 is a circuit diagram showing a configuration of a three-stage power amplifier for PHS transmission including a bias circuit according to an embodiment of the present invention. This 3-stage power amplifier has a frequency of 1.9 GHz.
Power amplification of the signal.

In FIG. 1, an input signal is applied to the input terminal 11, and an amplified output signal is obtained from the output terminal 12. A gate bias voltage V _GG of -1V is applied to the gate bias application terminal 13, and a drain bias voltage V _DD of 3V is applied to the drain bias application terminal 14.

FETs 1, 2, 3 and capacitors C1 to C7
And the structure of the gate bias circuit composed of the resistors R1, R2 and R3 and the three-stage power amplifier composed of the inductors Lc1, Lc2 and Lc3 are the same as those of the three-stage power amplifier and the gate bias circuit shown in FIG. Is.

In this embodiment, a parallel resonance circuit 41 including an inductor L4 and a capacitor C8 is connected between the drain of FET1 and the drain of FET2.
Further, a parallel resonance circuit 42 including an inductor L5 and a capacitor C9 is connected between the drain of FET2 and the drain of FET3. Further, an inductor L is provided between the drain of the FET 3 and the drain bias applying terminal 14.
A parallel resonant circuit 43 including 6 and a capacitor C10 is connected. In this way, the three parallel resonant circuits 41, 42, 43 connected in series form a drain bias circuit.

If each of the parallel resonant circuits 41, 42, 43 resonates at a frequency of 1.9 GHz, the parallel resonant circuits 41, 4
The impedance of 2, 43 is 1.9GHz for each frequency.
It becomes maximum at z. Therefore, passage of a signal with a frequency of 1.9 GHz can be blocked. That is, the parallel resonant circuits 41, 42 and 43 each function as filter means.

Normally, in a multi-stage transmission power amplifier, an input signal is sequentially amplified by a multi-stage active element, and the output level of the final-stage active element is maximized. Therefore, even in the three-stage power amplifier of FIG.
The output level increases in the order of T2 and FET3, and the gate widths of the FETs 1, 2, and 3 are set to correspond to this. For example, the gate width of FET1 is 400 μm, F
The gate width of ET2 is set to 800 μm, and the gate width of FET3 is set to 1.6 mm. As a result, the input impedance of FET1 is the highest, the input impedance of FET2 is the next highest, and the input impedance of FET3 is the lowest.

For example, the second stage FET from the node A '
The impedance when looking at the side of 2 is about 100Ω, the impedance when looking at the side of the FET3 of the third stage from the node B ′ is about 50Ω, and the side of the output terminal 12 is seen from the node C ′. If the load impedance is about 20
It becomes Ω. That is, the drain bias circuit connected to the FET1 of the first stage needs the highest impedance, and the drain bias circuit connected to the FET2 of the second stage may have a lower impedance than that of the first stage and is connected to the FET3 of the third stage. The drain bias circuit having the lowest impedance is sufficient.

In the drain bias circuit 4 of FIG. 1, three parallel resonance circuits 41, 42, 43 are provided between the drain of the first stage FET 1 and the drain bias application terminal 14.
Since they are connected in series, the highest impedance is obtained in the first stage. Further, since the two parallel resonant circuits 42 and 43 are connected between the drain of the FET 2 of the second stage and the drain bias applying terminal 14, the impedance of the second stage is lower than that of the first stage. Further, since only one parallel resonant circuit 43 is connected between the drain of the FET 3 in the third stage and the drain bias application terminal 14, the lowest impedance is obtained in the third stage. With such a configuration, the impedances required by the respective FETs 1, 2, 3 can be obtained by the relatively small value inductors L4, L5, L6 and the relatively small value capacitors C8, C9, C10.

Further, the parallel resonance circuit 43 is composed of FETs 1, 2,
3 are commonly used, and the parallel resonance circuit 42 is composed of FETs 1 and 2.
, The drain bias circuit 4 for the three FETs 1, 2, and 3 is configured with a minimum number of circuit elements.

Therefore, the drain bias circuit 4 is set to 3
It can be monolithic in chip 10 with stage power amplifiers and gate bias circuits. Here, as an example, the values of the capacitors C1, C4, and C6 are 1 to 2 p.
F, the value of the capacitor C2 is 10 to 20 pF, the value of the capacitors C3 and C5 is 3 to 10 pF,
The value of the capacitor C7 is 2-5 pF. The value of the inductor L1 is 2 to 3 nH, the value of the inductor L2 is 3 to 5 nH, and the value of the inductor L3 is 1 to 3 nH.
Is. Furthermore, the values of resistors R1, R2 and R3 are 2.5K.
Ω or more. External chip capacitors Cs1, Cs
The value of 2 is 1000 pF.

In this case, the values of the inductors L4, L5 and L6 of the drain bias circuit 4 are set to 2.35 nH, and the values of the capacitors C8, C9 and C10 are set to 3 p, for example.
Set to F.

When the parallel resonant circuit is monolithic, for example, a spiral inductor is used as the inductor. 2A shows a spiral inductor, and FIG. 2B shows an equivalent circuit of a parallel resonant circuit using the spiral inductor.

The spiral inductor shown in FIG. 2A is formed of a metal film. Since the film thickness of the metal film can be increased only up to several μm, a resistance component is generated. Therefore, the equivalent circuit of the parallel resonance circuit has a capacitor C and an inductor L as shown in FIG.
A resistance R is also included. Therefore, the impedance of the parallel resonant circuit at resonance is ideally infinite,
The actual impedance Z is expressed by the following equation.

Z = L / (RC) For example, when the value of the inductor L is 2.35 nH, the value of the capacitor C is 3 pF, and the value of the resistor R is 2Ω, the impedance Z is 391Ω. Thus, by using the parallel resonant circuit, it is possible to realize a high impedance for a specific single frequency with a relatively small inductor and capacitor. In the case of this embodiment, an impedance of about 1.2 KΩ can be obtained by connecting the three parallel resonant circuits 41, 42, 43 in series.

FIG. 3 is a diagram showing an example of a layout when the three-stage power amplifier of FIG. 1 is made monolithic and mounted on a printed circuit board. The three-stage power amplifier, gate bias circuit and drain bias circuit 4 of FIG.
Monolithic on top, resin mold package 16
Sealed inside. Input terminal 1 on the printed circuit board 100
1, an output terminal 12, a gate bias applying terminal 13, a drain bias applying terminal 14 and a ground terminal GND are formed. Gate bias application terminal 13 and ground terminal GND
An external chip capacitor Cs1 is connected between
An external chip capacitor Cs2 is connected between the drain bias application terminal 14 and the ground terminal GND.

As described above, the drain bias circuit 4 is monolithically formed on the chip 10. Therefore, by connecting the gate bias applying terminal 14 to only one external terminal 15 of the resin mold package 16, three FETs are formed.
The drain bias voltage V _DD can be supplied to 1, 2, and 3.

As described above, in the above embodiment, the drain bias circuit 4 can be made monolithic.
Two chip capacitors Cs1 and C as external parts
Only s2. As a result, the mounting area on the printed circuit board 100 is reduced and the number of parts is reduced. Therefore, the electronic device can be downsized and the reliability can be improved.

When the chip area is reduced, feedback is applied to the amplifier due to the parasitic capacitance between the gate and drain of the FET. However, in the three-stage power amplifier of FIG.
A parallel resonant circuit 41 is inserted between the gate and drain of
Since the parallel resonant circuit 42 is inserted between the gate and drain of the FET3, the parallel resonant circuits 41 and 42 improve the isolation between the gate and drain of the FETs 2 and 3 and minimize the increase in the feedback amount. be able to. Therefore, problems such as a decrease in the gain of the amplifier due to an increase in the feedback amount do not occur.

It should be noted that the inductors Lc1, Lc2 of FIG.
When one parallel resonant circuit is connected instead of Lc3, 1 KΩ unless the Q value of the parallel resonant circuit is considerably improved.
Impedance of a certain degree cannot be obtained. Therefore, it is practically difficult to configure the drain bias circuit with one parallel resonance circuit.

On the other hand, in this embodiment, the FE of the first stage is
Since the three parallel resonance circuits 41, 42, 43 are connected in series between the drain of T1 and the drain bias application terminal 14, the impedance of each parallel resonance circuit 41, 42, 43 may be low.

In the above embodiments, the case where the bias circuit of the present invention is applied to a three-stage power amplifier has been described. However, the bias circuit of the present invention can be applied to other amplifiers, and further, such as a mixer. It can also be applied to other signal processing circuits. When the bias circuit of the present invention is applied to a mixer, contrary to the above embodiment, the active element at the first stage is connected to the parallel resonance circuit closest to the drain bias application terminal, and the drain bias is applied in order as the final stage is approached. Connect to a parallel resonant circuit far from the terminals.

[0050]

As described above, according to the present invention, since the bias circuit is constituted by the minimum filter means composed of, for example, the parallel resonance circuit, the occupied area of the bias circuit is reduced, and the bias circuit is replaced with the signal processing circuit. Can be formed on the same chip.

Therefore, the number of parts is reduced, and the electronic device can be downsized and its reliability can be improved.

[Brief description of drawings]

FIG. 1 includes 3 including a bias circuit according to an embodiment of the present invention.
It is a circuit diagram which shows the structure of a stage power amplifier.

FIG. 2 is a diagram showing a spiral inductor used in the bias circuit of FIG. 1 and an equivalent circuit diagram of a parallel resonance circuit using the spiral inductor.

FIG. 3 is a diagram showing an example of a layout when the three-stage power amplifier of FIG. 1 is monolithic and mounted on a printed board.

FIG. 4 is a circuit diagram showing a configuration of a three-stage power amplifier including a conventional bias circuit.

5 is a diagram showing an example of a layout when the three-stage power amplifier of FIG. 4 is monolithic and mounted on a printed circuit board.

[Explanation of symbols]

1,2,3 FET 4 bias circuit 10 chips 11 input terminals 12 output terminals 13 Gate bias application terminal 14 Drain bias application terminal 15 External terminal 41, 42, 43 Parallel resonant circuit L4, L5, L6 inductor C8, C9, C10 capacitors 100 printed circuit board In the drawings, the same reference numerals indicate the same or corresponding parts.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yatsuo Harada 2-5-5 Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd. (56) Reference JP-A-63-309009 (JP, A) JP-A-5-315857 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03F 1/00-3/72 H01P 1/00

Claims (2)

(57) [Claims] 1. A bias circuit for applying a bias voltage to a signal processing circuit for processing a signal of a predetermined frequency by a plurality of active elements connected in a plurality of stages , wherein a voltage application terminal to which the bias voltage is applied a plurality of filter means for blocking passage of the predetermined frequency of the signal
Connected in series, each of the plurality of filter means includes an inductor and a key.
A parallel resonant circuit including a capacitor, and the predetermined electrode of the active element at each stage is
A bias circuit characterized by being connected to one end of each stage . 2. A bias circuit for applying a bias voltage to an amplifier for amplifying a signal of a predetermined frequency by a plurality of active elements connected in a plurality of stages, wherein the first stage active element and the voltage to which the bias voltage is applied are applied. A plurality of parallel resonant circuits corresponding to the plurality of stages of active elements are connected in series between the application terminal and each of the plurality of filter means.
A parallel resonant circuit including a capacitor, and the predetermined electrodes of the active elements in each stage correspond to each other.
A bias circuit that is connected to one end of a parallel resonant circuit.