KR20050002031A - Method of forming isolation layer for semiconductor device - Google Patents
Method of forming isolation layer for semiconductor device Download PDFInfo
- Publication number
- KR20050002031A KR20050002031A KR1020030043077A KR20030043077A KR20050002031A KR 20050002031 A KR20050002031 A KR 20050002031A KR 1020030043077 A KR1020030043077 A KR 1020030043077A KR 20030043077 A KR20030043077 A KR 20030043077A KR 20050002031 A KR20050002031 A KR 20050002031A
- Authority
- KR
- South Korea
- Prior art keywords
- etching
- forming
- trench
- hard mask
- semiconductor device
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000002955 isolation Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 150000004767 nitrides Chemical class 0.000 claims abstract description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 14
- 238000001039 wet etching Methods 0.000 claims description 10
- 239000011259 mixed solution Substances 0.000 claims description 8
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 abstract 2
- 239000007789 gas Substances 0.000 abstract 2
- 238000000059 patterning Methods 0.000 abstract 2
- 229920000642 polymer Polymers 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로, 특히 에스티아이(STI; Shallow Trench Isolation) 공정을 적용한 반도체 소자의 소자분리막 형성방법에 관한 것이다.The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a method of forming a device isolation film of a semiconductor device using a shallow trench isolation (STI) process.
반도체 소자의 고집적화에 따른 패턴의 미세화에 대응하기 위하여, 소자분리막을 STI 공정에 의해 형성하고 있다. 통상적으로, STI 공정은 질화막 등의 하드 마스크를 이용하여 기판에 얕은 깊이의 트렌치를 형성하고 이 트렌치에 산화막을 매립시킨 후 평탄화하는 과정으로 이루어진다.In order to cope with the miniaturization of the pattern resulting from the high integration of semiconductor devices, an element isolation film is formed by an STI process. In general, the STI process uses a hard mask such as a nitride film to form a trench having a shallow depth in the substrate, and fills an oxide film in the trench and then flattens it.
최근에는 STI 공정 후 야기되는 모트(moat) 발생을 최소화하기 위하여, 질화막 식각시 CF4/CHF3개스비를 변화시켜 질화막 식각부위에 폴리머(polymer)를 형성시켜 트렌치 형성을 위한 기판의 식각시 식각배리어로서 작용하도록 하여 트렌치 최상부 코너에 라운드(round)를 형성하고 있다.Recently, in order to minimize the occurrence of moat caused after the STI process, by changing the CF 4 / CHF 3 gas ratio during nitride etching, a polymer is formed on the nitride etching region to etch the substrate for etching the substrate for trench formation. It forms a round at the top corner of the trench to act as a.
그러나, 이러한 라운드 형성은 0.115㎛ 이상 기술의 소자에서는 적용이 가능하지만, 예컨대 0.10㎛ 이하 기술의 고집적 소자에서는 폴리머 형성에 의한 액티브 영역의 CD(Critical Dimension) 증가로 인하여 트렌치의 공간마진(space margin)이 감소하고 어스펙트비(aspect ratio)가 높아지기 때문에, 트렌치 내부에 산화막을 완전히 매립하기가 어려우므로 적용이 용이하지 못하다. 따라서, 모트 발생으로 인해 야기되는 소자 특성 저하 등의 문제를 해결하기가 어렵다.However, such round formation can be applied to devices having a technology of 0.115 μm or more, but for high integration devices having a technology of 0.10 μm or less, for example, the space margin of the trench is increased due to an increase in the CD (critical dimension) of the active region due to polymer formation. Since this decreases and the aspect ratio is high, it is difficult to fully embed the oxide film inside the trench, and thus it is not easy to apply. Therefore, it is difficult to solve problems such as deterioration of device characteristics caused by mote generation.
본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 0.10㎛ 이하 기술의 고집적 소자에서 모트 발생을 최소화하면서 트렌치 내부의 산화막 매립특성을 향상시켜 소자의 특성을 향상시킬 수 있는 반도체 소자의 소자분리막 형성방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, a semiconductor device that can improve the characteristics of the device by improving the oxide buried characteristics inside the trench while minimizing the generation of the mott in a highly integrated device of 0.10㎛ or less technology The purpose of the present invention is to provide a method for forming a device isolation film.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 소자분리막 형성방법을 위하 단면도.1A to 1D are cross-sectional views for forming a device isolation film of a semiconductor device according to an embodiment of the present invention.
※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing
10 : 반도체 기판 11 : 패드 산화막10 semiconductor substrate 11 pad oxide film
12 : 패드 질화막 13 : O-BARC막12 pad nitride film 13 O-BARC film
14 : 포토레지스트 패턴 15 : 트렌치14 photoresist pattern 15 trench
16 : 월산화막16: moon oxide film
상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 상기의 본 발명의 목적은 반도체 기판 상에 패드 산화막과 패드 질화막을 순차적으로 증착하는 단계; 패드 질화막 상부에 포토레지스트 패턴을 형성하는 단계; 포토레지스트 패턴을 마스크로하여 기판의 일부가 노출되도록 패드 질화막과 패드 산화막을 식각하여 측부가 수직 프로파일을 가지는 하드 마스크를 형성하는 단계; 포토레지스트 패턴을 제거하는 단계; 하드 마스크를 이용하여 노출된 기판을 식각하여 소정 깊이의 트렌치를 형성하는 단계; 트렌치 표면을 소정 부분 식각하여 트렌치 최상부 코너에 라운드를 형성하는 단계; 및 트렌치 및 하드 마스크 표면에 월산화막을 형성하는 단계를 포함하는 반도체 소자의 소자분리막 형성방법에 의해 달성될 수 있다.According to an aspect of the present invention for achieving the above technical problem, the object of the present invention comprises the steps of sequentially depositing a pad oxide film and a pad nitride film on a semiconductor substrate; Forming a photoresist pattern on the pad nitride film; Etching the pad nitride film and the pad oxide film to expose a portion of the substrate using the photoresist pattern as a mask to form a hard mask having a vertical profile at a side thereof; Removing the photoresist pattern; Etching the exposed substrate using a hard mask to form a trench having a predetermined depth; Etching a portion of the trench surface to form a round in the top corner of the trench; And forming a monthly oxide film on the surfaces of the trench and the hard mask.
바람직하게, 하드 마스크를 형성하는 단계에서, 식각은 CF4/CHF3의 혼합개스를 이용한 건식식각으로 수행하는데, 이때 CF4/CHF3개스비가 1이 넘도록 조절한다.Preferably, in the step of forming a hard mask, etching is carried out to a dry etching using a mixed gas of CF 4 / CHF 3, this time is adjusted for more than a CF 4 / CHF 3 gaeseubi 1.
또한, 라운드를 형성하는 단계에서, 식각은 HNO3/HF의 혼합용액을 이용한 습식식각으로 수행하는데, 이때 HF 농도는 0.1 내지 1%로 유지한다.In addition, in the step of forming a round, etching is performed by wet etching using a mixed solution of HNO 3 / HF, wherein the HF concentration is maintained at 0.1 to 1%.
또한, 습식식각시 HNO3/HF의 혼합용액에 DI 워터를 첨가할 수도 있는데, 이때 DI 워터의 농도는 10 내지 60% 정도로 조절한다.In addition, DI water may be added to the mixed solution of HNO 3 / HF during wet etching, wherein the concentration of DI water is adjusted to about 10 to 60%.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 소자분리막 형성방법을 설명하기 위한 단면도이다.1A to 1D are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 실리콘과 같은 반도체 기판(10) 상에 패드 산화막(11)과 패드 질화막(12)을 순차적으로 증착하고, 패드 질화막(12) 상부에 유기-저부ARC(Organic Bottom Anti Reflective Coating; O-BARC)막(13)을 형성한다. 여기서, 패드 질화막(12)은 식각 및 평탄화시 배리어로서 충분히 작용하도록 약 1000Å 이상의 두께로 증착한다. 그 다음, O-BARC막(13) 상부에 ISO 마스크를 이용한 포토리소그라피 공정에 의해 포토레지스트 패턴(14)을 형성한다.Referring to FIG. 1A, a pad oxide layer 11 and a pad nitride layer 12 are sequentially deposited on a semiconductor substrate 10 such as silicon, and an organic bottom anti reflective coating is formed on the pad nitride layer 12. O-BARC) film 13 is formed. Here, the pad nitride film 12 is deposited to a thickness of about 1000 GPa or more so as to sufficiently function as a barrier during etching and planarization. Next, the photoresist pattern 14 is formed on the O-BARC film 13 by a photolithography process using an ISO mask.
도 1b를 참조하면, 포토레지스트 패턴(14)을 마스크로하여 기판(10)의 일부가 노출되도록 O-BARC막(13), 패드 질화막(12) 및 패드 산화막(11)을 건식식각에 의해 식각하여 패드 질화막(12)/패드 산화막(11)으로 이루어진 하드 마스크(100)를 형성하고, 공지된 방법에 의해 포토레지스트 패턴(14)과 O-BARC막(13)을 제거한다. 바람직하게, 건식식각은 종래와 마찬가지로 식각개스로서 CF4/CHF3의 혼합개스를 사용하되 폴리머를 형성시키는 CHF3개스의 플로우속도(flow rate)를 낮추거나 CF4개스의 플로우 속도를 증가시켜 CF4/CHF3개스비가 1이 넘도록 하여 수행함으로써 폴리머 발생을 최소화하여 하드 마스크(100) 측부가 수직 프로파일(vertical profile)을 갖도록 한다. 그 다음, 하드 마스크(100)를 이용하여 노출된 기판(10)을 식각하여 소정 깊이의 트렌치(15)를 형성한다. 즉, 폴리머 발생을 최소화하는 조건으로 식각을 수행하고 포토레지스트 패턴(14) 및 O-BARC막(13)의 제거 후 트렌치(15)를 형성하기 때문에 트렌치(15)의 공간마진을 충분히 확보하면서 어스펙트비 증가를 방지할 수 있게 된다.Referring to FIG. 1B, the O-BARC layer 13, the pad nitride layer 12, and the pad oxide layer 11 are etched by dry etching so that a portion of the substrate 10 is exposed using the photoresist pattern 14 as a mask. By forming a hard mask 100 made of the pad nitride film 12 / pad oxide film 11, the photoresist pattern 14 and the O-BARC film 13 are removed by a known method. Preferably, dry etching is performed by using a mixed gas of CF 4 / CHF 3 as an etching gas as in the related art, but lowering the flow rate of the CHF 3 gas forming the polymer or increasing the flow rate of CF 4 gas. Performing a 4 / CHF 3 gas ratio of greater than 1 minimizes polymer generation so that the hard mask 100 side has a vertical profile. Next, the exposed substrate 10 is etched using the hard mask 100 to form the trench 15 having a predetermined depth. That is, since the etching is performed under the condition of minimizing polymer generation and the trench 15 is formed after the photoresist pattern 14 and the O-BARC film 13 are removed, the space 15 of the trench 15 is sufficiently secured. This can prevent an increase in the spec ratio.
도 1c를 참조하면, 질화막 및 산화막으로 이루어진 하드 마스크(100)에 비해 실리콘으로 이루어진 기판(10)에 대하여 높은 식각율을 가지는 식각액, 바람직하게 HNO3/HF의 혼합용액을 이용한 습식식각으로 트렌치(15) 표면을 소정 부분 식각하여 트렌치(15) 최상부 코너에 라운드(200)를 형성하여 이후 모트 발생을 최소화한다. 바람직하게, 습식식각은 웨이퍼(기판)의 균일도(uniformity) 향상을 위하여 스핀형(spin type) 습식 스테이션(station)을 사용하거나 트렌치(15) 측벽의 기판(10) 식각을 용이하게 하도록 딥(dip) 방식의 습식 스테이션을 사용하여 수행한다. 또한, HNO3/HF의 혼합용액의 HF 농도를 0.1 내지 1%의 저농도로 유지하여 트렌치(15) 표면이 약 50 내지 100Å 정도 제거되도록 한다. 또한, HNO3/HF의 혼합용액에 DI(deionized) 워터(water)를 첨가하여 희석시켜 라운드 정도 및 식각율을 제어할 수도 있는데, 이때 DI 워터의 농도는 10 내지 60% 정도로 조절하는 것이 바람직하다.Referring to FIG. 1C, the trench may be formed by wet etching using an etching solution having a high etching rate, preferably a mixed solution of HNO 3 / HF, with respect to the substrate 10 made of silicon, compared to the hard mask 100 made of a nitride film and an oxide film. 15) The surface is partially etched to form a round 200 at the top corner of the trench 15 to minimize later generation of motes. Preferably, the wet etching uses a spin type wet station to improve the uniformity of the wafer (substrate) or a dip to facilitate etching of the substrate 10 on the sidewalls of the trench 15. Is performed using a wet type station. In addition, the HF concentration of the mixed solution of HNO 3 / HF is maintained at a low concentration of 0.1 to 1% to remove the surface of the trench 15 to about 50 to 100 kPa. In addition, the degree of rounding and etching rate may be controlled by adding and diluting DI (deionized) water to the mixed solution of HNO 3 / HF, wherein the concentration of DI water is preferably adjusted to about 10 to 60%. .
그 다음, 도 1d에 도시된 바와 같이, 월산화(wall oxidation) 공정을 수행하여 트렌치(15) 및 하드 마스크(100) 표면에 50 내지 100Å 두께의 월산화막(16)을 형성한다. 상기 HNO3/HF의 혼합용액을 이용한 습식식각은 기판(10) 표면의 산화와제거를 반복하기 때문에, 통상의 식각 손상(damage) 제거를 위하여 트렌치(15) 형성 후 수행되는 월희생산화(wall sacrificial oxidation) 공정과 월산화막 공정전 수행되는 사전세정(pre-cleaning) 공정 등을 생략하고 바로 월산화막(16)을 형성하는 것이 가능하다. 그 후, 도시되지는 않았지만, 트렌치(15)에 매립되도록 매립용 산화막을 증착하고 화학기계연마(Chemical Mechnaicl Polishing; CMP) 공정에 의해 평탄화를 수행하여 소자분리막을 형성한다.Next, as illustrated in FIG. 1D, a wall oxidation process is performed to form a monthly oxide film 16 having a thickness of 50 to 100 μm on the surface of the trench 15 and the hard mask 100. The wet etching using the mixed solution of HNO 3 / HF repeats the oxidation and removal of the surface of the substrate 10, so that the wall production is performed after the trench 15 is formed to remove the etching damage. It is possible to form the monthly oxide film 16 immediately by omitting a sacrificial oxidation process and a pre-cleaning process performed before the monthly oxide film process. Thereafter, although not shown, a buried oxide film is deposited so as to be embedded in the trench 15 and planarization is performed by a chemical mechanical polishing (CMP) process to form a device isolation film.
상기 실시예에 의하면, 하드 마스크인 질화막 식각시 폴리머 발생이 최소화되도록 식각개스비를 조절하고 트렌치 형성을 포토레지스트 패턴 제거 후에 수행함에 따라 트렌치의 공간마진을 충분히 확보하면서 어스펙트비를 증가를 방지할 수 있으므로 후속 트렌치 내부로의 산화막 매립시 우수한 매립 특성을 얻을 수 있게 된다. 또한, 트렌치 형성 후 습식식각에 의해 트렌치 최상부 코너에 라운드를 형성함에 따라 STI 공정 후의 모트 발생을 최소화할 수 있으므로, 모트로 인해 야기되는 문턱전압(Threshold Voltage; Vth) 등의 소자 특성 저하를 방지할 수 있게 된다.According to the above embodiment, by adjusting the etching gas ratio to minimize the generation of polymer during the etching of the nitride film, which is a hard mask, and forming the trench after removing the photoresist pattern, it is possible to prevent the increase in the aspect ratio while sufficiently securing the space margin of the trench. Therefore, excellent embedding characteristics can be obtained when the oxide film is embedded into the subsequent trench. In addition, since the generation of the mott after the STI process can be minimized by forming a round at the top corner of the trench by wet etching after the trench formation, it is possible to prevent deterioration of device characteristics such as threshold voltage (Vth) caused by the mott. It becomes possible.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
전술한 본 발명은 0.10㎛ 이하 기술의 고집적 소자에서 STI 공정에 의한 소자분리막 형성시 모트 발생을 최소화할 수 있을 뿐만 아니라 트렌치 내부의 산화막 매립특성을 향상시킬 수 있으므로 소자 특성을 향상시킬 수 있다.The present invention described above can minimize the generation of the mott when forming the device isolation film by the STI process in the highly integrated device having a technology of 0.10 μm or less, and can improve the device characteristics because the oxide buried property in the trench can be improved.
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2003-0043077A KR100500926B1 (en) | 2003-06-30 | 2003-06-30 | Method of forming isolation layer for semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2003-0043077A KR100500926B1 (en) | 2003-06-30 | 2003-06-30 | Method of forming isolation layer for semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20050002031A true KR20050002031A (en) | 2005-01-07 |
KR100500926B1 KR100500926B1 (en) | 2005-07-14 |
Family
ID=37217595
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR10-2003-0043077A KR100500926B1 (en) | 2003-06-30 | 2003-06-30 | Method of forming isolation layer for semiconductor device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100500926B1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20170036905A (en) | 2015-09-24 | 2017-04-04 | 신재철 | A vegetation soundproof panel nature-condion with rainbow |
-
2003
- 2003-06-30 KR KR10-2003-0043077A patent/KR100500926B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR100500926B1 (en) | 2005-07-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100275730B1 (en) | Trench isolating method | |
US6649489B1 (en) | Poly etching solution to improve silicon trench for low STI profile | |
KR100518587B1 (en) | Fabrication Method for shallow trench isolation structure and microelectronic device having the same structure | |
KR100500926B1 (en) | Method of forming isolation layer for semiconductor device | |
KR100451518B1 (en) | Isolation method of semiconductor device using shallow trench isolation process | |
KR20060002138A (en) | Method of manufacturing semiconductor device | |
KR100861290B1 (en) | Method for forming isolation layer of semiconductor device | |
KR20050028618A (en) | Method for forming isolation layer of semiconductor device | |
KR20050012584A (en) | Method for forming isolation layer of semiconductor device | |
KR100561524B1 (en) | Method for fabricating shallow trench isolation | |
KR100800106B1 (en) | Method for forming trench isolation layer in semiconductor device | |
KR100984854B1 (en) | Method for forming element isolation layer of semiconductor device | |
KR20040105980A (en) | The method for forming shallow trench isolation in semiconductor device | |
KR20030045216A (en) | Method of manufacturing a trench in semiconductor device | |
KR100499409B1 (en) | Method for forming shallow trench isolation film in semiconductor device | |
KR20040004988A (en) | Method for forming isolation layer of semiconductor device | |
KR100480625B1 (en) | Method for forming trench isolation and semiconductor device comprising the same | |
KR20050059703A (en) | Method for forming isolation layer of semiconductor device | |
KR20080001340A (en) | Method for forming isolation layer in semiconductor device | |
KR20040060219A (en) | Method for fabricating of semiconductor device | |
KR20070010532A (en) | Method for fabrication of semiconductor device | |
KR20050012652A (en) | Method for forming element isolation layer of semiconductor device | |
KR20030008053A (en) | Method for forming isolation layer in semiconductor device | |
KR20050012660A (en) | Method for forming element isolation layer of semiconductor device | |
KR20030050683A (en) | Method for forming isolation layer in semiconductor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20100624 Year of fee payment: 6 |
|
LAPS | Lapse due to unpaid annual fee |