KR20040060219A - Method for fabricating of semiconductor device - Google Patents

Method for fabricating of semiconductor device Download PDF

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Publication number
KR20040060219A
KR20040060219A KR1020020086761A KR20020086761A KR20040060219A KR 20040060219 A KR20040060219 A KR 20040060219A KR 1020020086761 A KR1020020086761 A KR 1020020086761A KR 20020086761 A KR20020086761 A KR 20020086761A KR 20040060219 A KR20040060219 A KR 20040060219A
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South Korea
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oxide film
cvd
semiconductor device
pad
manufacturing
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KR1020020086761A
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Korean (ko)
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KR100895388B1 (en
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윤효섭
정영석
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent moat by forming a CVD oxide layer at lower of a linear nitride layer. CONSTITUTION: A trench(16) is formed by selectively etching a substrate(10) using a pad oxide and nitride pattern as a mask. A well oxide layer(18), a CVD oxide layer(30) and a linear nitride layer(20) are sequentially formed on the trench. A field oxide layer(22) is then formed in the trench and planarized. The pad nitride pattern is removed.

Description

반도체소자의 제조방법{METHOD FOR FABRICATING OF SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD FOR FABRICATING OF SEMICONDUCTOR DEVICE}

본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 선형 질화막을 사용하는 고밀도 소자의 얕은 트랜치 소자분리(shallow trench isolation; 이하 STI라 칭함) 공정에서 소자분리산화막 에지 부분의 모트(moat)에서의 잔류물에 의한 단락을 방지하여 공정수율 및 소자의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to retaining in a moat of an edge portion of a device isolation oxide film in a shallow trench isolation (STI) process of a high density device using a linear nitride film. The present invention relates to a method for manufacturing a semiconductor device which can prevent a short circuit caused by water and improve process yield and device reliability.

일반적으로 반도체소자는 소자가 형성되는 활성영역과, 이들을 분리하는 소자분리 영역으로 구분할 수 있으며, 소자분리영역이 소자의 전체 면적에서 차지하는 비율이 크므로 소자의 고집적화를 위해서는 소자분리영역의 축소가 필요하다.In general, semiconductor devices can be divided into active regions in which devices are formed and device isolation regions separating them, and since the device isolation region occupies a large portion of the entire area of the device, it is necessary to reduce the device isolation region for high integration. Do.

고집적 소자에서는 기판에 얕은 트랜치를 형성하고 이를 절연막으로 메우는 STI 방법이 많이 사용되고 있다.In high-integration devices, STI methods that form shallow trenches in a substrate and fill them with insulating films are widely used.

도 1a 내지 도 1e는 종래 기술에 따른 반도체소자의 제조 공정도이다.1A to 1E are manufacturing process diagrams of a semiconductor device according to the prior art.

먼저, 반도체기판(10)상에 패드산화막(12)과 패드질화막(14)을 순차적으로 형성하고, 소자분리 마스크(도시되지 않음)를 이용한 사진식각 공정으로 상기 패드질화막(14)과 패드산화막(12)을 식각하여 패드질화막(14) 패턴과 패드산화막(12) 패턴을 형성한다.First, the pad oxide layer 12 and the pad nitride layer 14 are sequentially formed on the semiconductor substrate 10, and the pad nitride layer 14 and the pad oxide layer 14 are formed by a photolithography process using an element isolation mask (not shown). 12) is etched to form a pad nitride film 14 pattern and a pad oxide film 12 pattern.

그다음 상기 패드질화막(14) 패턴에 의해 노출되어있는 반도체기판(10)을 일정 깊이 식각하여 트랜치(16)를 형성하고, 상기 구조의 전표면에 웰 산화막(18)과 선형 질화막(20)을 형성한 후, 상기 구조의 전표면에 필드산화막(22)을 도포하여 트랜치(16)를 메운다. (도 1a 참조).Then, the trench 16 is formed by etching the semiconductor substrate 10 exposed by the pad nitride layer 14 pattern to a predetermined depth, and the well oxide layer 18 and the linear nitride layer 20 are formed on the entire surface of the structure. After that, the field oxide film 22 is applied to the entire surface of the structure to fill the trench 16. (See FIG. 1A).

그후 화학-기계적 연마(chemical mechanical polishing ; 이하 CMP라 칭함) 등의 방법으로 상기 필드산화막(22)을 평탄화시킨다. (도 1b 참조).Thereafter, the field oxide film 22 is planarized by a method such as chemical mechanical polishing (hereinafter referred to as CMP). (See FIG. 1B).

그다음 상기 남아있는 패드질화막(14)을 제거하고, (도 1c 참조), 상기 패드산화막(12)을 제거하고, 문턱전압 조절용 산화막(24)을 반도체기판(10)상에 형성한다. (도 1d 참조).Then, the remaining pad nitride film 14 is removed (see FIG. 1C), the pad oxide film 12 is removed, and the threshold voltage adjusting oxide film 24 is formed on the semiconductor substrate 10. (See FIG. 1D).

그후 상기 산화막(24)을 제거하고, 반도체기판(10) 상에 게이트산화막(26)을 형성한다. 이때 상기 필드산화막(22)의 에지 부분에 깊이 M의 모트(28)가 형성된다. (도 1e 참조).Thereafter, the oxide film 24 is removed, and a gate oxide film 26 is formed on the semiconductor substrate 10. At this time, a moat 28 having a depth M is formed at an edge portion of the field oxide layer 22. (See FIG. 1E).

상기와 같은 종래 기술에 따른 반도체 소자의 제조방법은 고집적 소자에 사용되는 선형 질화막을 이용한 STI 공정에서는 패드질화막의 제거 공정시 선형질화막도 함께 식각되고, 후속 세정 공정에서도 산화막과 질화막의 식각선택비 차이로 인하여 필드산화막 에지 부분에 모트가 발생하게 되고, 상기 모트는 후속 게이트전극 패턴닝 공정시 식각 잔류물이 남는 자리를 제공하여 게이트전극의 원활한 패턴닝을 방해하고, 라인의 단락을 유발할 수도 있으며, 소자의 리플레쉬 특성도 저하시키는 등의 문제점이 있다.In the method of manufacturing a semiconductor device according to the prior art as described above, in the STI process using the linear nitride film used in the highly integrated device, the linear nitride film is also etched during the pad nitride film removal process, and the etching selectivity difference between the oxide film and the nitride film in the subsequent cleaning process is also different. Due to the mott generated in the edge portion of the field oxide layer, the mott may provide a place where the etch residue remains during the subsequent gate electrode patterning process to prevent smooth patterning of the gate electrode, and may cause a short circuit of the line. There is a problem such as lowering the refresh characteristics of the device.

본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본발명의 목적은 선형 질화막을 이용하는 STI 공정에서 선형 질화막의 하부에 CVD 산화막을 형성하여 평탄화 공정시 선형질화막이 트랜치 보다 높게 남도록하여 모트의 깊이를 감소시켜 모트에 의한 후속 식각 공정에서의 식각잔류물 발생을 방지하여 라인 단락의 원을 제거하고, 소자의 리플레쉬 특성을 향상시킬 수 있는 반도체소자의 제조방법을 제공함에 있다.The present invention is to solve the above problems, an object of the present invention is to form a CVD oxide film on the lower portion of the linear nitride film in the STI process using a linear nitride film so that the linear nitride film remains higher than the trench during the planarization process to increase the depth of the mote The present invention provides a method of manufacturing a semiconductor device capable of reducing the occurrence of etch residues in a subsequent etching process by a mote to remove circles of line short circuits and improving refresh characteristics of the device.

도 1a 내지 도 1e는 종래 기술에 따른 반도체소자의 제조공정도.1A to 1E are manufacturing process diagrams of a semiconductor device according to the prior art.

도 2a 내지 도 2e는 본 발명에 따른 반도체소자의 제조공정도.2a to 2e is a manufacturing process diagram of a semiconductor device according to the present invention.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

10 : 반도체기판 12 : 패드산화막10 semiconductor substrate 12 pad oxide film

14 : 패드질화막 16 : 트랜치14 pad nitride film 16 trench

18 : 웰 산화막 20 : 선형 질화막18 well oxide film 20 linear nitride film

22 : 필드산화막 24 : 문턱전압 조절용 산화막22: field oxide film 24: oxide film for adjusting the threshold voltage

26 : 게이트산화막 28 : 모트26 gate oxide film 28 mort

30 : CVD 산화막30: CVD oxide film

본발명은 상기와 같은 목적을 달성하기 위한 것으로서, 본발명에 따른 반도체소자 제조방법의 특징은,The present invention is to achieve the above object, the characteristics of the semiconductor device manufacturing method according to the present invention,

반도체기판상에 패드산화막과 패드질화막을 순차적으로 형성하는 공정과,Sequentially forming a pad oxide film and a pad nitride film on the semiconductor substrate;

상기 패드질화막과 패드산화막을 소자분리마스크를 이용한 패턴닝 공정으로 선택 식각하여 반도체기판의 소자분리영역으로 예정되어있는 부분을 노출시키는 패드질화막 패턴을 형성하는 공정과,Selectively etching the pad nitride film and the pad oxide film by a patterning process using a device isolation mask to form a pad nitride film pattern exposing a predetermined portion of the semiconductor substrate as a device isolation region;

상기 패드질화막에 의해 노출되어있는 반도체기판을 일정 두께 식각하여 트랜치를 형성하는 공정과,Etching the semiconductor substrate exposed by the pad nitride layer to form a trench by a predetermined thickness;

상기 구조의 전표면에 웰 산화막과 CVD 산화막 및 선형질화막을 순차적으로 형성하는 공정과,Sequentially forming a well oxide film, a CVD oxide film and a linear nitride film on the entire surface of the structure;

상기 구조의 전표면에 필드산화막을 형성하여 트랜치를 메우는 공정과.Forming a field oxide film on the entire surface of the structure to fill the trench;

상기 필드산화막을 평탄화시키는 공정과,Planarizing the field oxide film;

상기 패드질화막 패턴을 제거하는 공정을 구비함에 있다.And removing the pad nitride film pattern.

또한 본 발명의 다른 특징은, 상기 CVD 산화막을 저압CVD 또는 플라즈마 유도 CVD방법으로 형성하고, 상기 CVD 산화막의 반응가스로는 Si(OC2H5)4, Si2H6, SiH2Cl2, SiHCl3, SiCl4및 O2중 하나를 사용하며, 상기 저압 CVD 방법은 650∼900℃에서 CVD 산화막을 성장시키고, 상기 플라즈마 유도 CVD 방법은 PSG, BSG 또는 BPSG 산화막을 형성하며, 상기 CVD 산화막 형성공정후 900∼1100℃ 의 온도에서 1-30분의 열처리 공정을 실시하는 공정을 구비하는 것을 특징으로 한다.In addition, another feature of the present invention, the CVD oxide film is formed by a low pressure CVD or plasma induced CVD method, the reaction gas of the CVD oxide film Si (OC 2 H 5 ) 4 , Si 2 H 6 , SiH 2 Cl 2 , SiHCl 3 , SiCl 4 and O 2 , the low pressure CVD method grows a CVD oxide film at 650 to 900 ° C., the plasma induced CVD method forms a PSG, BSG or BPSG oxide film, and the CVD oxide film forming process It is characterized in that it comprises a step of performing a heat treatment step of 1-30 minutes at a temperature of 900 ~ 1100 ℃.

이하, 본 발명에 따른 반도체소자의 제조방법에 관하여 첨부도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2e는 본 발명에 따른 반도체소자의 제조공정도이다.2A to 2E are manufacturing process diagrams of a semiconductor device according to the present invention.

먼저, 도 1b의 공정과 마찬가지로 실리콘 웨이퍼등의 반도체기판(10)상에 소자분리 마스크(도시되지 않음)를 이용하여 패턴닝된 패드질화막(14) 패턴과 패드산화막(12) 패턴을 형성하고, 상기 패드질화막(14) 패턴에 의해 노출되어있는 반도체기판(10)을 일정 깊이 식각하여 트랜치(16)를 형성한 후, 상기 구조의 전표면에 웰 산화막(18)과 CVD 산화막(30) 및 선형 질화막(20)을 순차적으로 형성한다. 여기서 상기 CVD 산화막(30)은 단차피복성이 우수한 저압CVD나 플라즈마 유도 CVD방법으로 형성하고, 반응가스로는 Si(OC2H5)4, Si2H6, SiH2Cl2, SiHCl3, SiCl4및 O2등을 사용하고, 저압CVD 에서는 650∼900℃에서 성장시키며, 플라즈마 유도 CVD방법은 PSG, BSG 또는 BPSG 산화막을 성장시킨다.First, similarly to the process of FIG. 1B, a patterned pad nitride film 14 pattern and a pad oxide film 12 pattern are formed on a semiconductor substrate 10 such as a silicon wafer by using an isolation mask (not shown). After etching the semiconductor substrate 10 exposed by the pad nitride layer 14 pattern to a predetermined depth to form the trench 16, the well oxide 18, the CVD oxide 30, and the linear structure are formed on the entire surface of the structure. The nitride film 20 is formed sequentially. Here, the CVD oxide film 30 is formed by low pressure CVD or plasma induced CVD with excellent step coverage, and as reaction gas, Si (OC 2 H 5 ) 4 , Si 2 H 6 , SiH 2 Cl 2 , SiHCl 3 , SiCl 4 and O 2 , and the like, are grown at 650 to 900 ° C. in low pressure CVD, and the plasma induced CVD method grows PSG, BSG, or BPSG oxide films.

그다음 상기 트랜치(16)를 메우는 필드산화막(22)을 형성한다. (도 2a 참조).A field oxide film 22 is then formed to fill the trench 16. (See FIG. 2A).

그 후, 상기 필드산화막(22)의 상부 표면을 CMP 등의 방법으로 식각하여 평탄화시킨다. (도 2b 참조).Thereafter, the upper surface of the field oxide film 22 is etched and planarized by a method such as CMP. (See FIG. 2B).

그다음 상기 패드질화막(14)을 제거하게 되면, 패드질화막(14)이 모두 제거되어도 선형질화막(20)은 필드산화막(22)과 CVD 산화막(30)의 사이에 위치하게 되어 모세관 효과를 받게되므로, 패드질화막(14)을 인산으로 제거하는 공정에서 선형질화막(20)은 패드질화막(14)에 비해 1/4 정도의 식각비를 가진다. 따라서 선형질화막(20)의 에지가 트랜치(16) 보다 높게 남는다. (도 2c 참조).Then, if the pad nitride film 14 is removed, even if all of the pad nitride film 14 is removed, since the linear nitride film 20 is positioned between the field oxide film 22 and the CVD oxide film 30 to receive a capillary effect, In the process of removing the pad nitride layer 14 with phosphoric acid, the linear nitride layer 20 has an etch ratio of about 1/4 of the pad nitride layer 14. Therefore, the edge of the linear nitride film 20 remains higher than the trench 16. (See FIG. 2C).

그후, 상기 패드산화막(12)을 제거하고, 문턱전압 조절용 산화막(24)을 반도체기판(10)상에 형성한다. 이때 다시 선형질화막(20)의 에지 일부가 제거된다. (도 2d 참조).Thereafter, the pad oxide film 12 is removed, and the threshold voltage adjusting oxide film 24 is formed on the semiconductor substrate 10. At this time, a part of the edge of the linear nitride film 20 is removed again. (See FIG. 2D).

그후 상기 산화막(24)을 제거하고, 반도체기판(10) 상에 게이트산화막(26)을 형성한다. 이때 상기 필드산화막(22)의 에지 부분에 모트(28)가 거의 형성되지 않는다. (도 2e 참조).Thereafter, the oxide film 24 is removed, and a gate oxide film 26 is formed on the semiconductor substrate 10. At this time, the mort 28 is hardly formed at the edge portion of the field oxide film 22. (See FIG. 2E).

또한 상기 필드산화막 식각을 위한 CMP 공정시 저선택비 슬러리를 사용하면 평탄화 공정시 단차에 의한 평탄도 저하를 방지할 수 있으며, CVD 산화막 형성후에 900∼1100℃ 정도의 온도에서 30분 미만의 열처리 공정을 실시하면, 필드산화막과 CVD 산화막간의 산에 대한 식각비가 3 이하가 된다.In addition, the use of a low selectivity slurry in the CMP process for etching the field oxide film can prevent the flatness due to the step difference during the planarization process, and after the formation of the CVD oxide film, a heat treatment process of less than 30 minutes at a temperature of about 900 to 1100 ° C. The etching ratio of the acid to the acid between the field oxide film and the CVD oxide film is 3 or less.

이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자의 제조방법은, 선형 질화막의 하부에 CVD 산화막을 형성하여 패드질화막 제고 공정시 선형질화막의 식각 정도를 감소시켜 패드질화막이 모두 제거되어도 선형질화막의 에지가 트랜치의 상부에 위치하도록 형성하여 트랜치 에지 부분에서의 모트 발생을 방지하였으므로, 모트에 의해 후속 식각 공정에서의 잔류물 발생이 방지되고 라인의 단락이 방지되어 공정수율 및 소자의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, a CVD oxide film is formed below the linear nitride film to reduce the etching degree of the linear nitride film during the pad nitride film removing process, so that the edges of the linear nitride film are removed even if all of the pad nitride films are removed. Is formed so as to be located on the top of the trench to prevent the generation of motes in the trench edge portion, the mort prevents residues in the subsequent etching process and prevents short circuits, thereby improving process yield and device reliability. There is an advantage to that.

Claims (6)

반도체기판상에 패드산화막과 패드질화막을 순차적으로 형성하는 공정과,Sequentially forming a pad oxide film and a pad nitride film on the semiconductor substrate; 상기 패드질화막과 패드산화막을 소자분리마스크를 이용한 패턴닝 공정으로 선택 식각하여 반도체기판의 소자분리영역으로 예정되어있는 부분을 노출시키는 패드질화막 패턴을 형성하는 공정과,Selectively etching the pad nitride film and the pad oxide film by a patterning process using a device isolation mask to form a pad nitride film pattern exposing a predetermined portion of the semiconductor substrate as a device isolation region; 상기 패드질화막에 의해 노출되어있는 반도체기판을 일정 두께 식각하여 트랜치를 형성하는 공정과,Etching the semiconductor substrate exposed by the pad nitride layer to form a trench by a predetermined thickness; 상기 구조의 전표면에 웰 산화막과 CVD 산화막 및 선형질화막을 순차적으로 형성하는 공정과,Sequentially forming a well oxide film, a CVD oxide film and a linear nitride film on the entire surface of the structure; 상기 구조의 전표면에 필드산화막을 형성하여 트랜치를 메우는 공정과.Forming a field oxide film on the entire surface of the structure to fill the trench; 상기 필드산화막을 평탄화시키는 공정과,Planarizing the field oxide film; 상기 패드질화막 패턴을 제거하는 공정을 구비하는 반도체소자의 제조방법.A method of manufacturing a semiconductor device comprising the step of removing the pad nitride film pattern. 제 1 항에 있어서,The method of claim 1, 상기 CVD 산화막은 저압CVD 또는 플라즈마 유도 CVD방법으로 형성하는 것을 특징으로 하는 반도체소자의 제조방법.The CVD oxide film is a method of manufacturing a semiconductor device, characterized in that formed by low pressure CVD or plasma induced CVD method. 제 1 항에 있어서,The method of claim 1, 상기 CVD 산화막의 반응가스로는 Si(OC2H5)4, Si2H6, SiH2Cl2, SiHCl3, SiCl4및 O2로 이루어지는 군에서 임의로 선택되는 하나의 가스를 사용하는 것을 특징으로 하는 반도체소자의 제조방법.As the reaction gas of the CVD oxide film, one gas arbitrarily selected from the group consisting of Si (OC 2 H 5 ) 4 , Si 2 H 6 , SiH 2 Cl 2 , SiHCl 3 , SiCl 4, and O 2 is used. A method of manufacturing a semiconductor device. 제 2 항에 있어서,The method of claim 2, 상기 저압 CVD 방법은 650∼900℃에서 CVD 산화막을 성장시키는 것을 특징으로 하는 반도체소자의 제조방법.The low pressure CVD method is a method for manufacturing a semiconductor device, characterized in that to grow a CVD oxide film at 650 ~ 900 ℃. 제 2 항에 있어서,The method of claim 2, 상기 플라즈마 유도 CVD 방법은 PSG, BSG 및 BPSG 산화막으로 이루어지는 군에서 임의로 선택되는 하나의 산화막을 형성하는 것을 특징으로 하는 반도체소자의 제조방법.The plasma induced CVD method is a method for manufacturing a semiconductor device, characterized in that to form one oxide film arbitrarily selected from the group consisting of PSG, BSG and BPSG oxide film. 제 1 항에 있어서,The method of claim 1, 상기 CVD 산화막 형성공정후 900∼1100℃ 의 온도에서 1-30분의 열처리 공정을 실시하는 공정을 구비하는 것을 특징으로 하는 반도체소자의 제조방법.And a heat treatment step of 1-30 minutes at a temperature of 900 to 1100 ° C. after the CVD oxide film forming step.
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