KR20030008053A - Method for forming isolation layer in semiconductor device - Google Patents
Method for forming isolation layer in semiconductor device Download PDFInfo
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- KR20030008053A KR20030008053A KR1020010041858A KR20010041858A KR20030008053A KR 20030008053 A KR20030008053 A KR 20030008053A KR 1020010041858 A KR1020010041858 A KR 1020010041858A KR 20010041858 A KR20010041858 A KR 20010041858A KR 20030008053 A KR20030008053 A KR 20030008053A
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- 238000002955 isolation Methods 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title abstract description 24
- 150000004767 nitrides Chemical class 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 19
- 230000008569 process Effects 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 125000006850 spacer group Chemical group 0.000 claims abstract description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
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Abstract
Description
본 발명은 반도체 소자의 소자분리막 형성방법에 관한것으로, 소자분리막 모서리의 호(moat)에 의한 누설전류를 방지할 수 있는 반도체 소자의 소자분리막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a method of forming a device isolation film of a semiconductor device capable of preventing a leakage current caused by a moat at the edge of the device separation film.
일반적으로 실리콘 웨이퍼에 형성되는 반도체 장치는 개개의 회로 패턴들을 전기적으로 분리하기 위한 소자 분리 영역을 포함한다. 특히 반도체 장치가 고집적화 되고 미세화 되어감에 따라 각 개별 소자의 크기를 축소시키는 것뿐만 아니라 소자 분리 영역의 축소에 대한 연구가 활발히 진행되고 있다. 그 이유는 소자 분리 영역의 형성은 모든 제조 단계에 있어서 초기 단계의 공정으로서, 활성영역의 크기 및 후공정 단계의 공정마진을 좌우하게 되기 때문이다.In general, semiconductor devices formed on silicon wafers include device isolation regions for electrically separating individual circuit patterns. In particular, as semiconductor devices have been highly integrated and miniaturized, research into not only the size of each individual device but also the device isolation region has been actively conducted. The reason for this is that the formation of the device isolation region is an initial step in all the manufacturing steps, and depends on the size of the active area and the process margin of the post-process step.
일반적으로 반도체 장치의 제조에 널리 이용되는 로코스 소자분리 방법은 공정이 간단하다는 이점이 있지만 256M DRAM급 이상의 고집적화되는 반도체 소자에 있어서는 소자 분리 영역의 폭이 감소함에 따라 버즈비크(Bird' Beak)에 의한 펀 치쓰루(Punch-Through)와 소자 분리막의 두께 감소로 인하여 그 한계점에 이르고 있다.In general, the Locos device isolation method widely used in the manufacture of semiconductor devices has the advantage of simple process, but in the case of highly integrated semiconductor devices of 256M DRAM level or more, the width of the device isolation region decreases in the bird's beak. Due to the punch-through and thickness reduction of the device isolation layer, the limit point is reached.
이에따라, 고집적화된 반도체 장치의 소자 분리에 적합한 기술로 트랜치를 이용한 소자 분리 방법, 예컨대 샬로우 트랜치 분리방법(Shallow Trench Isolation: 이하, STI)이 제안되었다.Accordingly, a device isolation method using a trench, such as a shallow trench isolation method (STI), has been proposed as a technique suitable for device isolation of highly integrated semiconductor devices.
이하, 첨부된 도면을 참조하여 종래의 소자분리막 형성공정을 설명하도록 한다.Hereinafter, a conventional device isolation film forming process will be described with reference to the accompanying drawings.
도 1a 내지 도 1d는 종래의 반도체 소자의 소자분리막 형성방법을 설명하기 위한 제조공정도이다.1A to 1D are manufacturing process diagrams for explaining a method of forming a device isolation film of a conventional semiconductor device.
먼저, 도 1a에 도시된 바와같이, 실리콘 기판(1)상에 버퍼 역할을 하는 패드산화막(2)과 산화를 억제하는 실리콘 질화막(3)을 순차적으로 형성한다. 다음, 실리콘 질화막(3) 상부에 소자 분리 예정 영역을 형성시키기 위한 감광막 패턴(4)을 형성한다. 이때, 감광막 패턴(4)은 얇은 폭의 소자 분리막을 형성하기 위하여 해상도가 우수한 DUV(deep ultra violet)광원을 이용하여 형성한다.First, as shown in FIG. 1A, a pad oxide film 2 serving as a buffer and a silicon nitride film 3 that inhibits oxidation are sequentially formed on the silicon substrate 1. Next, a photosensitive film pattern 4 for forming a device isolation region is formed on the silicon nitride film 3. In this case, the photoresist pattern 4 is formed using a deep ultra violet (DUV) light source having excellent resolution in order to form a thin device isolation layer.
그 다음, 도 1b에 도시된 바와같이, 감광막 패턴(4)을 식각장벽으로 실리콘 질화막을 식각하여 질화막 패턴(3a)을 형성한다.1B, the silicon nitride film is etched using the photoresist pattern 4 as an etch barrier to form the nitride film pattern 3a.
그 다음, 도 1c에 도시된 바와같이, 상기 감광막 패턴을 제거한 후, 질화막 패턴(3a)을 식각 마스크로 패드 산화막(2) 및 실리콘 기판(1)을 소정 깊이만큼 건식각하여 샬로우 트랜치(ST)를 형성한다.Next, as illustrated in FIG. 1C, after the photoresist pattern is removed, the shallow trench ST may be dry-etched by using the nitride film pattern 3a as an etching mask by dry etching the pad oxide film 2 and the silicon substrate 1 to a predetermined depth. ).
이어서, 도 1d에 도시된 바와같이, 트랜치 식각시 유발되는 스트레스를 제거하기 위해 트랜치(ST)가 형성된 실리콘 기판(1)상에 희생산화막(도시되지않음) 형성 및 제거함으로써 식각 데미지를 완화하고, 계속해서 사이드 월 산화(side wall oxidation)공정을 수행하여 트랜치내에 열산화막(5)을 형성한다.Subsequently, as shown in FIG. 1D, etching damage is alleviated by forming and removing a sacrificial oxide film (not shown) on the silicon substrate 1 on which the trench ST is formed to remove stress caused during trench etching. Subsequently, a side wall oxidation process is performed to form a thermal oxide film 5 in the trench.
그런다음, 열산화막(5)이 형성된 트랜치(ST)내를 매립하는 갭필 산화막(6), 예컨대, CVD(Chemical Vapor Deposition) 산화막을 증착한다. 그리고나서, 갭필 산화막을 화학기계연마하여 질화막 패턴(3a)이 노출되도록 평탄화한 후, 상기 마스크 패턴(3a) 및 패드산화막(2)을 차례로 습식각하여 반도체 소자의 소자분리막(10)을 형성한다.Then, a gap fill oxide film 6, for example, a chemical vapor deposition (CVD) oxide film, which is embedded in the trench ST in which the thermal oxide film 5 is formed, is deposited. Thereafter, the gapfill oxide film is chemically polished and planarized to expose the nitride film pattern 3a, and then the mask pattern 3a and the pad oxide film 2 are sequentially wetted to form the device isolation film 10 of the semiconductor device. .
이후, 도면에는 도시하지 않았지만 게이트 절연막과 게이트 전극 및 소오스/드레인 전극을 형성하여 트랜지스터를 형성한다.Subsequently, although not shown in the drawing, a transistor is formed by forming a gate insulating film, a gate electrode, and a source / drain electrode.
그러나, 질화막 패턴(3a)의 습식각 이후 실시되는 습식각 공정의 등방성 식각 공정으로 인해, 도 2에 도시된 바와같이 소자분리막(10)의 양쪽 모서리에 호(moat)(15)가 생성된다. 이는 반도체 소자의 동작 시, 호(15)가 생성된 지역에 누설 전류가 많이 발생되어 반도체 소자의 전기적 특성을 저하시킨다.However, due to the isotropic etching process of the wet etching process performed after the wet etching of the nitride film pattern 3a, an arc 15 is generated at both edges of the device isolation layer 10 as shown in FIG. 2. This causes a large amount of leakage current in the region in which the arc 15 is generated during operation of the semiconductor device, thereby lowering the electrical characteristics of the semiconductor device.
또한, 트랜지스터의 동작시 이상전류 증가 현상인 험프(hump) 현상이 발생한다. 이는 트랜지스터의 문턱 전압을 낮추어 반도체 소자의 신뢰성을 손상시킨다.In addition, a hump phenomenon, which is an abnormal current increase phenomenon, occurs during operation of the transistor. This lowers the threshold voltage of the transistor and impairs the reliability of the semiconductor device.
따라서, 상기 문제점을 해결하기 위해 안출된 본 발명의 목적은, 소자분리막 형성에 있어서 호(moat) 발생을 방지할 수 있는 반도체 소자의 소자분리막 형성방법을 제공하는 것이다.Accordingly, an object of the present invention devised to solve the above problems is to provide a method for forming a device isolation film of a semiconductor device capable of preventing the generation of moats in the device isolation film formation.
도 1a 내지 도 1d는 종래의 반도체 소자의 소자분리막 형성방법을 설명하기 위한 제조공정도.1A to 1D are manufacturing process diagrams for explaining a device isolation film forming method of a conventional semiconductor device.
도 2는 종래의 소자분리막의 문제점을 설명하기 위한 단면도.2 is a cross-sectional view illustrating a problem of a conventional device isolation film.
도 3a 내지 도 3g는 본 발명의 반도체 소자의 소자분리막 형성방법을 설명하기 위한 제조공정도.3A to 3G are manufacturing process diagrams for explaining a device isolation film forming method of a semiconductor device of the present invention.
* 도면의 주요 부분에 대한 부호 설명 *Explanation of symbols on the main parts of the drawings
20 : 실리콘 기판 22 : 제1 산화막20 silicon substrate 22 first oxide film
23 : 질화막 23a : 질화막 패턴23 nitride film 23a nitride film pattern
28 : 열산화막 30 : 제2 산화막28: thermal oxide film 30: second oxide film
50 : 제3 산화막 100 : 스페이서50: third oxide film 100: spacer
상기 목적 달성을 위한 본 발명의 반도체 소자의 소자분리막 형성방법은, 기판상에 제1 산화막 및 질화막을 형성하는 단계; 소자분리 영역의 질화막을 식각하여 질화막 패턴을 형성하는 단계; 상기 질화막 패턴을 식각 마스크로 상기 산화막 및 기판을 식각하여 트랜치를 형성하는 단계; 상기 트랜치내에 제2 산화막을 매립하는 단계; 상기 질화막 패턴을 제거하는 단계; 상기 제1, 제2 산화막 상에 제3 산화막을 형성하는 단계; 및 상기 제3 산화막을 식각하여 제2 산화막 양측벽에 스페이서를 형성하면서 상기 제1 산화막을 제거하는 단계를 포함하는 것을 특징으로 한다.The device isolation film forming method of the semiconductor device of the present invention for achieving the above object comprises the steps of: forming a first oxide film and a nitride film on the substrate; Etching the nitride film of the device isolation region to form a nitride film pattern; Forming a trench by etching the oxide layer and the substrate using the nitride layer pattern as an etching mask; Embedding a second oxide film in the trench; Removing the nitride film pattern; Forming a third oxide film on the first and second oxide films; And removing the first oxide film by etching the third oxide film to form spacers on both side walls of the second oxide film.
이하, 본 발명의 바람직한 실시예를 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.
도 3a 내지 도 3g는 본 발명의 반도체 소자의 소자분리막 형성방법을 설명하기 위한 각 단계별 제조공정도이다.3A to 3G are manufacturing process diagrams for each step for explaining a method of forming an isolation layer of a semiconductor device of the present invention.
먼저, 도 3a에 도시된 바와같이, 실리콘 기판(20)상에 버퍼 역할을 하는 제1 산화막(22)과 산화를 억제용 질화막(23)을 순차적으로 형성한다. 그 다음, 질화막(23) 상부에 감광막(25)을 도포한다.First, as shown in FIG. 3A, a first oxide film 22 serving as a buffer and a nitride film 23 for inhibiting oxidation are sequentially formed on the silicon substrate 20. Next, the photosensitive film 25 is coated on the nitride film 23.
그 다음, 도 3b에 도시된 바와같이, 상기 감광막(25)에 소자 분리 예정 영역을 형성시키기 위해 노광 및 현상공정을 수행하여 감광막 패턴(25a)을 형성한다. 이어서, 감광막 패턴(26)을 식각 마스크로 질화막(23)을 식각하여 질화막 패턴(23a)을 형성한다.Next, as shown in FIG. 3B, an exposure and development process is performed to form a device isolation region on the photosensitive film 25 to form the photosensitive film pattern 25a. Next, the nitride film 23 is etched using the photoresist pattern 26 as an etching mask to form the nitride film pattern 23a.
그 다음, 도 3c에 도시된 바와같이, 상기 감광막 패턴을 제거한 후, 질화막 패턴(23a)을 식각장벽으로 제1 산화막(22) 및 실리콘 기판(20)을 소정 깊이만큼 건식각하여 샬로우 트랜치(ST)를 형성한다. 이어서, 트랜치 식각시 유발되는 스트레스를 제거하기 위해 트랜치(ST)가 형성된 실리콘 기판(20)상에 희생산화막(도시되지않음) 형성 및 제거함으로써 식각 데미지를 완화하고, 계속해서 사이드 월 산화(side wall oxidation)공정을 수행하여 후속 갭필 산화막과의 접착성을 향상시키기 위해 트랜치(ST)내에 열산화막(28)을 형성한다.Next, as shown in FIG. 3C, after the photoresist pattern is removed, the shallow trench is formed by dry etching the first oxide layer 22 and the silicon substrate 20 by a predetermined depth using the nitride layer pattern 23a as an etch barrier. To form ST). Subsequently, in order to remove the stress caused during the trench etching, a sacrificial oxide film (not shown) is formed and removed on the silicon substrate 20 on which the trench ST is formed to mitigate etching damage, and then side wall oxidation is continued. an oxidation process is performed to form a thermal oxide film 28 in the trench ST to improve adhesion to subsequent gapfill oxide films.
그 다음, 도 3d에 도시된 바와같이, 질화막 패턴(23a)과 트랜치(ST)상에 제2 산화막(30), 예컨대 CVD(Chemical Vapor Deposition) 산화막을 증착한다. 그리고나서, 제2 산화막(30)을 화학기계연마하여 질화막 패턴(23a)이 노출되도록 평탄화한다.Next, as shown in FIG. 3D, a second oxide film 30, for example, a chemical vapor deposition (CVD) oxide film, is deposited on the nitride film pattern 23a and the trench ST. Then, the second oxide film 30 is chemically polished to planarize so that the nitride film pattern 23a is exposed.
그 다음, 도 3e에 도시된 바와같이, 등방성 식각을 통하여 질화막 패턴(23a)을 제거하여 제2 산화막(30) 상부면을 노출시킨 다음, 도 3f에 도시된 바와같이, 제3 산화막(50)을 형성한다. 이때, 상기 제3 산화막(50)은 CVD(Chemical Vapor Deposition) 방식에 의해 형성됨이 바람직하다.Next, as illustrated in FIG. 3E, the nitride layer pattern 23a is removed by isotropic etching to expose the upper surface of the second oxide layer 30, and as shown in FIG. 3F, the third oxide layer 50 is formed. To form. In this case, the third oxide film 50 is preferably formed by a chemical vapor deposition (CVD) method.
이어서, 도 3g에 도시된 바와같이, 제3 산화막(50)을 이방성 식각하여 상기 노출된 제2 산화막(30) 양측벽에 스페이서(100)를 형성함과 동시에 제1 산화막(22)을 제거함으로써, 소자분리막을 형성한다. 이에따라, 이후 반도체 소자의 형성 공정에서 게이트가 형성시까지 진행되는 각 공정에서의 산화막이 식각되더라고 상기 스페이서(100)에 의해 소자분리막의 경계면에서의 호(moat) 발생을 방지할 수 있다. 따라서 호(moat)에 의해 발생되는 험프(hump) 현상이 개선된 소자의 특성을 얻을 수 있다.Subsequently, as shown in FIG. 3G, the third oxide film 50 is anisotropically etched to form spacers 100 on both exposed side walls of the second oxide film 30, and simultaneously remove the first oxide film 22. The device isolation film is formed. Accordingly, even when the oxide film is etched in each process of the semiconductor device forming process until the gate is formed, the moiety at the interface of the device isolation film can be prevented by the spacer 100. Therefore, it is possible to obtain the characteristics of the device in which the hump generated by the moat is improved.
여기서, 상기 스페이서(100)는 질화막 패턴(23a)의 두께에 의해 결정되며, 그 두께는 게이트 형성시 까지의 전세 공정에 의해 스페이서(100)가 제거될 수 있는 두께로 정의한다.Here, the spacer 100 is determined by the thickness of the nitride film pattern 23a, and the thickness is defined as a thickness at which the spacer 100 can be removed by a charter process until the gate is formed.
이후, 도면에는 도시하지 않았지만 게이트 절연막과 게이트 전극 및 소오스/드레인 전극을 형성하여 트랜지스터를 형성한다.Subsequently, although not shown in the drawing, a transistor is formed by forming a gate insulating film, a gate electrode, and a source / drain electrode.
한편, 이상에서 설명한 본 발명은 상술한 실시예 및 첨부된 도면에 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.
상술한 본 발명의 반도체 소자의 소자분리막 형성방법에 의하면, 제2 산화막(30) 상부면에 스페이서(100)를 형성함으로써, 이후 게이트 형성시까지의 세정공정 및 등방성 식각 공정이 실시되더라도 고집적 미세 회로에서 발생하는 트랜지스터의 단채널 효과 및 누설 전류의 발생원인인 호(moat)의 발생을 방지할 수 있다.According to the method of forming a device isolation film of the semiconductor device of the present invention described above, by forming the spacer 100 on the upper surface of the second oxide film 30, a highly integrated microcircuit even if a cleaning process and an isotropic etching process until the gate formation is performed It is possible to prevent the short channel effect of the transistor generated at and the generation of a moat which is a cause of leakage current.
따라서, 트랜치 분리 소자를 제조하는 경우 소자의 신뢰성을 향상시킬 수 있고, 보다 고집적도의 미세 소자를 형성하는 데 효과가 있다.Therefore, when the trench isolation device is manufactured, the reliability of the device may be improved, and it is effective to form a higher density micro device.
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| KR100512462B1 (en) * | 2003-01-30 | 2005-09-07 | 동부아남반도체 주식회사 | Method for manufacturing Semiconductor device using contact spiking prevention |
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|---|---|---|---|---|
| JPH09321131A (en) * | 1996-05-30 | 1997-12-12 | Nec Corp | Semiconductor device and manufacture thereof |
| JPH10199969A (en) * | 1996-12-26 | 1998-07-31 | Lg Semicon Co Ltd | Manufacture of semiconductor device having trench isolating structure |
| JPH1167893A (en) * | 1997-08-12 | 1999-03-09 | Nec Corp | Semiconductor device and its manufacture |
| US6197659B1 (en) * | 1999-03-09 | 2001-03-06 | Mosel Vitelic, Inc. | Divot free shallow trench isolation process |
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2001
- 2001-07-12 KR KR1020010041858A patent/KR20030008053A/en not_active Application Discontinuation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09321131A (en) * | 1996-05-30 | 1997-12-12 | Nec Corp | Semiconductor device and manufacture thereof |
| JPH10199969A (en) * | 1996-12-26 | 1998-07-31 | Lg Semicon Co Ltd | Manufacture of semiconductor device having trench isolating structure |
| JPH1167893A (en) * | 1997-08-12 | 1999-03-09 | Nec Corp | Semiconductor device and its manufacture |
| US6197659B1 (en) * | 1999-03-09 | 2001-03-06 | Mosel Vitelic, Inc. | Divot free shallow trench isolation process |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100512462B1 (en) * | 2003-01-30 | 2005-09-07 | 동부아남반도체 주식회사 | Method for manufacturing Semiconductor device using contact spiking prevention |
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