KR20040108575A - Magnetic memory device and method of manufacturing magnetic memory device - Google Patents

Abstract

PURPOSE: A magnetic memory device and a manufacturing method thereof are provided to reduce the power consumption and the heat by simplifying the process of a peripheral circuit region while using the clad structure through forming a magnetic material layer including a high magnetic permeability layer on both side surfaces of the first wiring only within the memory cell region and on a surface opposite to a surface facing the memory device. CONSTITUTION: A magnetic memory device having magnetic material layer including high magnetic permeability layer comprises a memory cell region(6) and a peripheral circuit region(8) mounted on a substrate(10), wherein: the memory cell region(6) comprises first wiring(11), second wiring(12) that three-dimensionally intersects with the first wiring, and a magnetoresistance effect type memory device(13) disposed in an intersection region of the first and the second wiring for storing and reproducing information of a magnetic spin; the peripheral circuit region(8) comprises first wiring(61) that is in the same wiring layer as that of the first wiring(11) in the memory cell region(6), second wiring(62) that is in the same wiring layer as the second wiring(12) in the memory cell region(6), and a magnetic material layer(51) including a high magnetic permeability layer is formed on both side surfaces of the first wiring only within the memory cell region and on a surface opposite to a surface facing the memory device(13).

Description

Magnetic memory device and method of manufacturing magnetic memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic memory device and a method of manufacturing the magnetic memory device, and in particular, a nonvolatile magnetic memory device for storing information by using a change in resistance value due to parallel or antiparallel spin directions of a ferromagnetic material; A method of manufacturing a magnetic memory device.

With the rapid spread of information communication devices, especially small personal devices such as portable terminals, devices such as memory elements and logic elements constituting this require higher performance, such as high integration, high speed, and low power consumption. In particular, nonvolatile memory is considered to be an indispensable element in the ubiquitous era.

For example, even in the case where power is consumed or troubles are caused, or when the server and the network are disconnected due to some kind of failure, the nonvolatile memory can protect important personal information. In addition, high density and large capacity of the nonvolatile memory are becoming more and more important as a technique for replacing a hard disk or an optical disk which cannot be miniaturized essentially due to the presence of a movable portion.

In addition, recent portable devices are designed to reduce power consumption as long as unnecessary circuit blocks can be placed in a standby state. However, power consumption and memory can be achieved if a nonvolatile memory capable of both high-speed network memory and mass storage memory can be realized. It is possible to get rid of uselessness. In addition, the so-called instant-on function, which can be started in a moment when the power supply is turned on, can be realized as long as the high speed nonvolatile memory can be realized.

Examples of the nonvolatile memory include flash memory using a semiconductor and Ferro electric random access memory (FRAM) using a ferroelectric. However, there is a drawback that the flash memory is slow because the writing speed is a sequence of μsec. In addition, since the structure is complicated, high integration is difficult, and furthermore, there is a drawback that the access time is as low as about 100 ns. On the other hand, there is a problem that the durability is low in completely replacing the rewritable number of times in the RAM with the number of rewrites from ¹² to ¹⁴ times to the static random access memory (DRAM) or the dynamic random access memory (SRAM). Moreover, the problem that the microfabrication of a ferroelectric capacitor is difficult is also pointed out.

Although it is attracting attention as a nonvolatile memory which does not have these drawbacks, it is a magnetic memory called MRAM (Magnetic Random Access Memory) or MRR (Magneto Resistance) memory, and a recent tunnel magnetoresistive element (hereinafter referred to as TMR), TMR is Tunnel Abbreviation of Magnetic Resistance) Attention has been drawn to improving the properties of the material (see, for example, Non-Patent Document 1).

MRMA is expected to have a large number of rewrites because of its simple structure and easy integration, and because of its storage by rotation of the magnetic moment. In addition, regarding the access time, it is expected to be considerably high speed, and it has been reported that it can already operate at 100 MHV (for example, see Non-Patent Document 2). Moreover, in the present time, when high output is obtained by the WMR effect, it has been greatly improved.

As described above, the MRAM has the advantage of high speed and high integration, but writing is performed in accordance with the generated magnetic field by passing a current through the bit line and the writing word line provided in proximity to the TRM element. The inversion magnetic field of the memory layer of the TMR element is also based on the material, but from 1.58 Pa / m to 8.5 Pa / m (200 O to 200 O e) is required, and the current at this time is several mA to several tens of MA. This is often associated with an increase in current consumption, which is a drawback in semiconductor devices such as device life, heat generation, and power consumption increase.

In order to solve this problem of increasing current consumption, a structure (hereinafter referred to as a clad structure) has been proposed that shields the periphery of the write word line and the bit line with a magnetic layer and concentrates the magnetic flux generated by the current (for example, For example, see patent document 1.).

Fig. 6 shows a schematic perspective view showing a simplified portion of an MRAM using a clad structure formed along a magnetic layer. As shown in FIG. 6, the magnetic material layer 16 covers the periphery of the word line 11 except for the surface of the magnetoresistive type memory element (for example, the TMR element) (13). The magnetic flux is concentrated on the memory element 13. Similarly, the second magnetic layer 17 is covered with the second magnetic layer 17 outside the surface on the side of the bit line 12 with the magnetic flux concentrated on the memory element 13.

[Patent Document 1]

Japanese Patent Laid-Open No. 022-246566 (Page 4, Fig. 6)

[Non-Patent Document 1]

Wang et al., "Feasibility of Ultra-Dense Spin-Tunneling Random Access Memory" IEEE Transaction on Magnetics 33 [6] (Nov. 1997) p4498-4512

[Non-Patent Document 2]

R. Schuerlein et al, "TA7.2 A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell" 2000 IEEE International Solid-State Circuits Conference Digest of Papers (Feb. 2000) p128- 129

However, the use of the clad structure makes it possible to reduce the write current value of the device having a higher magnetic field efficiency, while applying a process of covering the periphery of the wiring with the magnetic layer in the peripheral circuit region other than the memory cell. Since it becomes complicated, it becomes difficult to apply to fine wiring, and there exists a possibility of inhibiting high integration. In the peripheral circuit region, the magnetic layer reduces the wiring area, which may increase the wiring resistance.

1 is a schematic sectional view showing the first embodiment according to the magnetic memory device of the present invention.

2 is a schematic sectional view showing a second embodiment according to the magnetic memory device of the present invention.

3 is a cross sectional view of the production process showing the first embodiment according to the method of manufacturing the magnetic memory device of the present invention.

4 is a cross sectional view of the production process showing the second embodiment according to the method of manufacturing the magnetic memory device of the present invention.

Fig. 5 is a cross sectional view of the production process showing the third embodiment according to the method of manufacturing the magnetic memory device of the present invention.

6 is a schematic perspective view showing a simplified portion of an MRAM using a clad structure formed of a magnetic layer.

* Explanation of Codes *

1. Magnetic memory device 6. Memory cell area

8. Peripheral Circuit Area 11. Semiconductor Device Substrate

11. First wiring (write word line) 12. Second wiring (bit line)

13. Memory device 51. Magnetic layer

61. First Wiring M. Memory Cell Area

C. Peripheral Circuit Area

The present invention provides a magnetic memory device and a method of manufacturing the magnetic memory device, which are provided to solve the above problems.

The first magnetic memory device of the present invention is a magnetic memory device in which a memory cell region and a peripheral circuit region are mounted on the same substrate, wherein the memory cell region includes a first wiring and a second wiring that intersects the first wiring in three dimensions. And a magnetoresistive effect memory element for storing and reproducing magnetic spin information at an intersection area between the first wiring and the second wiring, wherein the peripheral circuit area is the same wiring layer as the first wiring of the memory cell area. A first wiring of the first wiring and a second wiring of the same wiring layer as the second wiring of the memory cell region, the both sides of the first wiring only in the memory cell region and a surface opposite to the surface facing the memory element The magnetic body layer which consists of a high permeability layer in this is formed.

In the first magnetic memory device, since a magnetic layer composed of a high permeability layer is formed on both sides of the first wiring only in the memory cell region and on a surface opposite to the surface facing the memory element, the magnetic layer is formed by the magnetic layer. Since the utilization efficiency of the magnetic field generated in the first wiring is increased, the write current value to the memory element is reduced. Further, the magnetic layer covering the wiring is formed only in the memory cell region, and not in the peripheral circuit region other than that. Therefore, in the first wiring of the peripheral circuit region, the wiring can be made highly integrated as long as the magnetic layer is not formed around the wiring. In other words, since it is possible to eliminate the reduction in the wiring area due to the formation of the magnetic layer, the wiring resistance is reduced by increasing the wiring area by that amount. In this way, the power consumption is reduced and the amount of heat generated is reduced. .

The second magnetic memory device of the present invention is a magnetic memory device in which a memory cell region and a peripheral circuit region are mounted on the same substrate, and the memory cell region includes a first wiring and a second wiring that intersects the first wiring in three dimensions. And a magnetoresistive effect memory element for storing and reproducing magnetic spin information at an intersection area between the first wiring and the second wiring, wherein the peripheral circuit area is the same wiring layer as the first wiring of the memory cell area. A first wiring of < RTI ID = 0.0 > and < / RTI > a second wiring of the same wiring layer as the second wiring of the memory cell region, the both sides of the second wiring only in the memory cell region and a surface opposite to the surface facing the memory element. The magnetic body layer which consists of a high permeability layer in this is formed.

In the second magnetic memory device, a magnetic layer composed of a high permeability layer is formed on both sides of the second wiring only in the memory cell region and on a surface opposite to the surface facing the memory element. Since the utilization efficiency of the magnetic field generated in the second wiring becomes high, the write current value to the memory element is reduced. Further, the magnetic layer covering the wiring is formed only in the memory cell region, and not in the peripheral circuit region other than that. Therefore, the high integration of the wiring can be achieved only as long as the magnetic layer is not formed around the wiring. In other words, since it is possible to eliminate the reduction in the wiring area due to the formation of the magnetic layer, the wiring resistance is reduced by increasing the wiring area by that amount. This reduces power consumption and heat generation.

A first manufacturing method of a magnetic memory device of the present invention is a method of manufacturing a magnetic memory device in which a memory cell region and a peripheral circuit region are mounted on the same substrate, and a process of forming a first wiring and sandwiching a tunnel insulating layer with a ferromagnetic material. Forming a tunnel magnetoresistive element that is electrically insulated from the first wiring; and electrically connecting the tunnel magnetoresistive element so that the tunnel magnetoresistive element intersects the first wiring in three dimensions. Forming a second wiring; forming a second wiring; forming a second wiring of the memory cell region; and forming a second wiring of the peripheral circuit region. The process of forming the second wiring of the memory cell region may include forming a wiring groove in the region forming the memory cell region of the substrate, and And a step of forming a magnetic layer made of a high permeability layer, and forming a first wiring on the side of the wiring groove through the magnetic layer.

In the first manufacturing method of the magnetic memory device, the process of forming the first wiring includes the process of forming the first wiring of the memory cell region and the process of forming the first wiring of the peripheral circuit region. In the step of forming the first wiring of the first wiring, the magnetic layer is formed by forming a first wiring having a high magnetic permeability layer formed on both sides of the first wiring and a surface opposite to the memory element. As a result, the utilization efficiency of the magnetic field generated in the first wiring becomes high, resulting in a structure in which the write current value to the storage element is reduced. Furthermore, since the process of forming the first wiring of the memory cell region and the process of forming the first wiring of the peripheral circuit region are performed in separate processes, the magnetic layer covering the wiring can be formed only in the memory cell region. It is not formed in other peripheral circuit areas. Therefore, in the first wiring of the peripheral circuit region, the wiring can be highly integrated as long as the magnetic layer is not formed around the wiring. In other words, since it is possible to eliminate the reduction in the wiring area due to the formation of the magnetic layer, the wiring resistance is reduced by increasing the wiring area by that amount. This forms a wiring structure in which power consumption is reduced and heat generation is reduced.

A second manufacturing method of the magnetic memory device of the present invention is a method of manufacturing a magnetic memory device for forming a memory cell region and a peripheral circuit region on the same substrate, the process of forming the first wiring and the tunnel insulating layer sandwiched by a ferromagnetic material Forming a tunnel magnetoresistive element that is electrically insulated from the first wiring; and electrically connecting the tunnel magnetoresistive element so that the tunnel magnetoresistive element intersects the first wiring in three dimensions. And forming a first wiring, forming a first wiring of the memory cell region, and forming a first wiring of the peripheral circuit region. The process of forming the first wiring of the memory cell region includes forming a wiring groove in an area forming the memory cell region of the substrate, and an inner surface of the wiring groove. And a step of forming a magnetic layer composed of a high permeability layer on the substrate, and a step of forming a first wiring in the wiring groove through the magnetic layer.

In the second manufacturing method of the magnetic memory device, the process of forming the second wiring includes the process of forming the second wiring of the memory cell region and the process of forming the second wiring of the peripheral circuit region. In the step of forming the second wiring, the magnetic layer is formed by forming a second wiring having a high magnetic permeability layer formed on both sides of the second wiring and a surface opposite to the memory element. As a result, the utilization efficiency of the magnetic field generated in the second wiring becomes high, resulting in a structure in which the write current value to the memory element is reduced. Furthermore, since the process of forming the second wiring of the memory cell region and the process of forming the second wiring of the peripheral circuit region are performed in separate processes, the magnetic layer covering the wiring can be formed only in the memory cell region. It is not formed in other peripheral circuit areas. Therefore, in the second wiring of the peripheral circuit region, the wiring can be highly integrated as long as the magnetic layer is not formed around the wiring. In other words, since it is possible to eliminate the reduction in the wiring area due to the formation of the magnetic layer, the wiring resistance is reduced by increasing the wiring area by that amount. This forms a wiring structure in which power consumption is reduced and heat generation is reduced.

A first embodiment according to the magnetic memory device of the present invention will be described with a schematic sectional view of FIG. In the first embodiment of the present invention, the magnetic layer is formed so that the current magnetic field emitted from the write word line in the memory cell region can be efficiently concentrated in the memory layer, and the wiring not forming the magnetic layer is disposed in the peripheral circuit region. will be.

As shown in Fig. 1, there is a semiconductor element substrate 10 on which elements, wirings, insulating films and the like are formed. In the semiconductor device substrate 10, for example, a trench well region is formed on the surface side of a semiconductor substrate (for example, a trench semiconductor substrate), and an element for separating the transistor formation region in the trench well region. The isolation region is formed of so-called shallow trench isolation (STI). On the X-well region, a gate electrode (word line) is formed with a gate insulating film interposed therebetween, and a diffusion layer region (for example, an N + diffusion layer region) is formed in the X-type well region on both sides of the gate electrode. A field effect transistor for selection is constructed. This field effect transistor functions as a switch element for reading. It is also possible to use various switch elements, such as a diode and a bipolar transistor, in addition to an n type or a V type field effect transistor.

A first insulating film is formed in a state covering the field effect transistor, and the first insulating film is formed.

A contact (for example, tungsten plug) for connecting to the diffusion layer region is formed in the insulating film 41. Furthermore, on the first insulating film, a sense line (not shown) to be connected to the contact, an electrode 31 for connection, and the like are formed.

A second insulating film 42 is formed on the first insulating film. The second insulating film 42 in the memory cell region 6 covers the sense line (not shown), the connection electrode 31, and the like. In the second insulating film 42, a contact (for example, a tungsten plug) 32 for connecting to the connection electrode 31 is formed. Further, on the second insulating film 42, a connecting electrode 33 to be connected to the contact 32, a first wiring (write word line) 11 and the like are formed. A description will be given as a write word line below. The write word line 11 is formed of a high permeability layer so as to surround both sides of the write word line 11 and a surface opposite to the surface facing the tunnel magnetoresistive element (hereinafter referred to as TMR) 13. The magnetic body layer 51 is provided. On the other hand, the first wiring 61 of the peripheral circuit region 8 is formed on the second insulating film 42 in the peripheral circuit region 8. Magnetic layers are not formed on the sidewalls and bottom surfaces of the first wirings 61.

As the high permeability material constituting the magnetic body layer 51, for example, a soft magnetic material having a maximum magnetic permeability μm of 100 or more can be used. Specifically, for example, an alloy containing nickel iron cobalt, iron aluminum It is possible to use a (FeAl) alloy or a ferite alloy. In the case where no electrical insulating layer is provided between the write word line 11 and the magnetic layer 51, it is preferable to use a soft magnetic film having a high resistivity in order to prevent current loss.

On the second insulating film 42 in the memory cell region 6, the write word line (first wiring) 11, the magnetic layer 51, the connecting electrode 33, and the peripheral circuit region 8 A third insulating film 43 covering the first wiring 61 and the like is formed. The third insulating film 43 has a structure in which, for example, an insulating film serving as an etching stopper, an interlayer insulating film, an insulating film serving as an etching stopper, and an interlayer insulating film are laminated in order from the lower layer. When the write word line (first wiring) 11 and the first wiring 61 are formed of, for example, a buried copper wiring, an insulating film serving as an upper etching stopper prevents diffusion of copper and simultaneously copper wiring. It is preferable to also function as a film for preventing the ingress of oxygen into the material, and is formed of, for example, a nitride film. The third insulating film 43 is provided with a plug 34 for connecting to the connecting electrode 33 and a plug 71 for connecting to the first wiring 61 of the peripheral circuit region 8.

Furthermore, on the third insulating film 43 in the memory cell region 6, an antiferromagnetic layer 305 is formed which is connected to the plug 34 above the write word line 11, thereby forming the antiferromagnetic layer. A memory element (hereinafter referred to as TMR element) 13 is formed above the write word line 11 above the line 305. The memory element 13 is, for example, a magnetization fixing layer made of a ferromagnetic layer, a tunnel insulation layer formed on the magnetization fixing layer, a memory layer on which the magnetization rotates relatively easily by being formed on the tunnel insulation layer, and on the memory layer. It consists of the formed cap layer. In addition, a bypass line (shown integrally with the antiferromagnetic layer 305 in the drawing) is formed on the antiferromagnetic layer 305 with the magnetization fixing layer extending.

A fourth insulating film 44 covering the memory element 13 and the like is formed on the third insulating film 43 in the memory cell region 6. The surface of the fourth insulating film 44 is flattened, and the top surface of the cap layer of the memory element 13 is exposed. The fourth insulating film 44 is connected to an upper surface of the memory element 13 and is formed to intersect (for example, orthogonally) three-dimensionally with the write word line 11 and the memory element 13 interposed therebetween. Two wirings (bit lines) 12 are formed.

On the other hand, on the fourth insulating film 44 in the peripheral circuit region 8, the second wiring 62 of the peripheral circuit region 8 is formed. In the fourth insulating film 44, a plug 71 connected to the first wiring 61 and a plug 72 connected to the second wiring 62 are formed. The plugs 71 and 72 may be formed integrally.

The memory element 13 should just have a tunnel magnetic resistance (TMR) effect, and is not limited to the said structure. As an example, the magnetization fixing layer formed on the antiferromagnetic layer 305 may be formed by laminating and forming a conductor layer and a second magnetization fixing layer in which the first magnetization fixing layer and the magnetic layer are antiferromagnetically coupled. The magnetization fixing layer may be a laminated structure, a single layer structure of a ferromagnetic layer, or may be a structure in which three or more ferromagnetic layers are laminated with a conductor layer interposed therebetween. It is also possible to form a ground conductive layer (not shown) used for connection with a switch element connected in series with the TMR element under the antiferromagnetic layer 305. It is also possible to serve as the base conductive layer by the antiferromagnetic layer 305.

The memory layer and the first magnetization fixing layer are made of, for example, ferromagnetic material such as nickel, iron or cobalt, or an alloy made of at least two kinds of nickel, iron, and cobalt. The conductor layer is formed of, for example, ruthenium, copper, chromium, gold, silver, or the like.

The first magnetized pinned layer is formed in contact with the antiferromagnetic layer, and the first magnetized pinned layer has strong one-way magnetic anisotropy due to the exchange interaction between the layers.

As the antiferromagnetic layer, for example, one kind of iron-manganese alloy, nickel-manganese alloy, platinum manganese alloy, iridium-manganese alloy, rhodium-manganese alloy, cobalt oxide and nickel oxide can be used.

The tunnel insulating layer is made of, for example, aluminum oxide, magnesium oxide, silicon oxide, aluminum nitride, magnesium nitride, silicon nitride, aluminum oxide nitride, magnesium oxide, or silicon oxynitride.

The tunnel insulating layer has a function of breaking a magnetic coupling between the storage layer and the magnetization fixing layer and flowing a tunnel current. These magnetic films and conductor films are mainly formed by the sputtering method. The tunnel insulating layer can be obtained by oxidizing, nitriding or oxynitriding a metal film formed by sputtering.

The cap layer has functions of preventing diffusion between the memory element 13 and the wiring connecting the other memory element 13, reducing contact resistance, and preventing oxidation of the memory layer. Usually, it forms with materials, such as copper, tantalum nitride, tantalum, and titanium nitride.

Next, the operation of the magnetic memory device 1 will be described. The memory element 13 detects the tunnel current change due to the magnetoresistive effect and reads out information, but the magnetoresistive effect depends on the relative magnetization direction between the memory layer and the magnetization pinned layer.

In the memory device 13, a current flows through the bit line 12 and the write word line 11, and the magnetization direction of the storage layer is changed in the synthesized magnetic field, and " 1 " or " 0 " The reading is performed by detecting the tunnel current change due to the magnetoresistive effect. The case where the magnetization directions of the memory layer and the magnetization pinned layer are the same is referred to as low resistance (this is referred to as "0", for example). For example, "1").

In the magnetic memory device 1, a high permeability layer is provided on both sides of the first wiring (write word line) 11 of the memory cell region 6 alone and on the surface opposite to the surface facing the memory element 13. Since the magnetic layer 51 is formed, the use efficiency of the magnetic field generated in the first wiring 11 is increased by the magnetic layer 51, so that the write current value to the memory element 13 is reduced. Further, the magnetic layer 51 covering the first wiring is formed only in the memory cell region 6, and not in the peripheral circuit region 8 other than that. Therefore, in the peripheral circuit region 8, the high integration of the first wiring 61 is possible only as long as the magnetic layer is not formed around the first wiring 61. In other words, since it is possible to eliminate the reduction in the wiring area due to the formation of the magnetic layer, the cross-sectional area of the wiring increases by increasing the wiring area of the first wiring 61 by that amount. Therefore, wiring resistance is reduced, so that power consumption is reduced and heat generation is reduced.

Next, the second embodiment according to the magnetic memory device of the present invention will be described with a schematic sectional view of FIG. 2. FIG. 2 (2) shows a cross section in the width direction of the bit lines formed in the memory cell region 6 in FIG.

In the second embodiment of the present invention, the magnetic layer is formed so that the current magnetic field emitted from the bit line of the memory cell region 6 can be efficiently concentrated in the memory layer, and the magnetic layer is not formed in the peripheral circuit region 8. The second wiring is arranged.

As shown in Fig. 2, there is a semiconductor element substrate 10 on which elements, wirings, insulating films and the like are formed. In the semiconductor device substrate 10, for example, a trench well region is formed on the surface side of a semiconductor substrate (for example, a trench semiconductor substrate), and an element for separating the transistor formation region in the trench well region. The isolation region is formed of so-called shallow trench isolation (STI). On the X type well region, a gate electrode (word line) is formed with a gate insulating film interposed therebetween, and a diffusion layer region (for example, N ⁺ diffusion layer region) is formed in the X type well region on both sides of the gate electrode, and is selected. A field effect transistor is constructed. This field effect transistor functions as a switch element for reading. It is also possible to use various switch elements, such as a diode and a bipolar transistor, in addition to an n type or a V type field effect transistor.

A first insulating film is formed while covering the field effect transistor, and a contact (for example, a tungsten plug) for connecting to the diffusion layer region is formed in the first insulating film 41. Furthermore, on the first insulating film, a sense line (not shown) connected to the contact, a connecting electrode 31, and the like are formed.

A second insulating film 42 is formed on the first insulating film. The second insulating film 42 in the memory cell region 6 covers the sense line, the connecting electrode 31 and the like. In the second insulating film 42, a contact (for example, a tungsten plug) 32 for connecting to the connection electrode 31 is formed. Further, on the second insulating film 42, a connecting electrode 33 connected to the contact 32, a write word line 11 of the first wiring, and the like are formed. As described in the first embodiment, the write word line 11 is opposite to both sides of the write word line 11 and to a surface opposing the tunnel magnetoresistive element (hereinafter referred to as TMR) 13. Although it is more preferable to provide a magnetic layer 51 made of a high permeability layer so as to surround the surface, the writing of information to the storage element 13 by the write word line 11 even if the magnetic layer 51 is not provided. Is possible. On the other hand, the first wiring 61 of the peripheral circuit region 8 is formed on the second insulating film 42 in the peripheral circuit region 8. Magnetic layers are not formed on the sidewalls and bottom surfaces of the first wirings 61.

On the second insulating film 42 in the memory cell region 6, the write word line (first wiring) 11, the magnetic layer 51, the connecting electrode 33, and the peripheral circuit region 8 A third insulating film 43 covering the first wiring 61 and the like is formed. The third insulating film 43 has a structure in which, for example, an insulating film serving as an etching stop layer, an interlayer insulating film, an insulating film serving as an etching stop layer, and an interlayer insulating film are laminated in order from the lower layer. In the case where the write word line (first wiring) 11 and the first wiring 61 are formed of, for example, a buried copper wiring, an insulating film serving as an upper etching stop layer prevents diffusion of copper and simultaneously copper wiring. It is preferable to also function as a film for preventing the ingress of oxygen into the material, and is formed of, for example, a nitride film. The third insulating film 43 is provided with a plug 34 for connecting to the connecting electrode 33 and a plug 71 for connecting to the first wiring 61 of the peripheral circuit region 8.

Furthermore, on the third insulating film 43 in the memory cell region 6, an antiferromagnetic layer 305 is formed which is connected to the plug 34 above the write word line 11, and the antiferromagnetic layer Above the write word line 11 and above the write word line 11, a memory element (hereinafter referred to as a TMR element) 13 is formed. The memory element 13 is, for example, a magnetization fixing layer made of a ferromagnetic layer, a tunnel insulation layer formed on the magnetization fixing layer, a memory layer on which the magnetization rotates relatively easily by being formed on the tunnel insulation layer, and on the memory layer. It consists of the formed cap layer. In addition, a bypass line (shown integrally with the antiferromagnetic layer 305 in the drawing) is formed on the antiferromagnetic layer 305 with the magnetization fixing layer extending.

A fourth insulating film 44 covering the memory element 13 and the like is formed on the third insulating film 43 in the memory cell region 6. The surface of the fourth insulating film 44 is flattened, and the top surface of the cap layer of the memory element 13 is exposed. The fourth insulating film 44 is connected to an upper surface of the memory element 13 and is formed to cross (for example orthogonally) three-dimensionally between the write word line 11 and the memory element 13. Two wirings (bit lines) 12 are formed. In the bit line 12, a magnetic layer made of a high permeability layer so as to surround the both sides of the bit line 12 and the surface opposite to the surface opposite to the tunnel magnetoresistive element (hereinafter referred to as TMR) 13 ( 52) is formed.

On the other hand, on the fourth insulating film 44 in the peripheral circuit region 8, the second wiring 62 of the peripheral circuit region 8 is formed. The magnetic layer is not formed on the side wall and the bottom surface side of the second wiring 62. In the fourth insulating film 44, a plug 71 connected to the first wiring 61 and a plug 72 connected to the second wiring 62 are formed. The plugs 71 and 72 may be formed integrally.

As the high permeability material constituting the magnetic layers 51 and 52, for example, a soft magnetic material having a maximum magnetic permeability μm of 100 or more can be used, and specifically, an alloy containing nickel, iron, and cobalt as an example. It is possible to use an iron, aluminum alloy or ferite alloy. In addition, when the electrical insulation layer is not provided between the write word line 11 and the magnetic layer 51, and when the electrical insulation layer is not provided between the bit line 12 and the magnetic layer 61, In the magnetic layer 51, a soft magnetic film having a high resistivity is preferably used to prevent current loss.

The storage element 13 may have a tunnel magnetic resistance (TMR) effect, and the same thing as described in the first embodiment can be used. It is also possible to form a ground conductive layer (not shown) for use in connection with a switch element connected in series with the TMR element in the base of the antiferromagnetic layer 305. It is also possible to serve as the base conductive layer by the antiferromagnetic layer 305.

As the antiferromagnetic material layer, the first magnetization fixing layer, the conductor layer, the second magnetization fixing layer, the tunnel insulation layer, the memory layer, the cap layer, and the like, the same ones as described in the first embodiment can be used.

The operation of the magnetic memory device 2 is basically the same as that of the magnetic memory device 1 of the first embodiment.

In the magnetic memory device 2, although the magnetic word layers 51 and 52 are provided in the write word line 11 and the bit line 12 in the memory cell region 6, the write word is the same as in the first embodiment. Even if the magnetic layer 51 is provided only on the line 11 or the magnetic layer 52 is provided only on the bit line 12, the writing efficiency to the memory element 13 is compared with the configuration in which the magnetic layer is not provided. It is possible to increase.

In the magnetic memory device 2, a high permeability layer is formed on both sides of the second wiring (write word line) 12 only in the memory cell region 6 and on the surface opposite to the surface facing the memory element 13. Since the magnetic layer 52 is formed, the utilization efficiency of the magnetic field generated in the second wiring 12 is increased by the magnetic layer 52, so that the write current value to the memory element 13 is reduced. Further, the magnetic layer 52 covering the second wiring 12 is formed only in the memory cell region 6, and is not formed in the peripheral circuit region 8 other than that. Therefore, in the peripheral circuit region 8, the high integration of the second wiring 62 is possible only as long as the magnetic layer is not formed around the second wiring 62. In other words, since it is possible to eliminate the reduction in the wiring area due to the formation of the magnetic layer, the cross-sectional area of the wiring increases by increasing the wiring area of the second wiring 62 by that amount, so that the wiring resistance is reduced. This reduces power consumption and heat generation.

Further, in the magnetic memory device 2, even if the magnetic layer 52 is formed in the side wall portion of the second wiring 62 of the peripheral circuit region 8 for the reason of simplifying the manufacturing process, the second wiring The wiring resistance is reduced as compared with the case where the second wiring 62 is formed in the same process as the bit line 12 of the memory cell region 6.

In the magnetic memory devices 1 and 2, in the first and second wirings 11 and 12, a barrier metal layer (not shown) is preferably formed so as to surround the wiring circumference. That is, the magnetic layer 51 formed on the first wiring 11 and the magnetic layer 52 formed on the second wiring 12 are formed around the wiring with a barrier metal layer (not shown) interposed therebetween. desirable. In addition, it is preferable to form a barrier metal layer that isolates the insulating film around the magnetic layers 51 and 52 outside the magnetic layers 51 and 52. In addition, the film structure of a 1st-5th insulating film is an example, and another structure may be sufficient. For example, the stopper insulating film can be omitted as long as the etching selectivity of the insulating film under the stopper insulating film is sufficiently obtained when the insulating film over the stopper insulating film is etched. The wiring structure may be an insulating film covering the wiring after the wiring is formed by a normal wiring forming process, and the surface of the insulating film may be flattened, or a wiring groove may be formed in the insulating film after the insulating film is formed. The groove wiring structure may be a buried wiring material.

Next, the first embodiment according to the manufacturing method of the magnetic memory device of the present invention will be described with reference to FIG. 3 manufacturing process cross section. In this first embodiment, a method of manufacturing the first wiring (write word line), which is a feature of the present invention, will be described in detail. In addition, in Fig. 3, the memory cell region 6 is shown on the left side, and the peripheral circuit region 8 is shown on the right side.

By a known technique, for example, an element isolation region for separating the element formation regions of the memory cell region 6 and the element formation regions of the peripheral circuit region 8 is formed in a semiconductor substrate, and thus the memory cell region. A switch element for reading is formed in the element formation region of (6). This switch element can be formed with various switch elements, such as an n type or a V type field effect transistor, a diode, and a bipolar transistor. In the peripheral circuit region 8, desired elements, wirings and the like are formed.

A contact formed by forming a first insulating film in a state covering the field effect transistor, the peripheral circuit region 8, and the like, and connecting the first insulating film 41 to a lower layer element such as the switch element, wiring, or the like ( Tungsten plugs, for example). Furthermore, a sense line for connecting to a contact, an electrode for connection, and the like are formed on the first insulating film.

A second insulating layer 42 is formed on the first insulating layer. The second insulating film 42 in the memory cell region 6 covers the sense line, the connecting electrode and the like. In the second insulating film 42, a contact (for example, a tungsten plug) for connecting to the connecting electrode is formed.

Next, as shown in FIG. 3 (1), a third insulating film 43 is formed on the second insulating film 42. As shown in FIG. First, a stopper insulating film 431 serving as an etch stop layer is formed on the second insulating film 42, and then an interlayer insulating film 432 in which the first wiring is formed is formed. The stopper insulating film 431 can be formed of, for example, silicon nitride or silicon carbide. The interlayer insulating film 432 may be formed of, for example, an insulating material film such as a silicon oxide (SiO 2) film, a silicon oxyfluoride (SiOF) film, a silicon oxide carbide (SiOOC) film, an organic compound film, or a plurality thereof. It is possible to form the laminated film which consists of. Thereafter, a first wiring groove 436 for forming a first wiring (write word line) is formed in the memory cell region 6. The first wiring groove 436 is formed by a lithography technique using a resist and an etching technique using a resist mask formed thereby. At this time, in order to prevent the etching of the insulating film 432 on which the first wiring is formed, the second insulating film 42 of the lower layer is prevented from being etched, the insulating film 432 on which the first wiring is formed on the stopper insulating film 431 once. ), The stopper insulating film 431 is selectively etched with respect to the second insulating film 42, and the first wiring groove 436 is completed.

Next, as shown in Fig. 3 (2), the barrier metal layer 53 and the magnetic layer 51 (the magnetic layer (the magnetic layer) are formed on the inner surface of the first wiring groove 436 using, for example, a sputtering method. 51) may be formed by stacking a plurality of kinds of magnetic layers), and then the barrier metal layer 54 is formed. The barrier metal layers 53 and 54 may be materials which suppress the reaction and diffusion of the wiring layer and the magnetic layer, and are, for example, tantalum (Ta), tantalum nitride (TaN), tungsten (tungsten) and tungsten nitride (TN). , Titanium (Ti), titanium nitride (Ti), or the like can be used. The magnetic layer 51 may, for example, use a soft magnetic material having a maximum magnetic permeability μm of 100 or more, and specifically, an example. It is possible to use nickel, iron, cobalt, or an alloy containing one or more of them, an iron or aluminum alloy, or a ferite alloy. In the case where no electrical insulating layer is provided between the write word line 11 and the magnetic layer 51, it is preferable to use a soft magnetic film having a high resistivity in order to prevent current loss. Moreover, when forming the 1st wiring 11 from copper, a copper seed layer (not shown) is formed by sputtering. Thereafter, the first wiring groove 436 is buried in the copper film by, for example, electrolytic plating. Thereafter, the excess copper film, the barrier metal layers 53 and 54, the magnetic layer 51, and the like on the interlayer insulating film 432 are removed by a chemical mechanical polishing method, and the barrier metal layer is formed in the first wiring groove 436. 53, a first wiring (write word line) 11 made of copper film is formed with the magnetic body layer 51 and the barrier metal layer 54 interposed therebetween. For example, it is also possible to form with copper alloy, aluminum, an aluminum alloy, etc.

Next, as shown in FIG. 3 (3), an etch stop layer covering the first wiring 11 and a stopper insulating film 433 serving as a protective layer of the same wiring are formed on the interlayer insulating film 432. . The stopper insulating film 433 can be formed of, for example, silicon nitride or silicon carbide. Thereafter, a first wiring groove 437 is formed in the peripheral circuit region 8 for forming the first wiring. The first wiring groove 437 is formed by a lithography technique using a resist and an etching technique using a resist mask formed thereby. At that time, in order to suppress the etching beyond the second insulating film 42 in the lower layer when etching the interlayer insulating film 432 on which the first wiring is formed, the first one is placed on the stopper insulating film 431 serving as the etching stop layer. The etching of the interlayer insulating film 432 in which the wiring is formed is stopped, and then, the stopper insulating film 431 is selectively etched with respect to the second insulating film 42, and the first wiring grooves of the peripheral circuit region 8 ( 43) to complete.

Next, as shown in Fig. 3 (4), the barrier metal layer 56 is formed on the inner surface of the first wiring groove 437 by, for example, sputtering. The barrier metal layer 56 may be a material that suppresses the reaction and diffusion of the wiring layer. For example, tantalum (Ta), tantalum nitride (TaN), tungsten (tungsten), tungsten nitride (TN), and titanium (Ti) Titanium nitride (TiN) etc. can be used. Further, in the case where the first wiring 11 is formed of copper, a copper seed layer (not shown) is formed by sputtering. Thereafter, the inside of the first wiring groove 437 is buried in the copper film by, for example, electrolytic plating. Thereafter, the excess copper film, barrier metal layer 56, and the like on the interlayer insulating film 432 are removed by a chemical mechanical polishing method, and the copper film is interposed between the barrier metal layer 56 in the first wiring groove 437. A first wiring 61 is formed. The first wiring 61 may be formed of, for example, copper alloy, aluminum, aluminum alloy, or the like in addition to copper. It is also preferable to form a cap barrier metal layer (not shown) on the first wiring 11 of the peripheral circuit region 8 that prevents the diffusion of copper and prevents the oxidation of copper. As the cap barrier metal layer, for example, a silicon nitride film, a cobalt-tungsten-phosphorus (CO-P-P) film, or the like can be used.

Next, after forming the first wirings 11 and 61 in the memory cell region 6 and the peripheral circuit region 8, the interlayer covering the first wirings 11 and 61 on the stopper insulating film 433. An insulating film (not shown) is formed.

It is also possible to form a plug, a connection electrode, or the like in the memory cell region 6 by a process concurrent with the formation of the first wiring 11 in the peripheral circuit region 8.

Next, although not shown, a memory device having a TMR effect is formed on the write word line 11 with an insulating film interposed therebetween by a known manufacturing process of a magnetic memory device. A bit line or the like intersecting three-dimensionally (orthogonally) is formed by sandwiching the write word line 11 and the memory element.

In the first manufacturing method of the magnetic memory device, the step of forming the first wiring includes the steps of forming the first wiring (write word line) 11 of the memory cell region 6 and the peripheral circuit region 8. Forming the first wiring 61 of the first wiring line 61 and forming the first wiring 11 of the memory cell region 6 on both sides of the first wiring (write word line) and the memory element 13. Since the first wiring (write word line) 11 having the magnetic layer 51 made of a high permeability layer is formed on the surface opposite to the surface opposite to the surface, the first wiring (write word line) is formed by the magnetic layer. Since the utilization efficiency of the magnetic field generated at (11) becomes high, the structure in which the write current value to the storage element 13 is reduced. Furthermore, the process of forming the first wiring (write word line) 11 of the memory cell region 6 and the process of forming the first wiring 61 of the peripheral circuit region 8 are performed in different processes. The magnetic layer 51 covering the first wiring 11 can be formed only in the memory cell region 6 and is not formed in the peripheral circuit region 8 other than that. Therefore, in the first wiring 61 of the peripheral circuit region 8, the integration of the wiring can be made high only as long as the magnetic layer is not formed around the wiring. In other words, since it is possible to eliminate the reduction in the wiring area due to the formation of the magnetic layer, the wiring resistance is reduced by increasing the wiring area by that amount. This forms a wiring structure in which power consumption is reduced and heat generation is reduced.

The manufacturing method is an example of manufacturing the magnetic memory device 1 described with reference to FIG. 1. When the magnetic memory device 1 is formed, a process in which a magnetic layer is left on the side or bottom of the first wiring 11 of the peripheral circuit region 8 may be used.

Next, a second embodiment according to the manufacturing method of the magnetic memory device of the present invention will be described with reference to the manufacturing process cross section of FIG. In this second embodiment, the manufacturing method of the second wiring (bit line), which is a feature of the present invention, will be described in detail. In addition, in Fig. 4, the memory cell region 6 is shown in the figure on the left and the peripheral circuit region 8 is shown in the figure on the right.

By the known technique, for example, an element isolation region for separating the element formation regions of the memory cell region 6 and the element formation regions of the peripheral circuit region 8 is formed in a semiconductor substrate, and the memory cell region ( A switch element for reading is formed in the element formation region of 6). This switch element can be formed with various switch elements, such as an n type or a V type field effect transistor, a diode, and a bipolar transistor. In the peripheral circuit region 8, desired elements, wirings and the like are formed.

A contact is formed to form a first insulating film in a state covering the field effect transistor, the peripheral circuit region 8, and the like, and to be connected to the first insulating film, for example, a lower layer element such as the switch element, wiring, or the like (for example, Tungsten plugs). Furthermore, a sense line for connecting to a contact, an electrode for connection, and the like are formed on the first insulating film.

A second insulating film is formed on the first insulating film. The second insulating film in the memory cell region 6 covers the sense line, the connecting electrode and the like. In the second insulating film, a contact (for example, a tungsten plug) to be connected to the connecting electrode is formed.

Next, a third insulating film is formed on the second insulating film. Next, the first wiring (write word line) is formed on the third insulating film by the method described with reference to Fig. 3 or the conventional writing word line forming method. In the method described with reference to Fig. 3, the first wiring (write word line) is formed in the memory cell region 6, and then the first wiring is formed in the peripheral circuit region 8. On the other hand, in the conventional writing word line forming method, the first wiring (write word line) is formed simultaneously in both the memory cell region 6 and the peripheral circuit region 8. Preferably, the former method is used. Thereafter, a third insulating film is further formed to cover the first wiring. It is also possible to form a plug, a connection electrode, and the like in the memory cell region 6 by a process concurrent with the formation of the first wiring in the peripheral circuit region 8.

As shown in FIG. 4 (1), a conductive layer 131, a magnetoresistive type memory element (for example, a TMR element) 13, and a conductive layer are formed on the third insulating film (not shown). A cap layer (protective metal layer) 133 is formed. Furthermore, the fourth insulating film 44 is formed so as to bury the memory element 13, the cap layer 133, and the like. Thereafter, the upper surface of the cap layer 133 is exposed by chemical mechanical polishing, and the surface of the fourth insulating film 44 is planarized. The processes so far can be performed by existing methods, and the process is not limited thereto. It is also possible to form a plug for connecting the lower wiring or the electrode to the fourth insulating film 44 by using a plug forming technique for connecting the existing upper wiring and the lower wiring. As shown here, as an example, the plug 72 is formed in the peripheral circuit region 8. The formation of this plug 72 can use a conventional plug formation technique.

Further, a stopper insulating film 451 serving as an etch stop layer and an interlayer insulating film 452 serving as a fifth insulating film 45 are formed on the fourth insulating film 44 in this order. The fifth insulating film 45 is formed of the stopper insulating film 451 and the interlayer insulating film 453. The stopper insulating film 451 is formed of an insulating film which stops etching when the interlayer insulating film 452 is etched, and is formed of, for example, a silicon nitride (SiN) film, a silicon carbide (SiC) film, or the like. The interlayer insulating film 452 is, for example, an insulating material film such as a silicon oxide (SiO 2) film, a silicon oxide (SiOF) film containing fluorine, a silicon oxide carbide (SiOOC) film, an organic compound film, or two of them. It forms as a laminated structure using the above.

Next, wiring grooves 453 are formed in the fifth insulating film 45 in the region where the bit lines are formed in the memory cell region 6 using ordinary resist coating techniques, lithography techniques, and etching techniques. . At this point, no wiring groove is formed in the peripheral circuit region 8. Thereafter, the unnecessary resist mask is removed.

Subsequently, a first barrier metal layer 55 and a magnetic layer 521 are formed on the inner surface of the wiring groove 453 and the surface of the fifth insulating film 45 by using a known film forming technique, for example, by sputtering. ) In order. The first barrier metal layer 55 may be a material that suppresses the reaction with copper and the magnetic body and at the same time suppresses the diffusion of the copper and the magnetic body. For example, tantalum (Ta), tantalum nitride (TaN), tungsten (tungsten), tungsten nitride (TN), etc. are mentioned. As the magnetic layer 521, for example, a soft magnetic material having a maximum magnetic permeability μm of 100 or more can be used. Specifically, for example, an alloy containing at least one of iron, cobalt, and nickel, iron and aluminum ( Fe alloys or ferite alloys are used.

Next, the magnetic layer 521 and the first barrier metal layer 55 are anisotropically etched by a known etch back technique. As the etching gas, for example, a halogen gas containing chlorine or an etching gas to which carbon monoxide (CO) or ammonia (NH3) is added thereto is used. Furthermore, oxygen may be added. For example, a mixed gas of chlorine (flow rate: 50 cm 3 / m) and argon (flow rate: 50 cm 3 / m) is used as the etching gas, and the source power is 600 kPa to 2 kPa, the bias power is 50 kPa to 500 kPa, and the pressure of the etching atmosphere is used. Was set to 0.67 Pa to 1.3 pa and the substrate temperature was set at 20 ° C to 600 ° C, and etching was performed. As a result, sidewalls of the magnetic layer 521 are formed on the sidewalls of the wiring grooves 453 with the first barrier metal layer 55 interposed therebetween.

Next, the stopper insulating film 451 exposed to the bottom of the wiring groove 453 is removed by etching to expose the surface of the cap layer 133 of the memory cell region 6, for example. For example, a fluorine-based gas is used as the gas for etching the stopper insulating film 451. For example, using a mixed gas of chlorine (flow rate: 600 cm 3 / mni), boron trichloride (flow rate: 90 cm 3 / m) and trifluoride methane (CHF 3) (flow rate: 5 cm 3 / m), source power Was set at 600 Pa to 2 Pa, the bias power was 50 Pa to 200 Pa, the pressure in the etching atmosphere was set to 3.3 Pa to 4.0 Pa, and the substrate temperature was set at 200 to 600 ° C, and etching was performed. Alternatively, a mixed gas of trifluorinated methane (CHF3) and carbon monoxide (CO) in an etching gas, a mixed gas of trifluorinated methane (CHF3), tetrafluorinated methane (CF4) and argon (Ar), trifluorinated methane A mixed gas of (CHF 3), oxygen (O 2), and argon (Ar) is used.

Next, the second barrier metal layer 56 is formed by sputtering, including the inner surface of the wiring groove 453 so as to cover the magnetic layer 521. The second barrier metal layer 56 is required to be a material that suppresses the reaction with copper and the diffusion of copper. For example, tantalum (Ta), tantalum nitride (TaN), tungsten, and tungsten nitride The same material as the said 1st barrier metal layer 55, or a different material may be sufficient.

Subsequently, after forming a copper seed layer (not shown) on the surface of the second barrier metal layer 56, a conductor (hereinafter, referred to as a copper film) is formed so as to bury the wiring groove 453 by, for example, electrolytic plating. Film). This copper film consists of copper or a copper alloy, for example. As a result, the inside of the wiring groove 453 is filled with the copper film, and the copper film is formed on the fifth insulating film 45 with the second barrier metal layer 56 interposed therebetween. Subsequently, the copper film on the second insulating film 42, the second barrier metal layer 56, the magnetic layer 521, and the first barrier metal layer 55 are subjected to, for example, a chemical mechanical polishing (CPM) method or the like. The second wiring 12 is formed using the copper film of the groove wiring structure as a main material. Therefore, in the memory cell region 6 only, the second wiring (hereinafter referred to as a bit line) orthogonal to the write word line with the memory element 13 interposed between the write word line (not shown) (12). ) Is formed.

Furthermore, as shown in FIG. 4 (2), the third barrier metal layer 58 is formed in order to suppress the reaction with copper from the upper surface of the second wiring (including the bit line) 12 and the diffusion of copper. Next, the magnetic layer 522 is formed. Further, an antireflection film (not shown) may be formed. The third barrier metal layer 58 is formed of, for example, insulating films such as silicon nitride (SiN) and silicon carbide (SiC), or tantalum (Ta), like the first and second barrier metal layers 55 and 56. Tantalum nitride, tungsten, tungsten nitride, and the like can be used. The magnetic layer 522 can be formed of the same material as the electromagnetic layer 521. In addition, an antireflection film is not essential when the influence of the reflection from the base | substrate does not become a problem at the time of exposure of the subsequent lithography process. Here, the case where an antireflection film is not formed is demonstrated.

Next, using a conventional resist coating technique, a resist film (not shown) is formed on the magnetic layer 522. Next, by the lithography technique, the resist film is left only in the portion where the clad structure is to be left, that is, the upper portion of the portion where the TMR element is to be formed, and the resist film in other portions is removed.

Thereafter, the resist film is used as an etching mask, and the magnetic layer 522 and the third barrier metal layer 58 are etched away by a known etching technique. This etching is etched using the fifth insulating film 45 as an etching stop layer. In this way, a magnetic layer 52 formed of the magnetic layer 521 formed on the side wall and the magnetic layer 522 is formed on the upper and side surfaces of the bit line 12.

Next, as shown in Fig. 4 (3), a protective film 81 covering the magnetic layer 522 is formed on the fifth insulating film 45. Next, as shown in FIG. As the protective film 81, an insulating film such as silicon nitride (SiN), silicon carbide (SiC) or the like can be used. Next, a wiring groove is formed in the protective film 81 and the fifth insulating film 45 in the region where the second wiring is formed in the peripheral circuit region 8, using a conventional resist coating technique, lithography technique, and etching technique. (45) is formed. For etching the protective film 81, an etching gas containing, for example, a halogen gas containing chlorine or carbon monoxide (CO) or ammonia (NH3) added thereto is used. Furthermore, oxygen may be added. In the etching of the fifth insulating film 45, for example, when the fifth insulating film 45 is made of a silicon oxide-based material, a fluorine-based gas, for example, etching a normal silicon oxide-based material is used.

Subsequently, the stopper insulating film 451 exposed to the bottom of the wiring groove 444 is removed by etching to expose the surface of the plug 72 of the peripheral circuit region 8, for example. For example, a fluorine-based gas is used as the gas for etching the stopper insulating film 451.

At this time, the wiring groove is not formed in the memory cell region 6 basically, but in the case where a wiring, a plug, or the like is formed in the memory cell region 6 in which the magnetic layer is not required to be formed on the wiring sidewall, the wiring is formed. It is also possible to form a groove, a connection hole and the like. Thereafter, the unnecessary resist mask is removed.

Next, as shown in Fig. 4 (4), a barrier metal layer is formed on the inner surface of the wiring groove 444 and the surface of the protective film 81 by using a known film forming technique, for example, using a sputtering method. (82) is formed. The barrier metal layer 82 may be a material that suppresses the reaction with copper and the magnetic body and at the same time suppresses the diffusion of the copper and the magnetic body. For example, tantalum (Ta), tantalum nitride (TaN), tungsten, tungsten nitride, etc. are mentioned.

Subsequently, after forming a copper seed layer (not shown) on the surface of the barrier metal layer 82, a conductor (hereinafter referred to as copper film) to fill the wiring groove 444 by, for example, electrolytic plating. Tabernacle This copper film consists of copper or a copper alloy, for example. As a result, the inside of the wiring groove 444 is filled with the copper film, and the copper film is deposited on the protective film 81 with the barrier metal layer 82 interposed therebetween. Subsequently, the copper film on the protective film 81 and the barrier metal layer 82 are removed by, for example, chemical mechanical polishing (CMP) method, and the peripheral circuit region 8 containing the copper film of the grooved wiring structure as the main material. The second wiring 62 is formed. Therefore, in this process, the second wiring 62 is formed only in the peripheral circuit region 8.

In the second embodiment of the manufacturing method of the magnetic memory device, the step of forming the second wirings 12 and 62 is a step of forming the second wiring (bit line) 12 of the memory cell region 6. And forming the second wiring 62 of the peripheral circuit region 8, and forming the bit lines 12 of the memory cell region 6, in which both sides and the memories of the bit lines 12 are formed. Since the bit line 12 having the magnetic layer 52 made of a high permeability layer is formed on the surface opposite to the surface opposite to the element 13, the magnetic layer 52 generates the bit line 12. Since the utilization efficiency of the magnetic field becomes higher, the structure in which the write current value to the storage element 13 is reduced becomes. Furthermore, since the process of forming the bit line 12 of the memory cell region 6 and the process of forming the second wiring 62 of the peripheral circuit region 8 are performed in different processes, the bit line 12 is covered. The magnetic layer 52 can be formed only in the memory cell region 6 and is not formed in the peripheral circuit region 8 other than that. Therefore, in the second wiring 62 of the peripheral circuit region 8, the integration of the wiring can be made high only as long as the magnetic layer is not formed around the wiring. That is, since the magnetic layer 522 is not formed directly on the second wiring 62, the magnetic layer 522 in the peripheral circuit region 8 does not fit and there is no need to consider the margin. As a result, since the second wiring 62 of the peripheral circuit region 8 can be formed with a minimum design dimension, high integration can be achieved. In other words, since it is possible to eliminate the reduction in the wiring area due to the formation of the magnetic layer, the wiring resistance is reduced by increasing the wiring area by that amount. As a result, a wiring structure in which power consumption is reduced and heat generation is reduced is formed. Furthermore, signal delay is suppressed and high speed response is possible.

Next, a third embodiment according to the manufacturing method of the magnetic memory device of the present invention will be described with reference to the manufacturing process cross section of FIG. In this third embodiment, a manufacturing method of the second wiring (bit line), which is a feature of the present invention, will be described in detail. In addition, in Fig. 5, the memory cell region 6 is shown in the figure on the left toward the figure, and the peripheral circuit region 8 is shown in the figure on the right.

By the known technique, for example, an element isolation region for separating the element formation regions of the memory cell region 6 and the element formation regions of the peripheral circuit region 8 is formed in a semiconductor substrate, and the memory cell region ( A switch element for reading is formed in the element formation region of 6). This switch element can be formed with various switch elements, such as an n type or a V type field effect transistor, a diode, and a bipolar transistor. In the peripheral circuit region 8, desired elements, wirings and the like are formed.

A first insulating film is formed to cover the field effect transistor, the peripheral circuit region 8 and the like, and is connected to a first insulating film, for example, a contact connected to a lower element such as the switch element, wiring, or the like (for example, Tungsten plugs). Furthermore, a sense line for connecting to a contact, an electrode for connection, and the like are formed on the first insulating film.

A second insulating film is formed on the first insulating film. The second insulating film in the memory cell region 6 covers the sense line, the connecting electrode and the like. In the second insulating film, a contact (for example, a tungsten plug) to be connected to the connecting electrode is formed.

Next, a third insulating film is formed on the second insulating film. Next, the first wiring (write word line) is formed on the third insulating film by the method described with reference to Fig. 3 or the conventional writing word line forming method. In the method described with reference to Fig. 3, the first wiring (write word line) is formed in the memory cell region 6, and then the first wiring is formed in the peripheral circuit region 8. In the conventional writing word line forming method, the first wiring (write word line) is formed simultaneously in both the memory cell region 6 and the peripheral circuit region 8. Preferably it is the former method. Thereafter, a third insulating film is further formed to cover the first wiring. It is also possible to form a plug, a connection electrode, and the like in the memory cell region 6 by a process concurrent with the formation of the first wiring in the peripheral circuit region 8.

As shown in FIG. 5 (1), on the third insulating film (not shown), a conductive layer 131, a memory element (for example, TMR element) 13 of a magnetoresistance effect type, a conductive A cap layer (protective metal layer) 1335 is formed. Further, the fourth insulating film 44 is formed to fill the memory element 13, the cap layer 133, and the like. Thereafter, the upper surface of the cap layer 133 is exposed by chemical mechanical polishing, and the surface of the fourth insulating film 44 is planarized. The process up to this point can be performed by the existing method, and is not limited to the said process. Moreover, it is also possible to form the plug connected to lower wiring or an electrode in the said 4th insulating film 44 using the plug formation technique which connects existing upper wiring and lower wiring. As shown here, as an example, the plug 72 is formed in the peripheral circuit region 8. The formation of this plug 72 can use a conventional plug formation technique.

Further, an etch stop layer 451 is formed on the fourth insulating film 44, an interlayer insulating film 452 is further formed, and a fifth insulating film 45 is formed. The stopper insulating film 451 is formed of an insulating film which stops etching when the fifth insulating film 45 is etched, and is formed of, for example, a silicon nitride (SiN) film, a silicon carbide (SiC) film, or the like. The fifth insulating film 45 is, for example, an insulating material film such as a silicon oxide (SiO 2) film, a silicon oxide (SiOF) film containing fluorine, a silicon oxide carbide (SiOOC) film, an organic compound film, or two of them. It is formed as a laminated structure using more than one species.

Next, wiring is applied to the fifth insulating film 45 in the region where the bit lines are formed in the memory cell region 6 and the peripheral circuit region 8 by using a conventional resist coating technique, lithography technique, and etching technique. Grooves 453 and 454 are formed. Thereafter, the unnecessary resist mask is removed.

Subsequently, the first barrier metal layer 55 and the magnetic material are formed on the inner surface of the wiring grooves 453 and 454 and the surface of the fifth insulating film 45 by using a known film formation technique, for example, a sputtering method. The layer 521 is formed in order. The first barrier metal layer 55 may be a material that suppresses the reaction between copper and the magnetic body and at the same time suppresses the diffusion of the copper and the magnetic body. For example, tantalum (TA), tantalum nitride (TAN), tungsten, tungsten nitride, etc. are mentioned. As the magnetic layer 521, for example, a soft magnetic material having a maximum magnetic permeability μm of 100 or more can be used. Specifically, for example, an alloy containing at least one of iron, cobalt, and nickel, iron and aluminum ( Fe alloys or ferite alloys are used.

Next, the magnetic layer 521 and the first stripped layer 55 are anisotropically etched by a known etch back technique. As the etching gas, for example, a halogen gas containing chlorine or an etching gas to which carbon monoxide (CO) or ammonia (NH3) is added thereto is used. Furthermore, oxygen may be added. For example, a gas such as an etching gas for anisotropically etching the magnetic layer 521 and the first barrier metal layer 55 described in the second embodiment was used. As a result, sidewalls of the magnetic layer 521 are formed on the sidewalls of the wiring grooves 453 and 454 with the first barrier metal layer 55 interposed therebetween.

Next, the stopper insulating film 451 exposed to the bottoms of the wiring grooves 453 and 454 is removed by etching, for example, the cap layer 133 surface of the memory cell region 6 and the peripheral circuit region 8. To expose the surface of the plug 72. For example, a fluorine-based gas is used as the gas for etching the stopper insulating film 451. For example, the same gas as the etching gas of the stopper insulating film 451 described in the second embodiment was used.

Next, the second barrier metal layer 56 is formed by sputtering to include the inner surfaces of the wiring grooves 453 and 454 so as to cover the magnetic layer 521. The second barrier metal layer 56 is required to be a material that suppresses the reaction with copper and the diffusion of copper. For example, tantalum (Ta), tantalum nitride (TaN), tungsten, and tungsten nitride The same material as the said 1st barrier metal layer 55 may be sufficient, and another material may be sufficient as it.

Subsequently, after forming a copper seed layer (not shown) on the surface of the second barrier metal layer 56, a conductor (hereinafter referred to as copper film) is formed so as to fill the wiring grooves 453 and 454 by, for example, electrolytic plating. To record). This copper film consists of copper or a copper alloy, for example. As a result, the insides of the wiring grooves 453 and 454 are filled with the copper film, and the copper film is formed on the fifth insulating film 45 with the second barrier metal layer 56 interposed therebetween. Subsequently, the copper film on the second insulating film 42, the second barrier metal layer 56, the magnetic layer 521, and the first barrier metal layer 553 are subjected to, for example, a chemical mechanical polishing (CMP) method. And the second wirings 12 and 62 are formed using the copper film of the groove wiring structure as a main material.

Furthermore, as shown in FIG. 5 (2), the third barrier metal layer 58 is formed in order to suppress reaction with copper from the upper surface of the second wiring (including bit lines) 12 and diffusion of copper. Next, the magnetic layer 522 is formed. Furthermore, an antireflection film (not shown) may be formed. The third barrier metal layer 58 is, for example, an insulating film such as silicon nitride (SiN), silicon carbide (SiC), or tantalum (Ta) like the first and second barrier metal layers 55 and 560. , Tantalum nitride, tungsten, tungsten nitride, or the like can be used. The magnetic layer 522 can be formed of the same material as the magnetic layer 521. In addition, an antireflection film is not essential when the influence of the reflection from the base | substrate does not become a problem at the time of exposure of the subsequent lithography process. Here, the case where an antireflection film is not formed is demonstrated.

Next, using a conventional resist coating technique, a resist film (not shown) is formed on the magnetic layer 522. Next, by the lithography technique, the resist film is left only in the portion where the clad structure is to be left, that is, the upper portion of the portion where the TMR element is to be formed, and the resist film of the other portions is removed.

Thereafter, the resist film is used as an etching mask, and the magnetic layer 522 and the third barrier metal layer 58 are etched away by a known etching technique. This etching is performed by using the fifth insulating film 45 as an etching stop layer. In this way, the magnetic layer 521 formed on the sidewalls and the magnetic layer 52 formed of the magnetic layer 522 are formed on the upper and side surfaces of the bit line 12. In the case where the third barrier metal layer 58 is formed of an insulating film, the third barrier metal layer 58 may be left in the peripheral circuit region 8. Further, when the barrier metal layer is not formed on the second wiring 62 of the peripheral circuit region 8 by the above process, the second wiring 62 of the peripheral circuit region 8 is removed by another process. It is preferable to form the barrier metal layer to coat | cover.

In the third embodiment of the method for manufacturing the magnetic memory device, when the wiring groove 453 for forming the second wiring (bit line) 12 is formed in the fifth insulating film 45, the cap layer 1303 is formed. The etching is stopped by the stopper insulating film 451 covering the film. Then, the first barrier metal layer 55 and the magnetic layer 521 are sequentially formed on the inner surface of the wiring groove 453 and the surface of the fifth insulating film 45, and then the magnetic layer 521 of the bottom of the wiring groove 453. The first barrier metal layer 55 and the stopper insulating layer 451 are removed, and the top surface of the cap layer 133 is exposed, and at the same time, the magnetic layer 521 and the first barrier metal layer 55 on the fifth insulating layer 45 are removed. ), Sidewalls of the magnetic layer 521 are formed on the sidewalls of the wiring grooves 453 with the first barrier metal layer 55 therebetween. At that time, the upper surface of the cap layer 133 on the storage element 13 is exposed to the bottom of the wiring groove 453. Thereafter, a copper film (conductor), which is a main material of wiring, is embedded in the wiring groove 453 with the second barrier metal layer 56 interposed therebetween, and then the copper film and the second barrier metal on the fifth insulating film 45 are embedded. The layer 56 is removed and a second wiring (bit line) 12 made of copper film is formed in the wiring groove 453. As a result, the second wiring 12 of the memory cell region 6 is connected to the cap layer 133 above the memory element 13 with the second barrier metal layer 56 interposed therebetween. The second wiring 62) is connected to the plug 72 with the second barrier metal layer 56 interposed therebetween. Through such a process, it is possible to easily form the magnetic layer 55 covering the side surface of the second wiring 12 by the groove wiring formation technique.

Furthermore, after forming the third barrier metal layer 58 covering the bit line 12 of the memory cell region 6 on the fifth insulating film 45, the magnetic layer 522 is formed, and then the bit line. Patterning is carried out so as to leave the magnetic layer 522 and the third barrier metal layer 58 on (12), so that the sidewalls and top surfaces of the bit lines 12 are formed of the magnetic layer 521 and the magnetic layer formed on the sidewalls. It is almost covered by 522.

Furthermore, the magnetic layer 522 is not formed on the second wiring 62 of the peripheral circuit region 8. Therefore, although the magnetic layer 521 is formed on the sidewall of the second wiring 62 of the peripheral circuit region 8, the magnetic layer 522 is not formed directly on the second wiring 62. Therefore, it is not necessary to consider the margin without matching the magnetic layer 522 in the peripheral circuit region 8. As a result, since the second wiring 62 of the peripheral circuit region 8 can be formed with a minimum design dimension, high integration can be achieved.

As a method of forming the second wiring in the peripheral circuit region 8, the following method may be used in addition to the method described above.

For example, in the second embodiment according to the manufacturing method of the magnetic memory device, after the protective film 81 covering the bit line 12 of the memory cell region 6 is formed, the second embodiment is performed. As described above, the second wiring 62 is formed in the peripheral circuit region 8. Thereafter, the passivation layer 81 on the bit line 12 of the memory cell region 6 is removed, and the second wiring (on the bit line 12 and the peripheral circuit region 8 of the memory cell region 6 is removed. 62. The barrier metal layer 82 and the magnetic layer 522 are formed to cover the layer 62, and the barrier metal layer 82 and the magnetic layer 522 are formed in the shape of the bit line 12 and the second wiring 62. Patterning may be performed.

In each of the above embodiments, only the structure of the groove wiring is described, but the structure of forming the groove wiring and the connection hole formed at the bottom thereof in a simultaneous process, the so-called dual damascene structure, also includes the shape of the wiring structure. Does not ask. In addition, since conduction with the cap layer 133 of the storage element is achieved, conduction holes or the like may exist.

In each of the above embodiments, a process using the first and second barrier metal layers 55 and 56 and the barrier metal layer 82 is described, but the first wiring 11 is removed from the storage element 13 side. The first and second barrier metal layers 55 are covered with the magnetic layer 51, and the second wiring 12 is covered with the magnetic layer 52 with the storage element 13 side removed. 56 and the barrier metal layer 82 may be omitted.

In each said embodiment, it is also possible to form the barrier metal layer formed on the bit line 12 and on the 2nd wiring 62 with a cobalt tungsten phosphorus (COP-P-P) film, for example. . In this case, since the formation method is substitution plating with the wiring material, in the memory cell region, the magnetic layer 522 formed later and the magnetic layer 521 formed on the wiring side wall are formed so as to be connected to each other. Since the application efficiency of the current magnetic field to 13 is increased, writing with a lower current can be performed.

As described above, according to the magnetic memory device of the present invention, since a magnetic layer made of a high permeability layer is formed on both sides of the first wiring only in the memory cell region and on the side opposite to the surface facing the memory element. Since the use efficiency of the magnetic field generated in the first wiring is increased by the magnetic layer, the write current value to the memory element can be reduced. In addition, since the magnetic layer covering the first wiring is formed only in the memory cell region and not in the other peripheral circuit region, the magnetic layer is formed around the wiring in the first wiring of the peripheral circuit. Higher integration of the wiring is possible as long as it is not. In addition, since the wiring area can be increased as long as the magnetic layer is not formed, the wiring resistance can be reduced. As a result, the power consumption can be reduced and the amount of heat generated can be reduced. In addition, also in the second wiring, since a magnetic layer made of a high permeability layer is formed on both sides of the second wiring only in the memory cell region and on the surface opposite to the surface facing the memory element, the same as the first wiring. You can get the effect.

According to the manufacturing method of the magnetic memory device of the present invention, both sides of at least one of the first wiring (write word line) and the second wiring (bit line) of the memory cell region and the side opposite to the surface facing the memory element are provided. Since it has a so-called clad structure which forms a magnetic layer composed of a high permeability layer on the surface thereof, it is possible to manufacture a magnetic memory device having improved utilization efficiency of a magnetic field. As a result, it is possible to reduce the write current value to the memory device, and therefore it is possible to manufacture a magnetic memory device having low power consumption and low heat generation. In the peripheral circuit region other than the memory cell, it is possible to use a conventional wiring forming technique.

Claims (9)

A magnetic memory device in which a memory cell area and a peripheral circuit area are mounted on the same substrate. The memory cell area is The first wiring, A second wiring three-dimensionally intersecting with the first wiring; A magnetoresistive effect memory element for storing and reproducing information on the magnetic spins in an intersection region of the first wiring and the second wiring; The peripheral circuit area is A first wiring of the same wiring layer as the first wiring of the memory cell region, A second wiring of the same wiring layer as the second wiring of the memory cell region, A magnetic memory device comprising a high magnetic permeability layer formed on both sides of the first wiring only in the memory cell region and on a surface opposite to the surface facing the memory element. A magnetic memory device in which a memory cell area and a peripheral circuit area are mounted on the same substrate. The memory cell area is The first wiring, A second wiring three-dimensionally intersecting with the first wiring; A magnetoresistive effect memory element for storing and reproducing information on the magnetic spin in an intersection region of the first wiring and the second wiring; The peripheral circuit area is A first wiring of the same wiring layer as the first wiring of the memory cell region, A second wiring of the same wiring layer as the second wiring of the memory cell region, A magnetic memory device comprising a high magnetic permeability layer formed on both sides of the second wiring only in the memory cell area and on a surface opposite to the surface facing the memory element. The method of claim 1, A magnetic memory device comprising a high magnetic permeability layer formed on both sides of the second wiring only in the memory cell area and on a surface opposite to the surface facing the memory element. The method of claim 2, A magnetic memory device comprising a high magnetic permeability layer formed on a portion of the second wiring in the peripheral circuit area. A method of manufacturing a magnetic memory device in which a memory cell region and a peripheral circuit region are mounted on the same substrate. Forming a first wiring, Forming a tunnel magnetoresistive element electrically insulated from the first wiring by sandwiching the tunnel insulation layer with a ferromagnetic material; Electrically connecting the tunnel magnetoresistive element to form a second interconnection intersecting the first interconnection in three dimensions with the tunnel magnetoresistive element interposed therebetween, Forming the second wiring; Forming a second wiring of the memory cell region; Forming a second wiring of the peripheral circuit region; The process of forming the second wiring of the memory cell region is Forming a wiring groove in an area forming the memory cell area of the substrate; Forming a magnetic layer composed of a high permeability layer on the side of the wiring groove; And forming a first wiring on the side surface of the wiring groove through the magnetic layer. A method of manufacturing a magnetic memory device for forming a memory cell region and a peripheral circuit region on the same substrate, Forming a first wiring, Forming a tunnel magnetoresistive element electrically insulated from the first wiring by sandwiching the tunnel insulation layer with a ferromagnetic material; Electrically connecting the tunnel magnetoresistive element to form a second interconnection intersecting the first interconnection in three dimensions with the tunnel magnetoresistive element interposed therebetween, Forming the first wiring; Forming a first wiring of the memory cell region; Forming a first wiring of the peripheral circuit region; The process of forming the first wiring of the memory cell region is Forming a wiring groove in an area forming the memory cell area of the substrate; Forming a magnetic layer comprising a high permeability layer on an inner surface of the wiring groove; And forming a first wiring through the magnetic layer in the wiring groove. The method of claim 5, The step of forming the second wiring, Forming a second wiring of the memory cell region; Forming a second wiring of the peripheral circuit region; Forming a second wiring of the memory cell region, Forming a wiring groove in an area forming the memory cell area of the substrate; Forming a magnetic layer composed of a high permeability layer on the side of the wiring groove; Forming a second wiring on the side surface of the wiring groove with the magnetic layer interposed therebetween; A method of manufacturing a magnetic memory device, comprising the step of forming a magnetic layer comprising a high permeability layer on the second wiring. The method of claim 5, When the wiring groove is formed in the region forming the memory cell region of the substrate, the wiring groove is also formed in the region forming the peripheral circuit region of the substrate, Forming a magnetic layer composed of a high permeability layer on the side surface of the wiring groove of the region forming the memory cell region and the region forming the peripheral circuit region; Forming a second wiring on the side of the wiring groove of the region forming the memory cell region and the peripheral circuit region, and filling the wiring groove with the magnetic layer interposed therebetween; A method of manufacturing a magnetic memory device, characterized in that a magnetic layer composed of a high permeability layer is formed on a second wiring only in the memory cell region. When the wiring groove is formed in the region forming the memory cell region of the substrate, the wiring groove is also formed in the region forming the peripheral circuit region of the substrate, Forming a magnetic layer composed of a high permeability layer on the side surface of the wiring groove of the region forming the memory cell region and the region forming the peripheral circuit region; Forming a second wiring on the side of the wiring groove of the region forming the memory cell region and the peripheral circuit region, and filling the wiring groove with the magnetic layer interposed therebetween; And forming a magnetic material layer comprising a high permeability layer on the second wiring of only the memory cell region.