JP2008021816A - Method of manufacturing nonvolatile magnetic memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture a magnetic memory element by a self-aligned forming method without using the lithography in a nonvolatile magnetic memory manufacturing method. <P>SOLUTION: The method of manufacturing a nonvolatile magnetic memory with magnetic memory elements 3 comprises a step of forming a surface-exposed conductor 51 on a first insulation film 41 formed on a substrate, removing the top of the conductor 51 to form recesses 52 in the insulation film 41 on the conductor 51, forming a magnetic memory element film 61 for forming the magnetic memory elements 3 and a cap film 37 on the insulation film 41 including the insides of the recesses 52 so as to have depressions 38 on the cap film 37 upside on the conductor 51, forming a second insulation film 42 in the depressions 38, and removing the cap layer 37 and the memory element film 61 with the second insulation film 42 used as a mask to form the magnetic memory elements 3 capped with the cap film 37 from the memory element film 61 left in the recesses 52. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a nonvolatile magnetic memory device including a magnetic memory element having a recording layer that stores information by changing a resistance value depending on a magnetization reversal state.

  With the rapid spread of information communication devices, especially small personal devices such as mobile terminals, the memory elements and logic elements that make up these devices will become even more powerful, including higher integration, higher speed, and lower power consumption. Is required. In particular, nonvolatile memory is considered indispensable in the ubiquitous era. Non-volatile memory can protect important personal information even when power is consumed or troubled, or when the server and network are disconnected due to some kind of failure. In addition, recent portable devices are designed to reduce power consumption as much as possible by putting unnecessary circuit blocks in a standby state. And waste of memory can be eliminated. In addition, an “instant-on” function that can be activated instantly when the power is turned on will be possible if a high-speed, large-capacity nonvolatile memory can be realized.

  Examples of the nonvolatile memory include a flash memory using a semiconductor, and a FRAM (Ferro electric Random Access Memory) using a ferroelectric. However, the flash memory has a drawback that the writing speed is as slow as the order of μ seconds. On the other hand, FRAM has a problem that the number of rewritable times is 1 tera (T) to 100 tera (T) times, and the durability is low to completely replace SRAM and DRAM. The problem that processing is difficult has been pointed out.

  A magnetic memory called MRAM attracts attention as a non-volatile memory that does not have these drawbacks. This magnetic memory has attracted attention due to the recent improvement in characteristics of TMR (Tunnel Magnetoresistance) materials (see, for example, Non-Patent Document 1).

  The MRAM has a simple structure and can be easily integrated. In addition, the MRAM has a large number of rewritable times for recording by rotating the magnetic moment. The access time is also expected to be very high, and it has already been reported that it can operate at 100 MHz (for example, see Non-Patent Document 2).

  Here, the configuration of a general MRAM will be described with reference to the schematic perspective view of FIG.

  As shown in FIG. 7, an element isolation layer 102 is formed on a semiconductor substrate 110 made of a silicon substrate or the like, and a selection transistor for selecting each memory cell is formed in a region isolated by the element isolation layer 102. Has been. That is, a gate electrode 101 is formed on a semiconductor substrate 110 via a gate insulating film (not shown), a drain region 108 is formed on the semiconductor substrate 110 on one side of the gate electrode 101, and the semiconductor substrate 110 is formed on the other side. A source region 107 is formed. A word line 105 extending in the gate width direction of the gate electrode is provided above the gate electrode 101. The drain region 108 serves as a common drain for the two selection transistors. A wiring 109 is connected to the drain region 108.

  A bit line 106 is formed above the word line 105 so as to intersect the word line 105. Between the word line 105 and the bit line 106, a magnetic memory element 103 having a recording layer that is connected to the bit line 106 and whose magnetization direction is reversed is disposed. The magnetic memory element 103 is composed of, for example, a magnetic tunnel junction element (MTJ element). Further, one end of a bypass line 111 arranged in parallel with the bit line 106 is connected to the lower side of the magnetic memory element 103, and the other end side of the bypass line 111 is connected to the source region 107 via a contact 104. Is electrically connected.

  In the MRAM, a current magnetic field is applied to the magnetic memory element 103 by passing currents through the word line 105 and the bit line 106, thereby reversing the magnetization direction of the recording layer of the magnetic memory element 103 and Recording can be performed. In order to stably hold recorded information in a magnetic memory such as MRAM, it is necessary that the magnetic layer (recording layer) for recording information has a certain coercive force. On the other hand, in order to rewrite the recorded information, a certain amount of current must be passed through the address wiring.

  However, as the elements constituting the MRAM become finer, the address wiring becomes thinner, so that a sufficient current cannot flow. In view of this, attention has been focused on a memory that uses magnetization reversal by spin injection as a structure that can perform magnetization reversal with a smaller current (see, for example, Patent Document 1).

  Magnetization reversal by spin injection is to cause magnetization reversal in another magnetic material by injecting spin-polarized electrons that have passed through the magnetic material into another magnetic material. For example, when a current is passed through a giant magnetoresistive element (GMR element) or a magnetic tunnel junction element (MTJ element) in a direction perpendicular to the film surface, magnetization of at least a part of the magnetic layer of these elements is performed. Can be reversed. Magnetization reversal by spin injection has an advantage that magnetization reversal can be realized without increasing current even if the element is miniaturized.

  In FIG. 8, the right vertical axis represents the spin RAM (SpRAM) cell size (F2), the left vertical axis represents the write current, and the horizontal axis represents the short side size of the MTJ element. As shown in FIG. 8, the spin RAM has a feature that the write current is reduced as the MTJ element size is reduced. In addition, the write current is about the same cell size as the embedded DRAM, and the write current is as low as 100 μA. On the other hand, the conventional MRAM has a feature that the write current is greatly increased as the MTJ element size is reduced. Moreover, when the cell size is about the same as that of a 6-transistor type SRAM (6TSRAM), the write current is about 1 mA.

  A memory device having a configuration utilizing the above-described magnetization reversal by spin injection will be described with reference to a schematic perspective view of FIG. 9 and a schematic cross-sectional view of FIG.

  As shown in FIGS. 9 and 10, an element isolation layer 152 is formed on a semiconductor substrate 160 made of a silicon substrate or the like, and for selecting each memory cell in a region separated by the element isolation layer 152 A transistor is formed. That is, a gate electrode 151 is formed on a semiconductor substrate 160 via a gate insulating film (not shown), a drain region 158 is formed in the semiconductor substrate 160 on one side of the gate electrode 151, and the semiconductor substrate 160 is formed on the other side. A source region 157 is formed. The gate electrode 151 also serves as a word line. The drain region 158 serves as a common drain for the two selection transistors. A wiring 159 is connected to the drain region 158 via a contact 154c.

  A bit line 156 is formed above the gate electrode (word line) 151 so as to intersect the gate electrode 151. The source region 157 and the bit line 156 are connected to the source region 157 via a contact 154a and to the bit line 156 via a contact 154b. The direction of magnetization is reversed by spin injection. A magnetic storage element 153 having a recording layer is disposed. The magnetic memory element 153 is composed of, for example, a magnetic tunnel junction element (MTJ element).

  As shown in FIG. 10, in the magnetic memory element 153, for example, a magnetic layer 161 and a magnetic layer 162 are formed so as to sandwich a tunnel insulating layer, and one of the two magnetic layers 161 and 162 is formed. The magnetic layer is a magnetization fixed layer whose magnetization direction is fixed, and the other magnetic layer is a magnetization free layer in which the magnetization direction changes, that is, a recording layer.

  In addition, since the magnetic memory element 153 is connected to the bit line 156 and the source region 157 via contacts 154a and 154b, a current is passed through the magnetic memory element 153 to change the magnetization direction of the recording layer by spin injection. Can be reversed. Such a memory structure using magnetization reversal by spin injection has a feature that the device structure can be simplified as compared with the general MRAM shown in FIG. Further, by utilizing magnetization reversal by spin injection, there is an advantage that the write current does not increase even if the element is miniaturized as compared with a general MRAM that performs magnetization reversal by an external magnetic field.

  However, in the spin transfer magnetization reversal, the write current is about 400 μA in an ellipse with an element size of 100 nm × 150 nm, and a further lower current is required (see Non-Patent Document 3, for example).

  In order to reduce power consumption, it is necessary to improve spin injection efficiency and reduce input current. Further, in order to increase the read signal, it is necessary to secure a large magnetoresistance change rate, and it is effective to use an intermediate layer in contact with the information recording layer as a tunnel barrier layer. In that case, the withstand voltage of the barrier layer is limited, and it is necessary to suppress the current at the time of spin injection also from this point.

  Further, as described above, the current for writing is controlled by the element selection transistor connected in series to the magnetic memory element, but it is also necessary to suppress the write current within the range of the drive capability of this transistor.

  The write current is generally considered to have a relationship as shown in the following equation (1). In the equation (1), Ms is the saturation magnetization of the storage layer material, V is the volume of the storage layer material, η is the write current efficiency, and α is the damping factor.

  Write current threshold (T = 0K): Ic0∝α / η · Ms · V (1)

  As described above, in order to realize a large-capacity and high-density memory using the spin injection phenomenon, it is essential to reduce the write current threshold. For this purpose, it is first necessary to develop a magnetic memory material that has high write current efficiency and a reduced damping factor.

  On the other hand, since the write current threshold is proportional to the volume of the storage layer, a simple method for reducing the current is to reduce the element size. That is, the write current threshold value can also be reduced by miniaturizing the magnetic memory element.

  In order to form a magnetic memory element, fine dot patterning is required, and EB drawing exposure is mainly used in the development stage. However, it is considered difficult to apply to mass production of a large capacity memory of several Mbit or more because of the length of drawing time.

  On the other hand, in photolithography widely used in the CMOS process, it is not easy to realize fine dot patterning on the second or higher wiring layer in consideration of DOF. If possible, it is desirable to realize element patterning without lithography.

In order to realize a large-capacity memory, it is necessary to reduce the cell size. In this case, it is necessary to ensure not only the element size but also the overlay accuracy with the base.

  As described above, in order to realize a large-capacity spin memory, there is a demand for a self-aligned element formation process that does not require lithography and does not need to have an overlay accuracy margin.

  Therefore, the present invention proposes a technique for patterning a magnetic memory element by using a step of a base pattern without using a lithography technique for patterning the magnetic memory element. Thereby, it is not necessary to provide an overlap margin, and the cell size can be reduced.

JP 2003-17782 A Wang et al., `` Feasibility of Ultra-Dense Spin-Tunneling Random Access Memory '' IEEE Transactions on Magnetics, Vol.33 November 1997, p.4498-4512 R. Scheuerlein et al., `` A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell '' 2000 IEEE International Solid-State CirCuits Conference Digest of Technical Papers, Feb. 2000, p.128 -129, M. Hosomi et al., “A Novel Nonvolatile Memory with Spin Torque Magnetization Switching: Spin-RAM”

  A problem to be solved is that it is difficult to form a large-capacity spin memory in a process for forming a memory element using an optical lithography technique or an electron beam lithography technique.

  The present invention relates to a non-volatile magnetic memory device including a self-aligned magnetic memory element forming process that does not require lithography and does not need to have an overlay accuracy margin in order to realize a large-capacity spin memory. An object of the present invention is to propose a manufacturing method.

  A method for manufacturing a nonvolatile magnetic memory device according to the present invention is a method for manufacturing a nonvolatile magnetic memory device including a magnetic memory element having a recording layer for storing information by changing a resistance value depending on a magnetization reversal state. The manufacturing process of the magnetic memory element includes a step of forming a conductive layer having a surface exposed on a first insulating film formed on a substrate, and removing the upper portion of the conductive layer to form the first insulating film. Forming a recess on the conductive layer, and forming a magnetic memory element film and a cap film for forming the magnetic memory element on the first insulating film including the inside of the recess. Forming a recess on the upper surface of the cap film; forming a second insulating film in the recess; and removing the cap layer and the magnetic memory element film using the second insulating film as a mask. The magnet left in the recess It consists of memory element layer, characterized by comprising a step of forming a magnetic memory element which carries the cap layer.

  In the method for manufacturing a nonvolatile magnetic memory device according to the present invention, patterning of the magnetic memory element is performed by using the step of the concave portion, so that element arrangement and cell design are possible without providing an overlap margin with the base.

  According to the method of manufacturing a nonvolatile magnetic memory device of the present invention, a lithography technique necessary for forming a magnetic memory element is unnecessary, and a large-capacity spin memory can be realized at low cost. Further, there is an advantage that it is not necessary to provide an overlap margin with the base layer, the cell size can be reduced, and high integration is possible.

  One embodiment (example) according to the method for manufacturing a nonvolatile magnetic memory device of the present invention will be described with reference to the manufacturing process sectional views of FIGS.

  Although not shown, a selection transistor is formed in the active region surrounded by the element isolation region on the semiconductor substrate. The selection transistor is covered with an insulating film. In this insulating film, plugs and landing pad portions connected to the selection transistors are formed, and sense lines, word lines, and the like are further formed.

  As shown in FIG. 1A, a conductor 51 whose surface is exposed on the insulating film (first insulating film) 41 is formed. Then, the upper portion of the conductor 51 is removed, and a recess 52 is formed in the first insulating film 41 on the conductor 51. The conductor 51 is made of, for example, copper wiring, and the wiring material is connected to a recess 50 such as a groove and a connection hole formed in the first insulating film 41 via a barrier film (not shown) that prevents copper diffusion and oxidation. This is formed by burying copper to be removed and removing an excess barrier film and copper (Cu) on the first insulating film 41. This removal process is performed by chemical mechanical polishing, for example.

  Next, an example of a method for forming the recess 52 will be described.

  As a method (first example) for forming the recess 52, first, as a conductive film for forming the conductor 51, a wiring material is provided via a barrier film (not shown) that prevents diffusion and oxidation of copper. (Not shown) is formed on the first insulating film 41 so as to fill the recess 50 formed in the first insulating film 41. Subsequently, the surplus conductive film on the first insulating film 41 is removed by a polishing technique, for example, chemical mechanical polishing (CMP), and the conductor 51 made of the conductive film is formed in the recess 50. Form. In the chemical mechanical polishing at this time, the conductive film 51 is recessed (retreated) by overpolishing the conductive film, and the concave portion 52 is formed in the first insulating film 41 on the conductive material 51. .

  Usually, the recess amount of the conductor 51 tends to increase in proportion to the over-polishing time. Generally, the copper overpolishing time is set to about 30% of the copper polishing end time, but in order to increase the recess amount, an overpolishing time of about 50% to 100% is required. As an example, when silicon carbide oxide (SiOC) is used for the first insulating film 41, a general chemical mechanical polishing (CMP) apparatus is used, and as an example of polishing conditions, a silica-based slurry is used as a polishing slurry. For example, a pad made of polyurethane foam is used for the pad, the polishing speed (for example, the rotation speed of the platen of the polishing apparatus) is set to 60 rpm to 100 rpm, and the processing pressure is set to 150 hPa to 200 hPa. Was over-polished.

As a method of forming the recess 52 (second example), the recess 52 is formed by utilizing a polishing rate difference between the first insulating film 41 and the conductor 51 by selecting a slurry of chemical mechanical polishing. In general, it has been found that, in chemical mechanical polishing, the amount of recess increases when a slurry that is more weighted than chemical polishing is used rather than mechanical polishing. An example of such a slurry is a silica-based slurry. As an example of the chemical mechanical polishing condition of copper in this case, a polishing pad made of, for example, polyurethane foam is used, the polishing speed (for example, the rotation speed of the platen of the polishing apparatus) is 60 rpm to 100 rpm, and the processing pressure is 150 hPa to 200 hPa. It was set the supply amount of the slurry to 100cm ³ / min~200cm ³ / min.

  Next, an example of another method for forming the recess 52 will be described.

  A concave portion in which a wiring material (not shown) is formed in the first insulating film 41 through a barrier film (not shown) that prevents copper diffusion and oxidation as a conductive film for forming the conductor 51. 50 is formed on the first insulating film 41 so as to be embedded. Next, an excessive conductive film on the first insulating film 41 is removed by a polishing technique, for example, chemical mechanical polishing, and the conductor 51 made of the conductive film is formed in the recess 50. Thereafter, the recess 51 is formed in the first insulating film 41 on the conductor 51 by removing the conductor 51.

  As a method for forming the recess 52 (third example), a conductor 51 that fills the recess 50 formed in the first insulating film 41 is formed by chemical mechanical polishing of copper, and then reverse sputtering with Ar ions is performed. Then, the conductor 51 is selectively removed from the first insulating film 41, a desired recess amount is obtained, the conductor 51 is recessed, and the recess 52 is formed on the conductor 51 of the first insulating film 41. Form. In this case, the sputtering rate difference between the first insulating film 41 and the conductor 51 is used. In this method, since the recess amount can be set uniformly over the entire surface of the substrate, the recess 51 can be formed in the substrate surface with good depth uniformity.

  In addition, as a method (fourth example) for forming the recess 52, a conductor 51 for embedding the recess 50 formed in the first insulating film 41 is formed by chemical mechanical polishing of copper, and then wet etching is performed. Then, the conductive material 51 is chemically removed and processed selectively with respect to the first insulating film 41, a desired recess amount is obtained, the conductive material 51 is recessed, and the conductive material 51 on the first insulating film 41 is formed on the conductive material 51. A recess 52 is formed. In this case, it is necessary to slow down the etching rate and improve controllability.

As a method of chemically removing the conductor 51 selectively with respect to the first insulating film 41, only the surface portion of the conductor 51 made of copper is oxidized using hydrogen peroxide (H ₂ O ₂ ). To form copper oxide. The recess can be formed by etching the copper oxide with an organic acid (for example, an acid for etching copper such as oxalic acid or citric acid). Since the oxidation of copper hardly proceeds in the depth direction, the amount of recess can be adjusted by repeating the above operation.

  In the first to fourth examples, the recess 52 is a region where a magnetic memory element is formed in a later step. Since this magnetic memory element needs to have shape anisotropy, it needs to be formed in an elliptical shape. Accordingly, the recess 52 needs to be formed in an oval shape, an oval shape, or a rectangular shape. That is, the recess 50 formed in the first insulating film 51 also needs to be formed in an oval shape, an oval shape, or a rectangular shape. Further, the recess 52 is formed in a state deeper than the thickness of the magnetic memory element film in which the magnetic memory element to be formed in a later step is formed, for example, the depth is about 50 nm.

  Next, as shown in FIG. 1B, a magnetic memory element (for example, MTJ element, MTJ is an abbreviation of Magnetic Tunnel Junction) is formed on the first insulating film 41 including the inside of the recess 52. The memory element film 61 and the cap film 37 are formed. At this time, the upper surface of the cap film 37 on the conductor 51 is formed to have a recess 38.

  The detailed structure of the magnetic memory element film 61 will be described with reference to the schematic sectional view of FIG.

  As shown in FIG. 4, the magnetic memory element film 61 includes, for example, a first ferromagnetic layer 31 including a base electrode 30, an antiferromagnetic layer 32, and a magnetization fixed layer 33 on a first insulating film 41. , A tunnel insulating layer 34, and a second ferromagnetic layer serving as a recording layer (magnetization free layer) 35, and a conductive top coat on the recording layer 35. A film 36 is formed.

First, the base electrode 30 is formed with a thickness of 10 nm using, for example, a tantalum (Ta) film. This film forming method is based on, for example, a sputtering method. As an example of the film formation conditions, argon is used as the process gas, the supply flow rate is set to 100 cm ³ / min, the pressure in the film formation atmosphere is set to 0.6 Pa, and the DC power is set to 200 W.

Next, the antiferromagnetic material layer 32 is formed to a thickness of 20 nm using, for example, a platinum manganese (Pt—Mn) alloy. This film forming method is based on, for example, a sputtering method. As an example of the film formation conditions, argon is used as the process gas, the supply flow rate is set to 100 cm ³ / min, the pressure in the film formation atmosphere is set to 0.6 Pa, and the DC power is set to 200 W.

  Next, the magnetization fixed layer 33 is formed. The magnetization fixed layer 33 may have a multilayer structure (for example, a ferromagnetic material layer / metal layer / ferromagnetic material layer) having a synthetic antiferromagnetic coupling (SAF), and more specifically, an example. As a lower layer, it has a three-layer structure of a cobalt iron alloy layer, a ruthenium layer, and a cobalt iron alloy layer. The magnetization pinned layer 33 is pinned in the direction of magnetization by exchange coupling with the antiferromagnetic material layer 32.

First, a lowermost cobalt iron (Co—Fe) alloy layer is formed to a thickness of 2 nm, for example. This film forming method is based on, for example, a sputtering method. As an example of the film formation conditions, argon is used as the process gas, the supply flow rate is set to 50 cm ³ / min, the pressure of the film formation atmosphere is set to 0.3 Pa, and the DC power is set to 100 W. Subsequently, an intermediate ruthenium (Ru) layer is formed to a thickness of 1 nm, for example. This film forming method is based on, for example, a sputtering method. As an example of the film formation conditions, argon is used as the process gas, the supply flow rate is set to 50 cm ³ / min, the pressure of the film formation atmosphere is set to 0.3 Pa, and the DC power is set to 50 W. Subsequently, an uppermost cobalt iron (Co—Fe) alloy layer is formed to a thickness of 2 nm, for example. This film forming method is based on, for example, a sputtering method. As an example of the film formation conditions, argon is used as the process gas, the supply flow rate is set to 50 cm ³ / min, the pressure of the film formation atmosphere is set to 0.3 Pa, and the DC power is set to 100 W.

Next, the tunnel insulating layer 34 is formed to a thickness of 0.5 nm to 1.5 nm using, for example, magnesium oxide. This film forming method is based on, for example, a sputtering method. As an example of the film formation conditions, argon is used as the process gas, the supply flow rate is set to 100 cm ³ / min, the pressure in the film formation atmosphere is set to 1.0 Pa, and the DC power is set to 500 W.

Next, the recording layer 35 is formed. The direction of magnetization of the recording layer 35 is changed to be parallel or anti-parallel to the magnetization fixed layer 33 depending on the direction of current flow. For example, a cobalt iron boron (Co—Fe—B) layer is formed to a thickness of 3 nm. This film forming method is based on, for example, a sputtering method. As an example of the film formation conditions, argon is used as the process gas, the supply flow rate is set to 50 cm ³ / min, the pressure of the film formation atmosphere is set to 0.3 Pa, and the DC power is set to 200 W.

  The magnetization fixed layer 33 and the recording layer 35 that is a magnetization free layer may be a single layer or a multilayer film having a synthetic anti-ferromagnetic coupling (SAF).

Next, the top coat film 36 is formed with a thickness of 5 nm, for example, with tantalum (Ta). This film forming method is based on, for example, a sputtering method. As an example of the film formation conditions, argon is used as the process gas, the supply flow rate is set to 100 cm ³ / min, the pressure in the film formation atmosphere is set to 0.6 Pa, and the DC power is set to 200 W.

Next, as shown in FIG. 1B, on the magnetic memory element film 61, which is also a hard mask layer for etching, mutual diffusion between the magnetic memory element and the wiring connecting the magnetic memory element is performed. A cap film 37 having functions of preventing, reducing contact resistance and preventing oxidation of the recording layer 35 is formed of, for example, titanium nitride (TiN) or titanium (Ti) film to a thickness of 100 nm. This film forming method is based on, for example, a sputtering method. As an example of the film formation conditions, argon is used as the process gas, the supply flow rate is set to 65 cm ³ / min, the pressure of the film formation atmosphere is set to 0.3 Pa, and the DC power is set to 10 kW. In the state where the cap film method is formed, a recess 38 is formed in the cap film method on the conductor 51. Since the second insulating film that becomes an etching mask remains in the recess 38 in a later step, the recess 38 is formed to a depth sufficient to leave the second insulating film.

  The film formation from the base electrode 30 to the cap film 37 is preferably performed in-situ, for example, without opening to the atmosphere for each film formation. For example, the sputtering target is exchanged in the same chamber. The film is formed by moving in a plurality of chambers that are formed or connected.

Next, a second insulating film 42 is formed on the cap film 37. The second insulating film 42 is made of, for example, silicon oxide (SiO ₂ ). In this film formation, it is necessary to embed the recess 38 with the second insulating film 42. Therefore, the film formation method is, for example, a bias high density plasma CVD (HDP-CVD) method having excellent embeddability. The film forming conditions, as an example, the process gas, monosilane (SiH ₄₎ and oxygen (O ₂₎ argon using a mixed gas of (Ar), 60cm ³ / min each supply flow rate, 120 cm ³ / min 130 cm ³ / min. The RF power of the film forming apparatus is set to 1.5 kW at the top and 3 kW at the side, for example.

Next, as shown in FIG. 1C, the surface of the second insulating film 42 is flattened and the surface of the cap film 37 is exposed, leaving the second insulating film 42 only in the recess 38. . In this flattening step, chemical mechanical polishing is used. At that time, it is preferable to use a slurry that stops chemical mechanical polishing at the cap film 37. For example, a cerium oxide slurry is used. As an example of chemical mechanical polishing conditions in this case, a polishing pad made of, for example, polyurethane foam is used, the polishing speed (for example, the rotation speed of the platen of the polishing apparatus) is 80 rpm to 120 rpm, the processing pressure is 150 hPa to 300 hPa, and the slurry is the supply amount was set to 100cm ³ / min~200cm ³ / min. As a result of this polishing, the second insulating film 42 is embedded in the recess 38 formed on the surface of the cap film 37.

Next, as shown in FIG. 2 (4), the cap film 37 is removed using the second insulating film 42 as a mask to leave the cap film 37 only in the recess 38. This removal processing is performed by, for example, etching or ion milling. When this removal process is performed by etching, for example, reactive ion etching is performed. The etching conditions include, for example, chlorine (Cl ₂ ), boron trichloride (BCl ₃ ), and nitrogen (N ₂ ) as an etching gas. The supply flow rates are set to 60 cm ³ / min, 80 cm ³ / min, and 10 cm ³ / min, respectively. The source power of the etching apparatus is set to 1 kW, the bias power is set to 150 W, and the pressure of the etching atmosphere is set to 1 Pa.

2 (5), the magnetic memory element film 61 is processed to form the magnetic memory element 3 using the second insulating film 42 and the cap film 37 as a mask. This processing is performed by, for example, reactive ion etching. As an example of the etching conditions, carbon monoxide (CO) and ammonia (NH ₃ ) are used as the etching gas, and the respective supply flow rates are set to 25 cm ³ / min and 75 cm ³ / min. The source power of the etching apparatus is set to 1.2 kW, the bias power is set to 200 W, and the pressure of the etching atmosphere is set to 0.53 Pa.

  Instead of the reactive ion etching method, the magnetic memory element 3 can also be formed by an ion milling method (ion beam etching method).

  Thereafter, deposits, etching gas residue, particles, etching residues and the like deposited on the sidewalls are removed by washing with water or organic cleaning liquid, aerosol, or the like.

  Thus, the recording layer 35 is made of a ferromagnetic material and stores information by changing the resistance value depending on the magnetization reversal state (see FIG. 4). The MTJ element (tunnel magnetoresistive element) Thus, the magnetic memory element 3 can be obtained.

Next, as shown in FIG. 2 (6), a third insulating film 43 is formed on the first insulating film 41 so as to cover the magnetic memory element 3, the cap film 37, and the like. The third insulating film 43 is made of, for example, silicon oxide. This film forming method is based on, for example, a bias high density plasma CVD (HDP-CVD) method. The film forming conditions, as an example, the process gas, monosilane (SiH ₄₎ and oxygen (O ₂₎ argon using a mixed gas of (Ar), 60cm ³ / min each supply flow rate, 120 cm ³ / min 130 cm ³ / min. The RF power of the film forming apparatus is set to 1.5 kW at the top and 3 kW at the side, for example.

Next, as shown in FIG. 3 (7), the surface of the third insulating film 43 is flattened, the third insulating film 43 is embedded in the recess 52, and the surface of the cap film 37 is exposed. . In this flattening step, chemical mechanical polishing is used. At that time, it is preferable to use a slurry that stops chemical mechanical polishing at the cap film 37. For example, a cerium oxide slurry is used. As an example of chemical mechanical polishing conditions in this case, a polishing pad made of, for example, polyurethane foam is used, the polishing speed (for example, the rotation speed of the platen of the polishing apparatus) is 80 rpm to 120 rpm, the processing pressure is 150 hPa to 300 hPa, and the slurry is the supply amount was set to 100cm ³ / min~200cm ³ / min. In this polishing, the second insulating film 42 [see FIG. 2 (5)] remaining on the cap film 37 is also removed.

  Next, as shown in FIG. 3 (8), a wiring 62 connected to the cap film 37 is formed. First, a fourth insulating film 44 is formed on the third insulating film 43 (first insulating film 41) so as to cover the cap film 37. After the wiring groove 45 is formed in the fourth insulating film 44, a barrier film (not shown) used for the copper wiring, for example, a tantalum (Ta) film is formed, and then a copper wiring material is embedded in the wiring groove 45, Excess wiring material and barrier film on the 4 insulating film 44 are removed, and wiring 62 made of wiring material is formed in the wiring groove 45 through the barrier film. As described above, the wiring 62 is formed by a wiring forming technique used in a back end process of a general CMOS process.

  In the method of manufacturing the nonvolatile magnetic memory device of the present invention, the magnetic memory element 3 is formed in the recess 52 in a self-aligned manner in order to perform patterning of the magnetic memory element film 61 using the step of the recess 52. Therefore, it is possible to arrange the magnetic memory element 3 and to design the cell without providing an allowance for overlapping with the underlying conductor 51. As described above, since a lithography technique that has been conventionally required for forming the magnetic memory element 3 is not required, a large-capacity spin memory can be realized at low cost. In addition, there is no need to provide an overlay margin with the conductor 51 of the base layer, and there is an advantage that the cell size can be reduced and high integration can be achieved.

  Next, an example of the nonvolatile magnetic memory device formed by the above manufacturing method will be described with reference to the schematic configuration cross-sectional view of FIG. 5 and the layout plan view of FIG. FIG. 5 is a drawing showing a cross-sectional structure of a memory cell of an MRAM having one selection element and one MTJ element (1T1J type). FIG. 6 shows the layout of the word line, magnetic memory element, bit line, etc. of the MRAM shown in FIG. 5, and illustration of the semiconductor substrate, sense line, selection transistor, etc. is omitted.

  As shown in FIGS. 5 and 6, the selection transistor 2 is formed in the active region surrounded by the element isolation region 11 in the semiconductor substrate 10. The selection transistor 2 is composed of a MOS type FET. Specifically, a gate electrode 22 formed on the semiconductor substrate 10 via a gate insulating film 21 and the semiconductor substrate on both sides of the gate electrode 22. 10 is formed of an impurity layer (source region) 23 and an impurity layer (drain region) 24 formed on the substrate 10. The selection transistor 2 is covered with a first interlayer insulating film 46. The surface of the first interlayer insulating film 46 is flattened, for example. Further, a second interlayer insulating film 47 is formed on the first interlayer insulating film 46.

  A plug 71a formed on the first interlayer insulating film 46 is connected to the one impurity layer 23, and a landing pad portion 72 formed on the first interlayer insulating film 46 is connected to the plug 71a. ing. A sense line 15 is formed in the other impurity layer 24 of the selection transistor 2 via a plug 71s. The landing pad portion 72 and the sense line 15 can be formed in the same layer.

  Further, a second interlayer insulating film 47 made of, for example, a plurality of layers (for example, three layers) is formed on the first interlayer insulating film 46, and vias connected to the landing pad portion 72 are formed in the second interlayer insulating film 47. 73, landing pads 74, and vias 75 are formed. In the second interlayer insulating film 47, the word line 12 is disposed, and a landing pad portion 76 connected to the via 75 is formed. The landing pad portion 76 and the word line 12 can be formed in the same layer. The write word line 12 is made of a wiring material such as an aluminum copper alloy, copper, or copper alloy.

  A first insulating film 41 is formed on the second interlayer insulating film 47 so as to cover the word line 12 and the landing pad portion 76. The first insulating film 41 has a recess 50 that reaches the bottom of the landing pad portion 76, and a via 77 (conductor 51) connected to the landing pad portion 76 is formed in the recess 50. A magnetic memory element (for example, MTJ element) 3 is connected to the upper recess 52 (upper part of the recess 50) via the base electrode 30. The concave portion 52 needs to be formed in a rectangular, oval or elliptical shape in order to give the magnetic memory element 3 shape anisotropy. Accordingly, the concave portion 50 is similarly rectangular or oval. Alternatively, it is necessary to form an ellipse. Therefore, the planar shape of the via 77 (conductor 51) formed in the recess 50 is not a square or a circle but a rectangle, an oval or an ellipse. The base electrode 30 is a tantalum (Ta) film, for example, and has a thickness of 10 nm.

  The magnetic memory element 3 includes, for example, a first ferromagnetic layer 31 composed of an antiferromagnetic layer 32 and a magnetization fixed layer 33, a tunnel insulating layer 34, and a recording layer (magnetization free layer) 35 from the lower layer. Further, a top coat film (not shown) having conductivity is formed on the recording layer 35. Further, a cap film 37 having conductivity is formed.

  The antiferromagnetic material layer 32 is made of, for example, platinum manganese (Pt—Mn) alloy and has a thickness of 20 nm. The magnetization fixed layer 33 can have a multilayer structure (for example, ferromagnetic material layer / metal layer / ferromagnetic material layer) having synthetic anti-ferromagnetic coupling (SAF). Specifically, more specifically, as an example, it has a three-layer structure including a cobalt iron (Co—Fe) alloy layer, a ruthenium (Ru) layer, and a cobalt iron (Co—Fe) alloy layer from the lower layer. For example, the lowermost Co—Fe alloy layer is formed to a thickness of 2 nm, the intermediate ruthenium layer is formed to a thickness of 1 nm, and the uppermost cobalt iron (Co—Fe) alloy layer is formed to a thickness of 2 nm. Formed. The magnetization pinned layer 33 is pinned in the direction of magnetization by exchange coupling with the antiferromagnetic material layer 32.

  The tunnel insulating layer 34 is made of, for example, magnesium oxide and has a thickness of 0.5 nm to 1.5 nm.

  The recording layer 35 has its magnetization direction changed to be parallel or anti-parallel to the magnetization fixed layer 33 depending on the direction of current flow. For example, a cobalt iron boron (Co—Fe—B) layer is formed to a thickness of 3 nm.

  The magnetization fixed layer 33 and the recording layer 35 which is a magnetization free layer may be a single layer or a multilayer film having a synthetic anti-ferromagnet coupling (SAF). The cap layer 36 plays a role of preventing mutual diffusion of atoms constituting the recording layer 35 of the MTJ element and the atoms constituting the bit line 13 connecting the MTJ element, reducing contact resistance, and preventing oxidation of the recording layer 35. is there. Therefore, for example, it is formed of copper (Cu), tantalum (Ta), titanium (Ti), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or the like. Further, the base electrode 37 can also serve as the antiferromagnetic material layer 32.

  The top coat film (not shown) is made of, for example, tantalum (Ta) and has a thickness of 5 nm.

  A third insulating film 43 is formed on the first insulating film 41 so that the surface of the cap film 37 on the magnetic memory element 3 is exposed and the magnetic memory element 3 is embedded. The third insulating film 43 protects the magnetic memory element 3.

  On the third insulating film 43, a bit line 13 (corresponding to the wiring 62 in FIG. 3) connected to the magnetic memory element 3 through the cap film 37 is formed. The bit 13 is formed in a direction orthogonal to the word line 12.

  The configuration of the non-volatile magnetic storage device 1 described above is an example, and is not limited to the above configuration. As long as the magnetic memory element 3 is formed by the method of manufacturing a nonvolatile magnetic memory device of the present invention, any configuration of the nonvolatile magnetic memory device may be used.

It is manufacturing process sectional drawing which showed one Embodiment (Example) which concerns on the manufacturing method of the non-volatile magnetic memory device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (Example) which concerns on the manufacturing method of the non-volatile magnetic memory device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (Example) which concerns on the manufacturing method of the non-volatile magnetic memory device of this invention. It is a schematic structure sectional view showing the detailed structure of a magnetic memory element film. 1 is a schematic cross-sectional view showing an example of a nonvolatile magnetic memory device formed by a manufacturing method of the present invention. It is the layout top view which showed an example of the non-volatile magnetic memory device formed with the manufacturing method of this invention. It is the typical perspective view which showed the structure of the general MRAM. The right vertical axis represents the spin RAM (SpRAM) cell size (F ² ), the left vertical axis represents the write current, and the horizontal axis represents the short side size of the MTJ element. It is a typical principal part perspective view of the memory apparatus of the structure using the magnetization reversal by spin injection. It is a typical principal part sectional view of a memory device of composition using magnetization reversal by spin injection.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Nonvolatile magnetic memory device, 3 ... Magnetic memory element, 37 ... Cap film, 38 ... Depression, 41 ... 1st insulating film, 42 ... 2nd insulating film, 61 ... Magnetic memory element film

Claims (7)

A method of manufacturing a nonvolatile magnetic memory device including a magnetic memory element having a recording layer for storing information by changing a resistance value depending on a magnetization reversal state,
The manufacturing process of the magnetic memory element is as follows:
Forming a conductor whose surface is exposed in a first insulating film formed on the substrate;
Removing the top of the conductor and forming a recess in the first insulating film on the conductor;
Forming a magnetic memory element film and a cap film for forming the magnetic memory element on the first insulating film including the inside of the recess so as to have a depression on the upper surface of the cap film on the conductor; ,
Forming a second insulating film in the recess;
Removing the cap layer and the magnetic memory element film using the second insulating film as a mask, and forming the magnetic memory element on which the cap film is mounted with the magnetic memory element film left in the recess A method of manufacturing a nonvolatile magnetic memory device, comprising: The step of forming the conductor and the recess includes
Forming a conductive film for forming the conductor on the first insulating film so as to fill a recess formed in the first insulating film;
And removing the excess conductive film on the first insulating film by a polishing technique, and forming the conductor made of the conductive film in the recess,
2. The nonvolatile magnetic memory device according to claim 1, wherein in the polishing technique, the recess is formed in the first insulating film on the conductor by overpolishing the conductive film. 3. Production method. The step of forming the conductor and the recess includes
Forming a conductive film for forming the conductor on the first insulating film so as to fill a recess formed in the first insulating film;
Removing the excess conductive film on the first insulating film by a polishing technique to form the conductor made of the conductive film in the recess;
The method of manufacturing a nonvolatile magnetic memory device according to claim 1, further comprising: forming the recess in the first insulating film on the conductor by removing the conductor. The step of forming the second insulating film in the depression includes
Forming the second insulating film so as to embed the depression on the cap film;
The method of manufacturing a nonvolatile magnetic memory device according to claim 1, wherein the second insulating film is polished to leave the second insulating film only inside the recess. Removing the cap layer using the second insulating film as a mask;
2. The nonvolatile magnetic memory device according to claim 1, wherein the magnetic memory element film is removed using the cap layer as a mask, and a magnetic memory element is formed from the magnetic memory element film left in the recess. 3. Manufacturing method. The method for manufacturing a nonvolatile magnetic memory device according to claim 1, wherein the recess is formed in an elliptical shape or a rectangular shape. After forming the magnetic memory element,
Coating a third insulating film on the first insulating film so as to cover the magnetic memory element;
2. The method of manufacturing a nonvolatile magnetic memory device according to claim 1, further comprising: removing the third insulating film to planarize and exposing the cap film.

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