JP2003086772A - Magnetic memory device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable stable operation by forming flat a TMR element of a magnetic memory device. SOLUTION: The TMR element 18 is constituted having a tunneling barrier layer 16 interposed as a nonmagnetic layer between an upper layer 17 and a lower layer 15 with vertical magnetic anisotropy. The TMR element 18 is laminated on a 2nd plug 14 formed in a contact hole formed in a 3rd inter-layer insulating film 12. The top surface (laminated layer surface) of the 2nd plug 14 is larger in area than the lower magnetic layer of the TMR element 18 laminated on the surface.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic memory device which is a nonvolatile solid-state memory using a magnetoresistive effect element.

[0002]

2. Description of the Related Art In recent years, semiconductor memory devices, which are solid-state memories, have been widely used in information equipment and the like.
mic Random Access Memory), FeRAM (Ferroelect
ric Random Access Memory), EEPROM (Electric
There are various types such as ally Erasable Programmable Read-Only Memory). The characteristics of such a semiconductor memory device have merits and demerits, and it is difficult for these conventional semiconductor memory devices to meet all of the specifications required in current information equipment.

Therefore, in recent years, a magnetic memory device (MRAM: Magnetic Random Access) using a magnetoresistive effect element has been proposed.
Memory) is being researched and developed. Magnetic memory device
Since a magnetic film is used to store information, it has non-volatility that does not erase the information even when the power is turned off. This magnetic memory device has a recording time, a reading time, a recording density,
Regarding various characteristics such as rewritable count and power consumption,
It is expected to meet all the specifications required for various information devices.

The memory cell of this magnetic memory device is provided with a magnetoresistive effect film, and in particular, a magnetoresistive effect element (T
MR element) is provided. The TMR element has a basic structure in which two ferromagnetic layers and a thin non-magnetic layer sandwiched therebetween store information, and the magnetoresistance change rate (MR ratio) is
Is larger than other magnetoresistive effect elements, and the resistance value is several kΩ to several tens of kΩ, which can be set to an optimum value as a memory cell of a magnetic memory device, and thus is suitable as a storage element of a magnetic memory device. Is.

In this TMR element, when the magnetizations of the magnetic layers sandwiching the non-magnetic layer are parallel to each other (see FIG. 19A).
And the antiparallel case (see FIG. 19B) have different resistance values, and thus these two states having different resistance values can be stored as “0” and “1”, respectively. For example, by fixing the magnetization direction of one of the two magnetic layers,
The state of “0” or “1” can be stored by changing the other magnetization direction by the external magnetic field. This is a so-called information writing operation. A known method for changing the magnetization direction is to use a magnetic field generated by passing an electric current through a wiring arranged near the TMR element.

Then, the resistance value of the TMR element is obtained by detecting the voltage or the current, and "0" or "1" can be determined by the magnitude of the resistance value. This is a so-called information reading operation. More specifically, the absolute detection method in which the absolute value of the resistance determines “0” or “1”, and a weaker magnetic field is applied during writing to reverse the magnetization of only the magnetic layer having the lower coercive force. A differential detection method for reading the state of "0" or "1" is known.

As shown in FIG. 19, a TMR element using a so-called in-plane magnetized film magnetized in a direction horizontal to the surface of the magnetic layer, when the element size is reduced, a demagnetizing field (self-decaying field) generated inside the magnetic layer and The magnetization direction of the magnetic layer for recording and holding is not fixed in one direction due to curling of the magnetization at the end faces, and the magnetic layer becomes unstable, resulting in a problem that the MR ratio is lowered and information cannot be held. Therefore, in the in-plane magnetized TMR element, if the element size is made too small, it becomes impossible to retain information, and there is a limit to downsizing and high integration of the memory device.

To solve this problem, Japanese Patent Laid-Open No. 11-
Japanese Patent No. 213650 discloses a magnetoresistive effect element (see FIG. 20) using a so-called perpendicular magnetization film magnetized in a direction perpendicular to the surface of the magnetic layer. This perpendicularly magnetized magnetoresistive effect element has a small demagnetizing field even when the element size becomes small and can stably hold information. Therefore, the magnetoresistive effect element having a smaller size and higher integration than the in-plane magnetized magnetoresistive effect element. The device can be configured.

When a magnetic memory device is constructed by using the magnetoresistive effect element as described above, a structure in which a TMR element is laminated on a MOSFET (field effect transistor) is general. Specifically, the magnetic layer of the magnetoresistive effect element is provided with a MOSF via a conductive member such as a metal plug.
It is joined to the drain region of ET.

[0010]

In the conventional magnetic memory device, the non-magnetic layer of the magnetoresistive effect element cannot be formed flat, and the magnetization directions of the upper and lower magnetic layers are ideally parallel or anti-parallel. There may be a problem that it is not possible to form. In particular, when the TMR element is used as a memory element, if the tunnel barrier layer is not flat, the film thickness becomes uneven, leak current occurs, the MR ratio is lowered, and the magnetization directions of the upper and lower magnetic layers are changed. When it is not in the ideal parallel state or antiparallel state, the spin polarizability at the interface of the tunnel barrier layer decreases, and the MR ratio also decreases. That is, it becomes impossible to obtain a stable change in magnetoresistance of the TMR element.

Further, the unevenness on the upper surface of the conductive member is a problem which is particularly noticeable when the magnetoresistive effect element is provided right above the drain region.

A case where the above-mentioned problem occurs will be specifically described with reference to FIG. 21 based on the manufacturing process of the conventional magnetic memory device.

First, a transistor structure is formed in a semiconductor substrate (not shown), and a conductive member 101 connected to the drain region is provided. Then, this conductive member 10
The periphery of 1 is covered with the interlayer insulating film 102. In this state, the interlayer insulating film 102 and the conductive member (specifically, T
The upper surface of the metal plug 101 that contacts the MR element 103 is polished and smoothed. However, at this time,
As shown in (a), the conductive member 101 may be depressed in a concave shape. This is so much as to surely prevent an electrical short circuit with any conductive material due to insufficient polishing of the plug 101, and the plug 10
This is because 1 is apt to be excessively shaved, and it is difficult to polish the boundary portion between the interlayer insulating film 102 and the plug 101 with high precision. When the TMR element 103 is laminated in this state, the TMR element 103 is not flat as shown in FIG. 21B, but has an uneven shape along the shape of the plug 101. Then, the tunnel barrier layer (non-magnetic layer) 107 of the TMR element 103 is not flat, and it is difficult to make the magnetization directions of the upper and lower magnetic layers 105 and 106 ideally parallel or antiparallel. As I did,
It is not possible to obtain a stable change in magnetoresistance of the TMR element 103.

In this way, the TM is directly formed on the conductive member 101.
In the magnetic memory device of the type in which the R element 103 is stacked to form the ferromagnetic tunnel junction, the conductive member 1
It is important that the surface of 01 is flat. This is because the surface roughness (roughness) of the conductive member 101 influences the surface roughness of the magnetic layer 105 of the TMR element 103 formed thereon, and further the flatness of the tunnel barrier layer 107. Because.

Therefore, an object of the present invention is to provide a magnetic memory device in which the surface roughness of the magnetic layer of the TMR element laminated on the conductive member is small, the magnetic layer and the tunnel barrier layer are flat, and the MR ratio is high, and the magnetic memory device. It is to provide a manufacturing method.

[0016]

The first feature of the present invention is to:
A magnetoresistive effect element including a substrate on which a transistor structure is formed, a first magnetic layer and a second magnetic layer, and a non-magnetic layer located between the first magnetic layer and the second magnetic layer. ,
In a non-volatile magnetic memory device including a magnetoresistive element and a conductive member connecting an electrode of a transistor,
The magnetoresistive effect element is formed right above the electrode region of the transistor, and the laminated surface of the conductive member has a larger area than the second magnetic layer laminated on the laminated surface.
The second magnetic layer is laminated on the central portion of the laminated surface of the conductive member.

The surface to be laminated has a sufficient margin in the outer peripheral portion so that a portion where unevenness is likely to occur during surface processing does not come into contact with the second magnetic layer. The area is larger than that of the second magnetic layer. The outer periphery of the conductive member is covered with an insulating film, and a portion where unevenness is likely to occur during surface processing is near the boundary between the insulating film and the stacked surface.

The conductive member may have a substantially T-shaped vertical sectional shape.

The laminated surface of the conductive member may be formed separately from the main body of the conductive member, and may be formed on the main body after the formation of the main body.

A second feature of the present invention is that it is located between the substrate on which the transistor structure is formed, the first magnetic layer and the second magnetic layer, and between the first magnetic layer and the second magnetic layer. In a non-volatile magnetic memory device including a magnetoresistive effect element including a non-magnetic layer, and a conductive member connecting the magnetoresistive effect element and an electrode of the transistor, the magnetoresistive effect element is an electrode of the transistor. The conductive member is formed on the region, the outer periphery of the conductive member is covered with the first insulating film, the magnetoresistive element is covered with the second insulating film, and the laminated surface of the conductive member is the first It is located above the upper surface of the insulating film.

A third feature of the present invention is that it is located between the substrate on which the transistor structure is formed, the first magnetic layer and the second magnetic layer, and between the first magnetic layer and the second magnetic layer. A magnetoresistive effect element formed of a non-magnetic layer, and a conductive member connecting the magnetoresistive effect element and the electrode of the transistor.
In a non-volatile magnetic memory device, a magnetoresistive effect element is formed on an electrode region of a transistor, an outer periphery of a conductive member is covered with an insulating film, and a laminated surface of the conductive member constitutes an insulating film. The insulating film is polished by using a slurry that selectively scrapes the insulating material, and then is polished by using the slurry that selectively scrapes the conductive material forming the conductive member.

The laminated surface is laminated on the laminated surface.
The magnetic layer may have a larger area than the magnetic layer.

The main magnetization directions of the first and second magnetic layers are preferably perpendicular to the film surface. The magnetoresistive effect film is preferably a spin-dependent tunnel magnetoresistive effect film.

A fourth feature of the present invention is that the main magnetization direction is between the first magnetic layer and the second magnetic layer, which are perpendicular to the film surface, and between the first magnetic layer and the second magnetic layer. A non-volatile magnetic memory device comprising a non-magnetic layer positioned and including a magnetoresistive effect element laminated on a conductive member,
The laminated surface of the conductive member has a larger area than the second magnetic layer laminated on the laminated surface.

The fifth feature of the present invention is that it comprises a first magnetic layer and a second magnetic layer, and a non-magnetic layer located between the first magnetic layer and the second magnetic layer, Including a magnetoresistive effect element laminated on a conductive member provided in the film,
In the method of manufacturing a nonvolatile magnetic memory device, a step of removing a part of the insulating film to form a contact hole,
The step of filling the contact hole with the conductive material and forming the conductive material layer on the insulating film by depositing the conductive material, and removing at least a part of the conductive material layer on the surface of the insulating film. In addition, the step of forming a conductive member by leaving the conductive material filled in the contact hole, and the tunnel magnetoresistive effect element having an area smaller than that of the conductive material layer remaining on the surface of the insulating film are made conductive. And a step of forming on the conductive material layer.

A sixth feature of the present invention is that it comprises a first magnetic layer and a second magnetic layer, and a non-magnetic layer located between the first magnetic layer and the second magnetic layer, Including a magnetoresistive effect element laminated on a conductive member provided in the film,
In the method of manufacturing a nonvolatile magnetic memory device, a step of removing a part of the insulating film to form a contact hole,
A step of filling the contact hole with the conductive material by depositing the conductive material, and laminating the conductive material on the conductive material filled in the contact hole in an area larger than the opening area of the contact hole. By
The method includes a step of forming a conductive member and a step of forming, on the conductive material layer, a tunnel magnetoresistive effect element having an area smaller than that of the conductive material layer laminated on the surface of the insulating film.

The step of forming the magnetoresistive effect element on the conductive material layer includes the step of sequentially laminating each layer constituting the magnetoresistive effect element on the conductive material layer and the step of forming on the conductive material layer. And a step of partially removing the respective layers to form a tunnel magnetoresistive effect element having an area smaller than that of the conductive material layer remaining on the surface of the insulating film.

The seventh feature of the present invention is that it comprises a first magnetic layer and a second magnetic layer, and a non-magnetic layer located between the first magnetic layer and the second magnetic layer. In a method of manufacturing a nonvolatile magnetic memory device including a magnetoresistive effect element laminated on a conductive member provided therein, a step of removing a part of an insulating film to form a contact hole; A step of filling a contact hole with a conductive material by depositing a material to form a conductive member, and polishing the upper surface of the insulating film using a slurry that selectively scrapes the insulating material forming the insulating film It includes a step, a step of polishing the upper surface of the conductive member using a slurry that selectively scrapes the conductive material, and a step of forming a tunnel magnetoresistive effect element on the conductive member.

The step of forming the magnetoresistive effect element on the conductive member includes a step of sequentially laminating each layer constituting the magnetoresistive effect element on at least the conductive member, and a step of partially forming each layer formed on the conductive member. And a step of forming a magnetoresistive effect element by removing the second element.

The upper surface of the conductive member may project above the upper surface of the insulating film.

It is preferable that the upper surface of the conductive member has a larger area than that of the second magnetic layer laminated thereon.

This method is a method of forming a conductive member (plug) in two steps by adopting a CMP method for performing chemical and mechanical planarization (planarization). Can be achieved.

Specifically, for example, BPSG (Borophos
A contact hole is formed in a substrate made of a material such as silicon having an oxide layer such as phosilicate glass. A metal layer (conductive material) such as tungsten is formed on the substrate and tungsten is deposited in the contact hole. Fill. This becomes a conductive plug.

First, the first CMP (Chemical Mechanical) that selectively acts on the material (metal) of the plug is used.
l Polishing) process, from the wafer surface of the substrate,
The tungsten layer overlying the oxide surface is removed with little or no oxide removed. In the final stage of this process, metal residues including barriers such as titanium nitride and titanium that are entirely present on the wafer surface are completely removed, but at this time, tungsten having a height below the oxide surface is removed. Are also partially removed. Therefore, a recess is formed on the upper surface of the tungsten plug. Such groove-like depression of the plug, which is a common phenomenon in conventional plug formation methods, makes it difficult to connect with subsequently deposited metal or other materials.

Therefore, in the second CMP step that selectively acts on the oxide material (insulating material) on the wafer surface,
A portion of the insulating material is removed so that the height of the wafer surface is the same as or slightly lower than the tungsten plug. At this time, a slurry of oxide CMP prepared so that a desired amount of tungsten can be removed is used in order to shape the tungsten protruding on the wafer surface and eliminate the above-mentioned depression. That is, the amount of the etchant having selectivity with respect to the plug material may be increased.

In this method, a plug is formed of a conductive material (such as tungsten), and the height of the plug is the same as the wafer surface of an insulating layer such as oxide (BPSG or other material such as SiO ₂ ). , Or slightly protruding from this. By controlling the projecting plug so that the shape of the protruding plug is formed into a convex body, the surface to which the connection with the conductive material such as aluminum to be subsequently applied is further improved.

[0037]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

The configuration of the magnetic memory device of this embodiment shown in FIG. 1 will be described.

An element isolation region 2 is formed at a predetermined position on a semiconductor substrate 1 made of polysilicon. The element isolation region 2 of the present embodiment is an STI (Shallow Trench Isolator).
on). Then, the gate insulating film 3 is formed on the semiconductor substrate 1.
The gate electrode 4 is provided through the pair of gate electrodes 4 and
A source region 5, a drain region 6 are formed between the gate electrode 4 and the element isolation region 2 to form a transistor structure.

A first interlayer insulating film 7 made of SiO ₂ is formed on the semiconductor substrate 1 having the transistor structure as described above. Then, a first plug 9 made of tungsten is formed in a contact hole 8 penetrating the first interlayer insulating film 7 above the source region 5 and the drain region 6. A first metal wiring 10 made of a Ti / AlSiCu / Ti layer is connected to the first plug 9. I won't go into detail,
The first metal wiring 10 connected to the source region 5 via the first plug 9 is connected to the ground line, and the first metal wiring 10 connected to the drain region 6 via the first plug 9. The metal wiring 10 is connected to a peripheral circuit or an external circuit (not shown).

Second and third interlayer insulating films 1 made of SiO ₂
A second plug (conductive layer) made of tungsten is formed in a contact hole 13 provided above the drain region 6 and penetrating the second and third interlayer insulating films 11 and 12. (Member) 14 is formed. Further, on this second plug 14, GdFe that will be the lower magnetic layer (second magnetic layer) 15, AlO _x that will be the tunnel barrier layer (non-magnetic layer) 16, and upper magnetic layer (first magnetic layer). ) 17, the TMR element 18 made of TbFe is formed. In this embodiment, the TMR element 1 in which the upper surface (surface to be stacked) of the second plug 14 is stacked on this surface
8 has a larger area than the lower magnetic layer 15. by this,
The surface roughness of the lower magnetic layer 15 of the TMR element 18 is small, and the magnetic layers 15 and 17 and the tunnel barrier layer 16 are flat. This point will be described later. TMR element 1
The lower magnetic layer 15 of No. 8 is connected to the drain region 6 via the second plug 14, the first metal wiring 10, and the first plug 9.

Further, on the upper part of the second interlayer insulating film 11,
A second metal wiring 19 made of copper is formed. The second metal wirings 19 are arranged on both sides of the TMR element 18 in proximity to each other and are write lines for applying a magnetic field to the TMR element 18 to write information. Then, the second metal wiring 19 is covered with the third interlayer insulating film 12 having a thickness of 50 nm or less. The outer periphery of the TMR element 18 is covered with a fourth interlayer insulating film 20 made of SiO ₂ .

Further, a bit line 21 made of copper is formed and connected to the upper magnetic layer 17 of the TMR element 18.
The periphery of the bit line 21 is covered with a fifth interlayer insulating film 22 made of SiO _2, and the entire surface including the bit line 21 is made of Si.
It is covered with a passivation film (protective film) 23 made of N.

Although not shown, peripheral circuits are formed outside the memory cell shown in FIG. 1 described above.

In this magnetic memory device, when a current flows through the second metal wiring 19, a magnetic field is applied to the lower magnetic layer 15 of the TMR element 18. The magnetization direction of the lower magnetic layer 15 is determined by the magnetic field generated by the second metal wiring 19, and the states "0" and "" are determined depending on whether or not the magnetization direction of the upper magnetic layer 17 held in advance matches. 1 ”is determined. That is, the information is read. In addition, bit line 2
The magnetic field is also applied to the TMR element 18 by the current flowing through 1. This magnetic field is, so to speak, an assist magnetic field and assists the magnetization direction determination by the second metal wiring 19 to improve the efficiency.

Regarding the manufacturing method of this magnetic memory device,
It demonstrates with reference to FIGS. 1-11 along with each process, and the flowchart of FIG. In addition, in FIGS.
(A) is a plan view, and for the sake of simplification, each insulating film and the like are omitted and only the main part is shown. (B) is a sectional view.

As shown in FIG. 2, first, a groove is formed in a predetermined portion of the semiconductor substrate 1 made of polysilicon, and S is formed in the groove by the CVD (Chemical Vapor Deposition) method.
iO ₂ is deposited to form the element isolation region 2 (step S1). The element isolation region 2 of the present embodiment is STI (Sh
allow Trench Isolation). Then, the gate electrode 4 is provided on the semiconductor substrate 1 via the gate insulating film 3.
Then, a source region 5 is formed between the pair of gate electrodes 4 and a drain region 6 is formed between the gate electrode 4 and the element isolation region 2 by ion implantation. Thus, the transistor structure is formed on the semiconductor substrate 1 (step S2). In this embodiment, the source region 5 is shared and the gate electrode 4 and the drain region 6 are provided on both sides of the source region 5, respectively. Si is formed on the semiconductor substrate 1 having the transistor structure as described above by the CVD method.
A first interlayer insulating film 7 made of O ₂ is formed (step S3).

Next, as shown in FIG. 3, RIE (Reacti
The first interlayer insulating film 7 on the source region 5 and the drain region 6 is partially removed by a ve ion etching method to form a contact hole 8 (step S4).

Then, as shown in FIG. 4, the contact hole 8 is filled with tungsten by the CVD method to form the first plug 9 (step S5). In this state, C
The upper surfaces of the first interlayer insulating film 7 and the first plug 9 are smoothed by the MP (Chemical Mechanical Polishing) method (step S6).

Then, as shown in FIG. 5, a Ti / AlSiCu / Ti layer is formed by sputtering, and RI is formed.
Patterning is performed by the E method to form the first metal wiring 10 connected to the first plug 9 (step S
7). Although not described in detail, the first metal wiring 10 connected to the source region 5 via the first plug 9 is connected to the ground line. The first metal wiring 10 connected to the drain region 6 via the first plug 9 is connected to a peripheral circuit or an external circuit (not shown).

Then, as shown in FIG. 6, the second interlayer insulating film 11 made of SiO ₂ is formed by the CVD method (step S8), and is partially removed by the RIE method to form the wiring groove 24. It is formed (step S9).

Next, as shown in FIG. 7, the second metal wiring 19 made of copper is formed in the wiring groove 24 by plating (step S10), and the second interlayer insulating film 11 and the second interlayer insulating film 11 and the second wiring are formed by the CMP method. The upper surface of the metal wiring 19 is smoothed (step S11). This second metal wiring 19 is T
A write line for applying a magnetic field to the MR element 18 to write information.

Then, as shown in FIG. 8, a third interlayer insulating film 12 made of SiO ₂ is formed by the CVD method (step S12). At this time, the second metal wiring 19
Although the third interlayer insulating film 12 is also formed on the upper side, in order to efficiently apply a magnetic field to the magnetic layer of the TMR element 18 which will be arranged in a later step by the current passing through the second metal wiring 19,
The third interlayer insulating film 12 is formed on the second metal wiring 19.
Is 50 nm or less. Therefore, the third
The film thickness of the inter-layer insulating film 12 is extremely finely controlled.

Then, as shown in FIG. 9, the third interlayer insulating film 12 located above the first metal wiring 10 on the drain region 6 is partially removed with high positional accuracy by the RIE method. , The contact hole 13 is formed (step S13). Then, by CVD, the contact hole 13 is filled with tungsten to form a second plug (conductive member).
14 is formed (step S14). In this state, CM
The P method is used to smooth the upper surfaces of the third interlayer insulating film 12 and the second plug 14 (step S15).

Here, as shown in FIG. 10, the TMR element 18 is formed on the second plug 14 (step S1).
6). Specifically, by sputtering, GdFe to be the lower magnetic layer (second magnetic layer) 15, AlO _x to be the tunnel barrier layer (nonmagnetic layer) 16, and upper magnetic layer (first magnetic layer) 17 are formed. After sequentially stacking TbFe, the shape is adjusted by the RIE method. In this embodiment, the upper surface (surface to be stacked) of the second plug 14 is stacked on this surface.
The MR element 18 is formed to have a larger area than the lower magnetic layer 15. This point will be described later.

Then, as shown in FIG. 11, a fourth interlayer insulating film 20 made of SiO ₂ is formed by the CVD method so as to fill the TMR element 18 (step S1).
7). In this state, the fourth interlayer insulating film 20 is polished by the CMP method to expose the upper surface of the TMR element 18 (step S18).

As shown in FIG. 1, SiO is formed by the CVD method.
_A fifth interlayer insulating film 22 made of 2 is formed (step S19). Then, the fifth interlayer insulating film 2 is formed by the RIE method.
2, a groove is formed at a predetermined position, and a bit line 21 made of copper is formed in the groove by plating (step S2).
0). The upper surfaces of the fifth interlayer insulating film 22 and the bit line 21 are smoothed by the CMP method (step S21). Finally, a passivation film (protective film) 23 made of SiN is formed by the CVD method (step S22).

In this way, the memory cell of the present invention is completed. A peripheral circuit (not shown) is formed in parallel with the formation of the memory cell, and the magnetic memory device is completed.
The material of each member and the specific forming method are not limited to the examples described above, and various changes can be made.

In the magnetic memory device shown in FIG. 1 described above, as described above, the upper surface (surface to be stacked) of the second plug 14 is larger than the lower magnetic layer 15 of the TMR element 18 stacked on this surface. It has become an area. This point will be explained again.

A case where the above-mentioned problem occurs will be specifically described based on the manufacturing process of the conventional magnetic memory device.

In step S14, the second plug 14
After the formation, the second plug 14 and the third interlayer insulating film 12 are polished by the CMP method in step S15, the second plug 14 may be recessed in a concave shape to lower the central portion. This is an artificial factor that the second plug is excessively cut in order to prevent a short circuit, and it is difficult to polish with high precision at the boundary portion between the third interlayer insulating film 12 and the second plug 14 which are made of different materials. It is because of the technical factor that In this state, if the TMR element 18 having the same area as or larger than the upper surface (surface to be stacked) of the second plug is stacked, the TMR element 18 (103) becomes the second surface as in the case shown in FIG. Plug 14 (1
The shape becomes uneven according to the shape of the upper surface of (01) and is not flat. Then, the tunnel barrier layer 16 (107) of the TMR element 18 (103) is not flat. In this case, since it is difficult to set the magnetization directions of the upper and lower magnetic layers 15, 17 (105, 106) to an ideal parallel state or anti-parallel state, a stable magnetoresistance change of the TMR element 18 (103) can be achieved. Can't get

Therefore, in the present embodiment, the second plug 1
Even if unevenness occurs on the upper surface of 4, the flat part of the surface,
Specifically, the TMR element 18 is arranged in the center of the surface. That is, in the upper surface of the second plug 14, the TMR element 18 is configured to be in contact only with the central portion that is formed to be flat when viewed partially, avoiding the vicinity of the outer periphery that is the uneven portion. Of course, for that, the second
Than the upper surface of the plug 14 of the TMR element 18 (lower magnetic layer 1
It is essential that 5) has a small area. Second plug 1
Since there is a margin near the outer circumference of 4, the TMR element 18 (lower magnetic layer 15) has a smaller area than the upper surface of the second plug 14 by at least this margin.

With this structure, the surface roughness of the lower magnetic layer 15 of the TMR element 18 is small, and the magnetic layers 15 and 17 and the tunnel barrier layer 16 are flat. Then, the magnetization directions of the upper and lower magnetic layers 15 and 17 can be set to an ideal parallel state or an antiparallel state, and a stable magnetoresistance change of the TMR element 18 can be obtained.

A method of forming the TMR element 18 (lower magnetic layer 15) having a smaller area than the upper surface of the second plug 14 will be described in more detail with reference to FIGS.

First, in step S15, when the second plug 14 and the third interlayer insulating film 12 are polished by the CMP method, the second plug 14 is depressed in a concave shape and the central portion becomes low (FIG. 13 ( From the state of a) to FIG.
(It becomes the state of (b)). Therefore, as shown in FIG. 13C, the resist 25 is applied except for the central portion of the upper surface of the second plug 14, and in step S16, as shown in FIG.
As shown in (d), TM is formed in the opening on the resist 25.
The R element 18 is formed, and the resist 25 is removed as shown in FIG. As a result, the TMR element 18 having a small area is formed only at the position of the opening of the resist 25, that is, only at the flat central portion of the upper surface of the second plug 14.

Further, as shown in FIG. 14C, the layers 15, 16 and 17 constituting the TMR element 18 are widely laminated on the second plug 14 and the third interlayer insulating film 12, As shown in FIG. 14D, a resist 25 is placed at a position where the TMR element 18 is to be formed, and exposure, development,
By removing the resist, a small area TMR element 1
It can also be 8. Further, it is possible to use a method in which the layers 15, 16 and 17 are cut by the RIE method without using the resist 25 to form the TMR element 18 having a small area.

Next, regarding the second embodiment of the present invention,
This will be described with reference to FIGS. The same parts as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted. With respect to the manufacturing process, only the differences from the first embodiment will be described.

As shown in FIGS. 15D to 15E, in this embodiment, the second plug (conductive member) 26 is joined to the main body portion 26a and the large-area upper surface (surface to be laminated) 26b. It has a substantially T shape. As a result, even if the planar shapes of the contact hole 13 and the main body portion 26a have the same small area as in the conventional case, the upper surface 26b of the second plug 26 has the TMR element 1
8 (lower magnetic layer 15) can have a larger area.

As the manufacturing process, in step S15, the second plug 14 and the third interlayer insulating film 12 are polished by the CMP method, and the main body portion 26a of the second plug 26 is recessed in the central portion. Becomes low (Fig. 1
The state of FIG. 15 (b) is changed from the state of 5 (a)). Therefore, as shown in FIG.
A resist 25 having a wider opening is applied and tungsten is deposited. Then, as shown in FIG. 15D, the resist 25 is removed to form a large-area upper surface 26b. CMP the upper surface 26b of this large area
Method is used to flatten the concave portion. Then, in step S16, as shown in FIG. 15E, the TMR element 1 is formed on the upper surface 26b of the second plug 26.
8 is laminated.

As shown in FIG. 16C, before the resist 25 is laminated, the main body portion 26 of the second plug 26 is formed.
Widely deposited tungsten on a and the third interlayer insulating film 12, and then, as shown in FIG.
By arranging the resist 25 at a position where the upper surface 26b of the second plug 26 is to be formed, and exposing, developing and removing the resist, the upper surface 26b having a desired area is formed as shown in FIG. You can also do it. Also, the resist 2
5, each layer 15, 16, 17 is formed by the RIE method.
It is also possible to cut the above to form the upper surface 26b having a desired area. Then, as shown in FIG. 16F, the large area upper surface 26b is polished by the CMP method to flatten the concave portion. Then, in step S16, the TMR element 18 is stacked on the upper surface 26b of the second plug 26.

The TMR element 18 has the second plug 26 and the third interlayer insulating film 1 as in the case shown in FIG.
2 on each of the layers 15, 16, 1 that compose the TMR element 18.
After stacking 7 widely, each layer 15, 1 is formed by RIE method.
It is also possible to form 6 and 17 by cutting.

Next, a third embodiment of the present invention will be described with reference to FIG. The same parts as those in the first and second embodiments are designated by the same reference numerals and the description thereof will be omitted. With respect to the manufacturing process, only the differences from the first embodiment will be described.

In this embodiment, the upper surface of the second plug 27 and the TMR element 18 may have the same area. That is, when performing CMP in step S15, as shown in FIG. 17A, first, as shown in FIG. 17A, a slurry for selectively shaving the insulating material (SiO ₂ ) forming the third interlayer insulating film 12 is used to Then, the upper surface of the third interlayer insulating film 12 is polished. Next, as shown in FIG. 17B, the upper surface of the second plug 27 is mainly polished using a slurry that selectively scrapes tungsten. Then, the TMR element 18 is formed on the upper surface of the second plug 27. In this method, since the second plug 27 and the third interlayer insulating film 12 are not polished at the same time, unevenness does not occur near the boundary between them. Also,
If the upper surface of the second plug 27 is formed so as to project above the upper surface of the third interlayer insulating film 12, the flatness is impaired even if the second plug 27 is carefully polished to prevent a short circuit. I can't.

Next, a fourth embodiment of the present invention will be described with reference to FIG. The same parts as those in the first to third embodiments are designated by the same reference numerals and the description thereof will be omitted. With respect to the manufacturing process, only the differences from the first embodiment will be described.

This embodiment, like the third embodiment,
The second plug 28 and the third interlayer insulating film 12 are selectively polished using different slurries, but the order is reversed from that in the third embodiment. Ie, ie,
When performing CMP in step S15, first, as shown in FIG.
As shown in FIG. 8A, the upper surface of the second plug 28 is mainly polished using a slurry that selectively scrapes tungsten. Next, as shown in FIG. 18B, the upper surface of the third interlayer insulating film 12 is mainly formed by using a slurry that selectively scrapes the insulating material (SiO ₂ ) forming the third interlayer insulating film 12. To polish. However, at this time, the upper surface of the second plug 28 is also slightly polished to eliminate the unevenness and make the surface flat. And
The TMR element 18 is formed on the upper surface of the second plug 27. Even in this method, since the second plug 28 and the third interlayer insulating film 12 are not polished at the same time, unevenness is unlikely to occur near the boundary between them. Further, if the upper surface of the second plug 28 is formed so as to project above the upper surface of the third interlayer insulating film 12, even if the second plug 28 is carefully polished to prevent a short circuit, the flatness is reduced. Is not damaged.

Also in the third and fourth embodiments, each layer 1 constituting the TMR element 18 is formed on the second plugs 27 and 28 and the third interlayer insulating film 12, similarly to the case shown in FIG.
After the layers 5, 16 and 17 are widely stacked, the layers 15, 16 and 17 may be cut by the RIE method to form the TMR element 18.

In the above description of each embodiment,
The second plugs 14, 26, 27, 28 and the third interlayer insulating film 12 have been described above, but in reality, the third interlayer insulating film 12 and the second interlayer insulating film 11 and the like are combined. The above description should be interpreted as the relationship between the insulating film in the state and the second plugs 14, 26, 27, 28.

Although the TMR element has been described as an example, the present invention is not limited to this, and any element that exhibits a magnetoresistive effect may be used.

[0079]

According to the present invention, the surface roughness of the magnetic layer of the TMR element laminated on the conductive member can be reduced to flatten the magnetic layer and the tunnel barrier layer. As a result, a magnetic memory device having a high MR ratio and capable of stable operation can be obtained.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of essential parts of a magnetic memory device according to a first embodiment of the present invention.

FIG. 2 is a main-portion cross-sectional view showing the manufacturing process of the magnetic memory device of the first embodiment;

FIG. 3 is a main-portion cross-sectional view showing the manufacturing process of the magnetic memory device of the first embodiment;

FIG. 4 is a main-portion cross-sectional view showing the manufacturing process of the magnetic memory device in the first embodiment;

FIG. 5 is a main-portion cross-sectional view showing the manufacturing process of the magnetic memory device in the first embodiment;

FIG. 6 is a main-portion cross-sectional view showing the manufacturing process of the magnetic memory device in the first embodiment;

FIG. 7 is a main-portion cross-sectional view showing the manufacturing process of the magnetic memory device in the first embodiment;

FIG. 8 is a main-portion cross-sectional view showing the manufacturing process of the magnetic memory device in the first embodiment;

FIG. 9 is a main-portion cross-sectional view showing the manufacturing process of the magnetic memory device in the first embodiment;

FIG. 10 is a main-portion cross-sectional view showing the manufacturing process of the magnetic memory device in the first embodiment;

FIG. 11 is a main-portion cross-sectional view showing the manufacturing process of the magnetic memory device in the first embodiment;

FIG. 12 is a flowchart showing manufacturing steps of the magnetic memory device of the first embodiment.

FIG. 13 is an enlarged cross-sectional view showing the manufacturing process of the magnetic memory device of the first embodiment.

FIG. 14 is an enlarged cross-sectional view showing a modified example of the manufacturing process of the magnetic memory device of the first embodiment.

FIG. 15 is an enlarged cross-sectional view showing the manufacturing process of the magnetic memory device according to the second embodiment of the present invention.

FIG. 16 is an enlarged cross-sectional view showing a modified example of the manufacturing process of the magnetic memory device of the second embodiment.

FIG. 17 is an enlarged cross-sectional view showing the manufacturing process of the magnetic memory device according to the third embodiment of the present invention.

FIG. 18 is an enlarged cross-sectional view showing the manufacturing process of the magnetic memory device according to the fourth embodiment of the present invention.

FIG. 19 is a schematic view of a TMR element having in-plane magnetization.

FIG. 20 is a schematic diagram of a vertically magnetized TMR element.

FIG. 21 is an enlarged cross-sectional view of a conventional magnetic memory device.

[Explanation of symbols]

1 Semiconductor substrate 2 element isolation region (STI) 3 Gate insulation film 4 gate electrode 5 Source area 6 drain region 7 First interlayer insulating film 8 contact holes 9 First plug 10 First metal wiring 11 Second interlayer insulating film 12 Third interlayer insulating film (insulating film) 13 contact holes 14 Second plug (conductive member) 15 Lower magnetic layer (second magnetic layer) 16 Tunnel barrier layer (nonmagnetic layer) 17 Upper magnetic layer (first magnetic layer) 18 TMR element (tunnel magnetoresistive element) 19 Second metal wiring 20 Fourth interlayer insulating film 21 bit line 22 Fifth interlayer insulating film 23 Passivation film 24 wiring groove 25 resist 26 Second plug (conductive member) 26a Main body of the second plug 26b Upper surface of second plug (layered surface) 27, 28 Second plug (conductive member)

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F033 JJ09 JJ18 JJ19 KK01 KK09                       KK18 MM08 NN34 QQ08 QQ09                       QQ10 QQ13 QQ37 QQ48 QQ58                       RR04 RR06 SS11 VV05 VV16                       XX01                 5F083 FZ10 GA09 GA30 JA36 JA37                       JA39 JA56 MA06 MA19 NA01                       PR03 PR21 PR22 PR23 PR40

Claims (19)

[Claims] 1. A substrate on which a transistor structure is formed, a first magnetic layer and a second magnetic layer, and a non-magnetic layer located between the first magnetic layer and the second magnetic layer. A non-volatile magnetic memory device comprising: a magnetoresistive effect element, and a conductive member connecting the magnetoresistive effect element and an electrode of the transistor, wherein the magnetoresistive effect element is formed immediately above an electrode region of the transistor. The magnetic memory device is characterized in that the surface to be laminated of the conductive member has a larger area than the second magnetic layer laminated on the surface to be laminated. 2. The magnetic memory device according to claim 1, wherein the second magnetic layer is stacked on a central portion of the stacked surface of the conductive member. 3. The laminated surface has a sufficient margin in an outer peripheral portion so that a portion where unevenness is likely to occur during surface processing does not come into contact with the second magnetic layer,
The magnetic memory device according to claim 1, wherein the area is larger than that of the second magnetic layer by at least the margin. 4. The outer periphery of the conductive member is covered with an insulating film, and a portion where unevenness is likely to occur during the surface processing is near a boundary portion between the insulating film and the stacked surface. Item 5. The magnetic memory device according to item 3. 5. The magnetic memory device according to claim 1, wherein the conductive member has a substantially T-shaped vertical cross-sectional shape. 6. The laminated surface of the conductive member is formed separately from the main body of the conductive member, and is formed on the main body after the main body is formed. The magnetic memory device according to claim 1. 7. A substrate on which a transistor structure is formed, a first magnetic layer and a second magnetic layer, and a nonmagnetic layer located between the first magnetic layer and the second magnetic layer. A non-volatile magnetic memory device comprising: a magnetoresistive effect element, and a conductive member connecting the magnetoresistive effect element and an electrode of the transistor, wherein the magnetoresistive effect element is formed on an electrode region of the transistor. The outer periphery of the conductive member is covered with a first insulating film, the magnetoresistive effect element is covered with a second insulating film, and the surface to be stacked of the conductive member is the first insulating film. A magnetic memory device characterized in that the magnetic memory device projects above an upper surface of an insulating film. 8. A substrate on which a transistor structure is formed, a first magnetic layer and a second magnetic layer, and a non-magnetic layer located between the first magnetic layer and the second magnetic layer. A non-volatile magnetic memory device comprising: a magnetoresistive effect element, and a conductive member connecting the magnetoresistive effect element and an electrode of the transistor, wherein the magnetoresistive effect element is formed on an electrode region of the transistor. The outer periphery of the conductive member is covered with an insulating film, and the stacked surface of the conductive member is polished by using a slurry that selectively scrapes the insulating material forming the insulating film. The magnetic memory device is characterized by being polished with a slurry that selectively scrapes the conductive material forming the conductive member. 9. The magnetic memory device according to claim 7, wherein the laminated surface has a larger area than the second magnetic layer laminated on the laminated surface. 10. The magnetic memory device according to claim 1, wherein a main magnetization direction of the first and second magnetic layers is a direction perpendicular to a film surface. 11. The magnetic memory device according to claim 1, wherein the magnetoresistive effect film is a spin-dependent tunnel magnetoresistive effect film. 12. A first magnetic layer and a second magnetic layer whose main magnetization direction is perpendicular to the film surface, and a non-magnetic layer located between the first magnetic layer and the second magnetic layer. Consists of
A non-volatile magnetic memory device including a magnetoresistive effect element laminated on a conductive member, wherein a surface to be laminated of the conductive member is formed from the second magnetic layer laminated on the surface to be laminated. A magnetic memory device having a large area. 13. A first magnetic layer and a second magnetic layer,
A non-volatile nonvolatile memory including a magnetoresistive effect element that is composed of a non-magnetic layer located between the first magnetic layer and the second magnetic layer and is laminated on a conductive member provided in an insulating film. In a method of manufacturing a magnetic memory device, a step of removing a part of the insulating film to form a contact hole, and depositing a conductive material to fill the contact hole with the conductive material and Forming the conductive material layer on the film, removing at least a part of the conductive material layer on the surface of the insulating film, and leaving the conductive material filled in the contact hole The step of forming the conductive member, and the step of forming the tunnel magnetoresistive effect element having a smaller area than the conductive material layer remaining on the surface of the insulating film on the conductive material layer. A method of manufacturing a magnetic memory device, comprising: 14. A first magnetic layer and a second magnetic layer,
A non-volatile nonvolatile memory including a magnetoresistive effect element that is composed of a non-magnetic layer located between the first magnetic layer and the second magnetic layer and is laminated on a conductive member provided in an insulating film. In the method for manufacturing a magnetic memory device, a step of removing a part of the insulating film to form a contact hole; a step of depositing a conductive material to fill the contact hole with the conductive material; A step of forming the conductive member on the conductive material with which the contact hole is filled with a conductive material having an area larger than the opening area of the contact hole; and stacking on the surface of the insulating film. Forming the tunnel magnetoresistive effect element having an area smaller than that of the conductive material layer formed on the conductive material layer. . 15. The step of forming the magnetoresistive effect element on the conductive material layer, the step of sequentially laminating each layer forming the magnetoresistive effect element on at least the conductive material layer, and the conductivity. Partially removing each of the layers formed on the conductive material layer to form the tunnel magnetoresistive effect element having a smaller area than the conductive material layer remaining on the surface of the insulating film. , Claim 13 or 14
A method of manufacturing a magnetic memory device according to claim 1. 16. A first magnetic layer and a second magnetic layer,
A non-volatile magnetic element including a magnetoresistive element, which is composed of a non-magnetic layer located between the first magnetic layer and the second magnetic layer and is laminated on a conductive member provided in an insulating film. In the method for manufacturing a memory device, a step of removing a part of the insulating film to form a contact hole; and depositing a conductive material to fill the contact hole with the conductive material, A step of forming a member, a step of polishing the upper surface of the insulating film by using a slurry that selectively scrapes the insulating material that constitutes the insulating film, and a conductive step that uses a slurry that selectively scrapes the conductive material. A method of manufacturing a magnetic memory device, comprising: a step of polishing an upper surface of a member; and a step of forming the tunnel magnetoresistive effect element on the conductive member. 17. The step of forming the magnetoresistive effect element on the conductive member, the step of sequentially laminating each layer constituting the magnetoresistive effect element on at least the conductive member, and the step of forming on the conductive member. 17. The method for manufacturing a magnetic memory device according to claim 16, further comprising the step of forming the magnetoresistive effect element by partially removing each of the formed layers. 18. The method of manufacturing a magnetic memory device according to claim 16, wherein an upper surface of the conductive member projects above an upper surface of the insulating film. 19. The upper surface of the conductive member has a larger area than that of the second magnetic layer stacked thereon.
The method for manufacturing a magnetic memory device according to any one of 6 to 18.