JP2003086774A - Magnetic memory device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of a magnetic memory device while suppressing its power consumption low. SOLUTION: After a 4th inter-layer insulating film 20 is formed covering a TMR element 18, the 4th inter-layer insulating film 20 is polished by using slurry which is slow in polishing speed for the metal, such as Pt, Au, and W, constituting an upper magnetic layer 17 of the TMR element 18 and fast in polishing speed for the 4th inter-layer insulating film 20. The polishing is stopped by the TMR element 18 as a stop layer and the TMR element 18 is exposed through self-alignment. Then a bit line 21 is laminated and formed on the 4th inter-layer insulating film 20 and TMR element 18. Consequently, an upper magnetic layer 17 of the TMR element 18 and the bit line 21 are brought into direct contact with each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic memory device which is a non-volatile solid-state memory using a magnetoresistive effect element and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, semiconductor memory devices, which are solid-state memories, have been widely used in information equipment and the like.
mic Random Access Memory), FeRAM (Ferroelect
ric Random Access Memory), EEPROM (Electric
There are various types such as ally Erasable Programmable Read-Only Memory). The characteristics of such a semiconductor memory device have merits and demerits, and it is difficult for these conventional semiconductor memory devices to meet all of the specifications required in current information equipment.

Therefore, in recent years, a magnetic memory device (MRAM: Magnetic Random Access) using a magnetoresistive effect element has been proposed.
Memory) is being researched and developed. Magnetic memory device
Since a magnetic film is used to store information, it has non-volatility that does not erase the information even when the power is turned off. This magnetic memory device has a recording time, a reading time, a recording density,
Regarding various characteristics such as rewritable count and power consumption,
It is expected to meet all the specifications required for various information devices.

A magnetoresistive effect element is provided in the memory cell of this magnetic memory device. A spin-dependent tunnel magnetoresistive effect element (TMR element) is suitable as such a magnetoresistive effect element. The TMR element has a basic structure in which two ferromagnetic layers and a thin non-magnetic layer sandwiched between the two ferromagnetic layers store information.
Ratio) is larger than that of other magnetoresistive effect elements, and the resistance value is several kΩ to several tens kΩ, which can be set to an optimum value as a memory cell of the magnetic memory device. Is commonly used as.

In this TMR element, when the magnetizations of the magnetic layers sandwiching the non-magnetic layer are parallel to each other (see FIG. 14A).
And the anti-parallel state (see FIG. 14B) have different resistance values, the two states having different resistance values can be stored as “0” and “1”, respectively. For example, by fixing the magnetization direction of one of the two magnetic layers,
The state of “0” or “1” can be stored by changing the other magnetization direction by the external magnetic field. This is a so-called information writing operation. A known method for changing the magnetization direction is to use a magnetic field generated by passing an electric current through a wiring arranged near the TMR element.

Then, the resistance value of the TMR element is obtained by detecting the voltage or the current, and "0" or "1" can be determined depending on the magnitude of the resistance value. This is a so-called information reading operation. More specifically, the absolute detection method that determines whether the absolute value of resistance is “0” or “1”, and a weaker magnetic field is applied during writing to reverse the magnetization of only the magnetic layer with the lower coercive force. A differential detection method for reading the state of "0" or "1" is known.

As shown in FIG. 14, the TMR element using a so-called in-plane magnetized film magnetized in the direction horizontal to the surface of the magnetic layer has a demagnetizing field (self-decaying field) generated inside the magnetic layer when the element size is reduced. The magnetization direction of the magnetic layer for recording and holding is not fixed in one direction due to curling of the magnetization at the end faces, and the magnetic layer becomes unstable, resulting in a problem that the MR ratio is lowered and information cannot be held. Therefore, in the in-plane magnetized TMR element, if the element size is made too small, it becomes impossible to retain information, and there is a limit to downsizing and high integration of the memory device.

To solve this problem, Japanese Patent Laid-Open No. 11-
No. 213650 discloses a TMR element using a so-called perpendicular magnetization film magnetized in a direction perpendicular to the surface of the magnetic layer (see FIG. 15).
) Is disclosed. The perpendicularly magnetized TMR element has a small demagnetizing field even when the element size is small and can stably hold information. Therefore, a smaller and highly integrated magnetic memory device can be configured than the in-plane magnetized TMR element. .

[0009]

[Problems to be Solved by the Invention] TMR as described above
When a magnetic memory device is constructed using elements, MOSF
A structure in which a TMR element is stacked on an ET (field effect transistor) is general. And the TMR element is a MOS
In addition to the electric system connected to the FET, electric wiring is provided above and below the TMR element, and the magnetic state generated by the current flowing through the electric wiring determines the magnetized state of the TMR element to store information.

As an example of the structure, as shown in FIG. 16, a metal wiring 102, which is a write line, is provided diagonally below both sides of the TMR element 101, and a metal wiring 102 is provided directly above the TMR element 101. The orthogonal bit lines 103 are provided. Both the metal wiring 102 and the bit line 103 are connected to an external circuit (not shown). TM
The magnetization direction of the magnetic layer 105 of the TMR element 101 can be changed by the magnetic field generated by the current flowing through the metal wirings 102 on both sides of the R element 101. further,
The magnetic field generated by the current flowing through the bit line 103 assists the determination of the magnetization direction of the magnetic layer 105 of the TMR element 101 by the metal wiring 102. Bit line 103
In other words, it generates an assist magnetic field.

For example, in the initial state, the TMR element 1
01, the magnetization directions of the upper magnetic layer 104 and the lower magnetic layer 105 sandwiching the non-magnetic layer 106 are from the bottom to the top, and the magnetic coercive force of the upper magnetic layer 104 is assumed to be strong. Metal wiring 1
If no current is applied to 02, the parallel magnetization directions of both magnetic layers 104 and 105 of the TMR element 101 are maintained. Therefore, the resistance value of the TMR element 101 does not change. But,
When a current flowing from the back to the front of the drawing in the right metal wiring 102 of the TMR element 101 and a current flowing from the front to the back of the drawing in the left metal wiring 102 are passed, the lower magnetic layer 105 is particularly formed.
Causes a magnetic field from top to bottom to cancel the original magnetization direction, and the magnetization direction of the lower magnetic layer 105 changes. Since the upper magnetic layer 104 has a strong magnetization holding force, there is no change in the magnetization direction from the bottom to the top. This allows TMR
The magnetization directions of both magnetic layers 104 and 105 of the element 101 are antiparallel. Therefore, the resistance value of the TMR element 101 becomes small. By detecting this change in resistance,
Records can be read. The direction of the current flowing through the bit line 103 does not directly affect the magnetization direction of the magnetic layers 104 and 105, but the magnetic field generated by this current reinforces the magnetic field generated by the current flowing through the metal wiring 102, A magnetic field strong enough to change the magnetization of the magnetic layer 105 can be obtained.

Due to this structure, the metal wiring 1
02 and the bit line 103, it is possible to apply a magnetic field as strong as possible to the magnetic layer 105 of the TMR element 101 without applying a very large current.
01 is important for improving reliability as a memory and suppressing power consumption. And for that, bit line 1
02 and the TMR element 101 are desired to be as close as possible.

Therefore, an object of the present invention is to provide a magnetic memory device and a method of manufacturing the same in which a TMR element and a bit line for applying a magnetic field to the TMR element can be brought as close as possible.

[0014]

A feature of the present invention is that a first magnetic layer and a second magnetic layer which are magnetized mainly in a direction perpendicular to a film surface are provided, and between the first magnetic layer and the second magnetic layer. In a non-volatile magnetic memory device having a magnetoresistive effect element including a non-magnetic layer located in a non-magnetic layer and a bit line above which the current for applying a magnetic field flows, a magnetoresistive element is provided. Is in direct contact with the upper surface of the bit line.

The upper surface of the magnetoresistive element in contact with the bit line is preferably made of any one of Pt, Au and W.

A write line is further provided below the magnetoresistive element, through which a current for applying a magnetic field is passed.

The outer periphery of the magnetoresistive element is covered with an insulating film, and the upper surface of the polished insulating film and the upper surface of the magnetoresistive element are located at the same height, and are placed on the insulating film and the magnetoresistive element. , Bit lines are preferably formed.

The magnetoresistive effect element may be a spin-dependent tunnel magnetoresistive effect element.

Another feature of the present invention is located between the first magnetic layer and the second magnetic layer, which are magnetized mainly in the direction perpendicular to the film surface, and between the first magnetic layer and the second magnetic layer. In a method of manufacturing a non-volatile magnetic memory device having a magnetoresistive effect element including a non-magnetic layer, and a bit line located above the magnetoresistive element and through which a current for applying a magnetic field is passed,
The step of forming the magnetoresistive element, the step of depositing an insulating material to cover the magnetoresistive element to form an insulating film, and the step of forming the insulating film covering the magnetoresistive element until the upper surface of the magnetoresistive element is exposed. The process includes a step of polishing and a step of forming the bit line on the insulating film and the magnetoresistive element.

In the polishing step, it is preferable to expose the upper surface of the magnetoresistive element in a self-aligned manner.

In the polishing step, it is preferable to perform polishing with the upper surface of the magnetoresistive element as a stop layer so that the upper surface of the insulating film and the upper surface of the magnetoresistive element have the same height.

In the polishing step, the insulating film may be polished using a slurry in which the grinding speed of the upper surface of the magnetoresistive element is lower than the grinding speed of the insulating film.

The first and second magnetic layers of the magnetoresistive element may have perpendicular magnetic anisotropy.

The upper surface of the magnetoresistive element in contact with the bit line is preferably made of any one of Pt, Au and W.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

The configuration of the magnetic memory device of this embodiment shown in FIG. 1 will be described.

An element isolation region 2 is formed at a predetermined position on a semiconductor substrate 1 made of a single crystal silicon substrate or an SOI substrate. Element isolation region 2 used in this embodiment
For STI (Shallow Trench Isolation), LOCO
It is made of a dielectric material formed by a method such as S. A gate electrode 4 made of polycrystalline silicon or the like doped through a gate insulating film 3 such as silicon oxide is provided on the semiconductor substrate 1, and a source region 5 and a gate electrode 4 are provided between the pair of gate electrodes 4. The drain region 6 is formed between the element isolation region 2 and the element isolation region 2 to form a transistor structure. Here, LDD (Lightly Doped Drain) having a low impurity concentration doped region on the gate electrode 4 side
Although a MOS transistor having a structure is given as an example, the present invention is not limited to this.

A first interlayer insulating film 7 made of SiO ₂ , BPSG or the like is formed on the semiconductor substrate 1 having the transistor structure as described above. Then, the first interlayer insulating film 7 is formed above the source region 5 and the drain region 6.
A first plug 9 made of tungsten or the like is formed in a contact hole 8 penetrating therethrough.
The first plug 9 is connected to a first metal wiring 10 made of a laminated body of Ti / AlSiCu / Ti or the like. Although not described in detail, the first metal wiring 10 connected to the source region 5 via the first plug 9 is connected to the ground line and connected to the drain region 6 via the first plug 9. The formed first metal wiring 10 is connected to a peripheral circuit or an external circuit (not shown).

Second interlayer insulating film 11 made of SiO ₂ or the like
And a third interlayer insulating film (insulating thin film) 12 made of alumina or the like is further laminated, and is provided above the drain region 6 through the second and third interlayer insulating films 11 and 12. A second plug (conductive member) 14 made of tungsten or the like is formed in the contact hole 13 present.

Further, on this second plug 14, GdFe to be the lower magnetic layer (second magnetic layer) 15, AlO _x to be the tunnel barrier layer (non-magnetic layer) 16, and upper magnetic layer (first magnetic layer). Magnetic layer) 17 and TMR element 1 having TbFe
8 is formed. If necessary, Pt, Au, W
A protective metal layer made of a metal such as the above may be formed on the upper magnetic layer (first magnetic layer) 17. The lower magnetic layer 15 of the TMR element 18 includes the second plug 14, the first metal wiring 10,
It is connected to the drain region 6 via the first plug 9.

On the upper part of the second interlayer insulating film 11,
A second metal wiring 19 made of copper or the like is formed.
The second metal wirings 19 are arranged on both sides of the TMR element 18 in proximity to each other and are write lines for applying a magnetic field to the TMR element 18 to write information. And
On the second metal wiring 19, a third metal wiring 19 having a thickness of 200 nm or less is formed.
Is covered with the interlayer insulating film (insulating thin film) 12. TM
The outer periphery of the R element 18 is covered with a fourth interlayer insulating film 20 made of SiO ₂ or the like.

Fourth interlayer insulating film 2 which is polished and flattened
The upper surface of 0 and the upper surface of the upper magnetic layer 17 of the TMR element 18 are located at the same height.

Further, a bit line 21 made of copper or the like is formed on the fourth interlayer insulating film 20 and the TMR element 18,
It is directly connected to the upper magnetic layer 17 of the TMR element 18.
The periphery of the bit line 21 is covered with a fifth interlayer insulating film 22 made of SiO ₂ or the like, and the entire surface including the bit line 21 is S
It is covered with a passivation film (protective film) 23 made of iN.

Although not shown, peripheral circuits are formed outside the memory cell shown in FIG. 1 described above.

In this magnetic memory device, when a current flows through the second metal wiring 19, a magnetic field is applied to the lower magnetic layer 15 of the TMR element 18. The magnetization direction of the lower magnetic layer 15 is determined by the magnetic field generated by the second metal wiring 19, and the state "0" or "0" is determined depending on whether or not the magnetization direction of the upper magnetic layer 17 held in advance matches. 1 ”is determined. That is, the information is read. In addition, bit line 2
The magnetic field is also applied to the TMR element 18 by the current flowing through 1. This magnetic field is, so to speak, an assist magnetic field and assists the magnetization direction determination by the second metal wiring 19 to improve the efficiency.

As the first and second plugs used in the present invention, in addition to W, Al, Cu, or an alloy containing these as the main components can be used. If necessary, Ti, Ta, TiN, TaN, WN, TiSi, TaSi, TiSi may be formed on the side surface and the bottom surface of the contact hole before forming the plug.
It is also preferable to form at least one kind of conductor that is a barrier metal selected from N, TaSiN, TiW and the like. The material to be the plug or the barrier metal can be formed by a known method such as CVD or sputtering.

As the first metal wiring used in the present invention, in addition to AlSiCu, metals such as AlCu, AlTi, AlSiTi, AlNd and Cu can be used. If necessary, Ti, Ta, TiN, TaN, WN, TiSi, TaSi,
It is also preferable to form at least one type of conductor that is a barrier metal selected from TiSiN, TaSiN, TiW, and the like.

As the second metal wiring used in the present invention, the same metal wiring as the above-mentioned first metal wiring can be used, but Cu or Au is used because a relatively large current flows.
It is desirable to use a highly conductive material such as Also, Cu and
In order to prevent Au diffusion, Ti, Ta,
It is also preferable to form a conductor which is at least one kind of barrier metal selected from TiN, TaN, WN, TiSi, TaSi, TiSiN, TaSiN, TiW and the like. The material to be the metal wiring or the barrier metal can be formed by a known method such as CVD, sputtering or plating.

As the first and second interlayer insulating films, non-doped silicon oxide, silicon oxide doped with B or P, silicon nitride, silicon oxynitride, alumina, diamond-like carbon, fluorocarbon, F-doped silicon oxide. Inorganic insulation film such as, or polyimide,
At least one selected from organic insulating films such as polyaryl ether and BCB can be used. These materials can be formed by CVD, sputtering, coating method or the like.

The third interlayer insulating film used in the present invention is made of the same material as the above-mentioned first and second interlayer insulating films as long as the film thickness can be 200 nm or less. Although a film can be used, it is more preferable to use alumina. Alumina can be formed by a method such as sputtering.

Prior to forming the third interlayer insulating film formed on the second metal wiring, CMP is performed so that the upper surface of the second metal wiring and the upper surface of the second interlayer insulating film 11 are substantially aligned with each other. It is preferable to flatten the surface by such a method. As such a flattening method, after forming a pattern of the second metal wiring, depositing an insulator covering the space between the wiring patterns and the upper surface of the wiring pattern, and then performing CMP or the like on the unnecessary insulator on the upper portion. By polishing to remove the upper surface of the wiring pattern, or after forming a wiring groove in an insulator having a flat upper surface, depositing a metal so as to fill at least the groove, and removing unnecessary portions of the metal. Can be removed by etching or CMP. Among the latter, the method using CMP is a method known as the damascene method, and is more preferable as the method for forming the second metal wiring in the present invention.

Further, in the present invention, after forming the third interlayer insulating film (insulating thin film), holes are formed therein to form the first interlayer insulating film (insulating thin film).
Although the second plug is formed, it is preferable that the second plug is similarly formed by the damascene method. In this case, the lower surface of the TMR element becomes a smooth surface, so that the TMR element having good characteristics can be formed.

As the layer constituting the upper surface of the TMR element used in the present invention, a magnetic layer such as TbFe or Pt or A is used.
At least one protective metal layer made of a transition metal such as u or W and an alloy thereof can be used.

Regarding the method of manufacturing this magnetic memory device,
1 to 12 along each step and the flowchart of FIG. 13 will be described. In addition, in FIGS.
(A) is a plan view, and for the sake of simplification, each insulating film and the like are omitted and only the main part is shown. (B) is a sectional view.

As shown in FIG. 2, first, a groove is formed in a predetermined portion of the semiconductor substrate 1 made of single crystal silicon, and SiO ₂ is deposited in the groove by a CVD (Chemical Vapor Deposition) method to form an element. The isolation region 2 is formed (step S1). The element isolation region 2 of this embodiment is formed by STI.
(Shallow Trench Isolation). Then, the gate electrode 4 is provided on the semiconductor substrate 1 via the gate insulating film 3. And 1 by ion implantation
The source region 5 is formed between the pair of gate electrodes 4 and
A drain region 6 is formed between the element isolation region 2 and the element isolation region 2. Thus, the transistor structure is formed on the semiconductor substrate 1 (step S2). In this embodiment, the source region 5 is shared and the gate electrode 4 and the drain region 6 are provided on both sides of the source region 5, respectively. The first interlayer insulating film 7 made of SiO ₂ is formed by the CVD method on the semiconductor substrate 1 having the transistor structure as described above (step S3).

Next, as shown in FIG. 3, RIE (Reacti
The first interlayer insulating film 7 on the source region 5 and the drain region 6 is partially removed by a ve ion etching method to form a contact hole 8 (step S4).

Then, as shown in FIG. 4, the contact hole 8 is filled with tungsten by the CVD method to form the first plug 9 (step S5). In this state, C
The upper surfaces of the first interlayer insulating film 7 and the first plug 9 are smoothed by the MP (Chemical Mechanical Polishing) method (step S6).

Then, as shown in FIG. 5, a Ti / AlSiCu / Ti layer is formed by sputtering, and RI is formed.
Patterning is performed by the E method to form the first metal wiring 10 connected to the first plug 9 (step S
7). Although not described in detail, the first metal wiring 10 connected to the source region 5 via the first plug 9 is connected to the ground line. The first metal wiring 10 connected to the drain region 6 via the first plug 9 is connected to a peripheral circuit or an external circuit (not shown).

Then, as shown in FIG. 6, the second interlayer insulating film 11 made of SiO ₂ is formed by the CVD method (step S8), and is partially removed by the RIE method to form the wiring groove 24. It is formed (step S9).

Next, as shown in FIG. 7, the second metal wiring 19 made of copper is formed in the wiring groove 24 by plating (step S10), and the second interlayer insulating film 11 and the second interlayer insulating film 11 and the second wiring are formed by the CMP method. The upper surface of the metal wiring 19 is smoothed (step S11). This second metal wiring 19 is T
A write line for applying a magnetic field to the MR element 18 to write information.

Then, as shown in FIG. 8, a third interlayer insulating film 12 made of SiO ₂ is formed by the CVD method (step S12). At this time, the T to be arranged in the subsequent process
In order to efficiently apply a magnetic field to the magnetic layer of the MR element 18 by the current passing through the second metal wiring 19, the third interlayer insulating film 12 has a thickness of 20 on the second metal wiring 19.
It should be 0 nm or less. The film thickness of the third interlayer insulating film 12 is controlled extremely precisely.

Subsequently, as shown in FIG. 9, the third interlayer insulating film 12 located above the first metal wiring 10 on the drain region 6 is partially removed with high positional accuracy by the RIE method. , The contact hole 13 is formed (step S13). Then, by CVD, the contact hole 13 is filled with tungsten to form a second plug (conductive member).
14 is formed (step S14). In this state, CM
The P method is used to smooth the upper surfaces of the third interlayer insulating film 12 and the second plug 14 (step S15).

Here, as shown in FIG. 10, the TMR element 18 is formed on the second plug 14 (step S1).
6). Specifically, by sputtering, GdFe to be the lower magnetic layer (second magnetic layer) 15, AlO _x to be the tunnel barrier layer (nonmagnetic layer) 16, and upper magnetic layer (first magnetic layer) 17 are formed. After sequentially stacking metals such as Pt, Au, and W, the shape is adjusted by the RIE method.

Then, as shown in FIG. 11, a fourth interlayer insulating film 20 made of SiO ₂ is formed by the CVD method so as to fill the TMR element 18 (step S1).
7). Then, as shown in FIG. 12, by the CMP method,
The fourth interlayer insulating film 20 is polished to expose the upper surface of the TMR element 18 (step S18). Specifically, TMR
The metal (Pt, Au,
S, etc., which has a polishing rate of W, etc., forming the fourth interlayer insulating film 20.
The fourth interlayer insulating film 20 is polished using a slurry that is slower than the polishing rate of iO ₂ . At this time, the TMR element 18
The upper magnetic layer 17 serves as a polishing stop layer. That is, the fourth interlayer insulating film 20 is polished from above, and the polishing is stopped when the upper surface of the upper magnetic layer 17 of the TMR element 18 is exposed. That is, the TMR element 18
By exposing the upper surface of the upper magnetic layer 17 in a self-aligned manner, the polished upper surface of the fourth interlayer insulating film 20 and the upper surface of the upper magnetic layer 17 have the same height.

As shown in FIG. 1, SiO is formed by the CVD method.
_A fifth interlayer insulating film 22 made of 2 is formed (step S19). Then, the fifth interlayer insulating film 2 is formed by the RIE method.
2, a groove is formed at a predetermined position, and a bit line 21 made of copper is formed in the groove by plating (step S2).
0). As a result, the upper surface of the upper magnetic layer 17 of the TMR element 18 is brought into direct contact with the bit line 21.

The upper surfaces of the fifth interlayer insulating film 22 and the bit line 21 are smoothed by the CMP method (step S2).
1). Finally, a passivation film (protective film) 23 made of SiN is formed by the CVD method (step S2).
2).

In this way, the memory cell of the present invention is completed. A peripheral circuit (not shown) is formed in parallel with the formation of the memory cell, and the magnetic memory device is completed.
The material of each member and the specific forming method are not limited to the examples described above, and various changes can be made.

According to this embodiment, since the TMR element 18 and the bit line 21 are in direct contact with each other, the magnetic field can be efficiently applied to the TMR element 18 even if the current flowing through the bit line 21 is low. Therefore, it is possible to improve the reliability of determining the magnetization direction of the second magnetic layer 15 of the TMR element 18 while suppressing the power consumption low. by this,
The reliability of the TMR element 18 as a memory is improved.

Conventionally, when an insulating film is interposed between the TMR element 18 and the bit line 21, the efficiency of magnetic field application is poor, and a contact hole is provided in the insulating film, and the contact hole is filled with a conductive material. There is a configuration in which a plug is formed and the TMR element 18 and the bit line 21 are connected via this plug. However, in the case of the present invention, the TMR element 1
Since 8 and the bit line 21 are in direct contact with each other, the step of forming a contact hole or a plug is not necessary, and the manufacturing process can be simplified. Further, when the fourth interlayer insulating film 20 is polished, the upper surface of the TMR element 18 is used as a stop layer to expose the TMR element 18 in a self-aligned manner, so that the operator must perform strict control to finish the polishing. No need to do it, work is easy. Moreover, the upper magnetic layer 17 and the fourth
Since the heights of the upper surfaces of the inter-layer insulating films 20 are easily and accurately matched, the bit lines 21 can be easily and firmly laminated with high accuracy. In this case, if the upper magnetic layer of the TMR element 18 is made of a metal such as Pt, Au, W, etc., it reliably acts as a stop layer, and the polishing step is performed at a polishing rate for the metal such as Pt, Au, W, etc. It is performed using a slurry that is slow and has a high polishing rate for SiO ₂ forming the fourth interlayer insulating film 20. A well-known slurry for polishing tungsten or the like can be used.

(Other Embodiments) Another manufacturing method for manufacturing the magnetic memory device of the present invention will be described.

First, a groove is formed in a predetermined portion of the semiconductor substrate 1 made of single crystal silicon, and a CVD (Chem
Silicon oxide is deposited by the ical vapor deposition method and the surface thereof is polished to form an element isolation region 2 having an upper surface at the same level as an active area (area where a transistor is formed) of single crystal silicon.

Then, after the gate insulating film 3 made of silicon oxide is formed on the semiconductor substrate 1 by thermal oxidation, the gate electrode 4 made of polycrystalline silicon is formed. ion·
By implantation, a gate electrode pattern of polycrystalline silicon is used as a mask to form a doped region having a low impurity concentration. After forming an oxide film on the surface of polycrystalline silicon by thermal oxidation, etching back is performed to leave a sidewall oxide film on the sidewall of the gate electrode. Ion impulitation is performed again to form the source region 5 and the drain region 6 having a high impurity concentration. Further, if necessary, a refractory metal such as Pt, Co, or Ni is deposited on the upper surface of the source region, the drain region, and the gate electrode, heat treated to silicify, and then the refractory metal not silicified is removed by etching. By doing so, a silicide layer may be formed.

Thus, the semiconductor substrate 1 is provided with the LDD structure MO.
An S-transistor structure is produced.

On the semiconductor substrate 1 having the transistor structure as described above, SiO ₂ or BPS is formed by the CVD method or the like.
A first interlayer insulating film 7 made of G is formed, and the upper surface thereof is flattened by reflow or CMP if necessary.

Next, the first interlayer insulating film 7 on the source region 5 and the drain region 6 is partially removed by RIE (Reactive Ion Etching) method or the like to form a contact hole 8.

Then, the first plug 9 is formed. As a method of forming the plug, Ti, TiN, T is formed in the contact hole and on the upper surface of the first interlayer insulating film 7 as necessary.
After forming a barrier metal such as a and TaN, a metal such as tungsten is deposited on the barrier metal by a CVD method, and the metal such as tungsten outside the contact hole is removed by etching or polishing, or a method of forming tungsten in the contact hole. A method of depositing a metal such as by selective CVD and polishing the upper surface of the metal as required.

Subsequently, by sputtering, Ti / A
A film in which a metal layer is sandwiched between barrier metals such as a 1Cu / Ti laminated body is formed and patterned by the RIE method to form a first metal wiring 10 connected to the first plug 9. By the way, for the first metal wiring, an insulating film is first formed, and then a groove corresponding to the wiring pattern is formed,
It is also possible to embed a metal in the groove and remove the unnecessary metal by CMP (single damascene method).

After patterning by the RIE method to form the first metal wiring 10, a second interlayer insulating film made of silicon oxide or the like is formed by the CVD method and the coating method, and the upper surface is flattened by etch back or CMP. Turn into. After that, when the second metal wiring is formed by the dual damascene method, a plurality of types of insulating films are laminated so that an etch stop layer such as silicon nitride exists below the second metal wiring. It is preferable to form the interlayer insulating film.

The second interlayer insulating film is partially removed by the RIE method to form the wiring groove 24.

Next, at least Ti and T are formed in the wiring groove 24.
After forming a barrier metal such as iN, a thin film of Cu or Au is formed on the barrier metal by CVD. And
Cu on the Cu or Au thin film by CVD by plating
Alternatively, Au is deposited.

Cu (or Au) and the barrier metal on the upper surface of the second interlayer insulating film 11 are removed by the CMP method, and the second
The metal wiring 19 is formed. It is also preferable to form a barrier metal again on the upper surface thereof if necessary.

Then, the third interlayer insulating film 12 made of alumina is formed by sputtering. At this time,
In order to efficiently apply a magnetic field to the magnetic layer of the TMR element 18 which will be arranged in a later step by the current passing through the second metal wiring 19, the thickness of the third interlayer insulating film 12 on the second metal wiring 19 is increased. Is 200 nm or less.

Then, the drain region 6 is formed by the RIE method.
A contact hole 13 is formed by partially removing the third interlayer insulating film 12 located above the upper first metal wiring 10 with high positional accuracy.

Then, after forming a barrier metal made of Ti or TiN in at least the hole 13, a thin film of Cu or Au is formed thereon by CVD. Then, Cu or Au is deposited on the Cu or Au thin film by CVD by plating. In this state, Cu (or Au) and the barrier metal on the third interlayer insulating film 12 are removed by the CMP method to form the second plug 14.
It is also preferable to form a barrier metal again on the upper surface thereof if necessary. In this way, the upper surface of the plug 14 is made smooth (step S15).

Then, the TMR element 18 is formed on the second plug 14. Specifically, by sputtering,
GdFe to be the lower magnetic layer (second magnetic layer) 15, AlO _x to be the tunnel barrier layer (non-magnetic layer) 16, TbFe to be the upper magnetic layer (first magnetic layer) 17, and a protective electrode layer. After Pt, Au, W, etc. are sequentially laminated, the shape is adjusted by an ion milling method.

Then, a fourth interlayer insulating film 20 made of silicon oxide or the like is formed by the CVD method and the coating method so as to fill the TMR element 18.

Then, the fourth interlayer insulating film 20 is polished by the CMP method to expose the upper surface of the protective electrode layer of the TMR element 18 and match the upper surface with the upper surface of the interlayer insulating film 20.

A fifth interlayer insulating film 22 made of silicon oxide is formed by the CVD method or the coating method. And RIE
A groove is formed at a predetermined position of the fifth interlayer insulating film 22 by the method. At least a barrier metal made of Ti or TiN is formed in the groove, and then Cu is formed on the barrier metal by CVD.
Alternatively, a thin film of Au is formed. And CV by plating
Deposit Cu or Au on the Cu or Au thin film according to D. Cu formed on the upper surface of the fifth interlayer insulating film 22 by the CMP method.
(Or Au) and the barrier metal are removed, and the bit line 2
1 is formed. It is also preferable to form a barrier metal again on the upper surface thereof if necessary.

Finally, a passivation film (protective film) 23 made of SiN is formed by the CVD method (step S22).

In this way, the memory cell of the present invention is completed. A peripheral circuit (not shown) is formed in parallel with the formation of the memory cell, and the magnetic memory device is completed.
The material of each member and the specific forming method are not limited to the examples described above, and various changes can be made.

[0081]

As described above, according to the present invention, T
Since the MR element and the bit line are in direct contact with each other, a magnetic field can be efficiently applied to the magnetic layer of the TMR element when a current is passed through the bit line. As a result, power consumption can be reduced and the reliability of the magnetic memory device can be improved. Further, the step of forming the contact hole and the plug can be omitted, and the manufacturing process can be simplified.

Further, when the TMR element is used as a stop layer for polishing to expose the TMR element in a self-aligning manner, the work of polishing the insulating film is simplified and the bit line can be laminated easily and firmly. You can

[Brief description of drawings]

FIG. 1 is a cross-sectional view of essential parts of a magnetic memory device according to a first embodiment of the present invention.

FIG. 2 is a main-portion cross-sectional view showing the manufacturing process of the magnetic memory device of the first embodiment;

FIG. 3 is a main-portion cross-sectional view showing the manufacturing process of the magnetic memory device of the first embodiment;

FIG. 4 is a main-portion cross-sectional view showing the manufacturing process of the magnetic memory device in the first embodiment;

FIG. 5 is a main-portion cross-sectional view showing the manufacturing process of the magnetic memory device in the first embodiment;

FIG. 6 is a main-portion cross-sectional view showing the manufacturing process of the magnetic memory device in the first embodiment;

FIG. 7 is a main-portion cross-sectional view showing the manufacturing process of the magnetic memory device in the first embodiment;

FIG. 8 is a main-portion cross-sectional view showing the manufacturing process of the magnetic memory device in the first embodiment;

FIG. 9 is a main-portion cross-sectional view showing the manufacturing process of the magnetic memory device in the first embodiment;

FIG. 10 is a main-portion cross-sectional view showing the manufacturing process of the magnetic memory device in the first embodiment;

FIG. 11 is a main-portion cross-sectional view showing the manufacturing process of the magnetic memory device in the first embodiment;

FIG. 12 is a main-portion cross-sectional view showing the manufacturing process of the magnetic memory device in the first embodiment;

FIG. 13 is a flowchart showing manufacturing steps of the magnetic memory device according to the first embodiment.

FIG. 14 is a schematic diagram of a TMR element having in-plane magnetization.

FIG. 15 is a schematic diagram of a vertically magnetized TMR element.

FIG. 16 is an enlarged cross-sectional view of a conventional magnetic memory device.

[Explanation of symbols]

1 Semiconductor substrate 2 element isolation region (STI) 3 Gate insulation film 4 gate electrode 5 Source area 6 drain region 7 First interlayer insulating film 8 contact holes 9 First plug 10 First metal wiring 11 Second interlayer insulating film 12 Third interlayer insulating film 13 contact holes 14 Second plug 15 Lower magnetic layer (second magnetic layer) 16 Tunnel barrier layer (nonmagnetic layer) 17 Upper magnetic layer (first magnetic layer) 18 TMR element (tunnel magnetoresistive element) 19 Second metal wiring (write line) 20 Fourth interlayer insulating film (insulating film) 21 bit line 22 Fifth interlayer insulating film 23 Passivation film 24 wiring groove

Continued front page    F term (reference) 5F033 HH09 HH11 HH18 HH21 HH23                       HH27 HH30 HH32 HH33 HH34                       JJ08 JJ11 JJ18 JJ19 JJ21                       JJ23 JJ27 JJ30 KK01 KK32                       KK33 KK34 MM01 MM02 MM12                       MM13 NN06 NN07 PP06 PP15                       QQ13 QQ24 RR01 RR03 RR04                       RR08 RR11 RR15 RR21 RR22                       SS08 SS11 SS21 TT04 VV16                       XX01 XX28                 5F083 FZ10 GA05 GA09 GA25 JA35                       JA36 JA37 JA39 JA40 JA56                       JA57 JA58 LA12 PR03 PR06                       PR21 PR22 PR23 PR40

Claims (11)

[Claims] 1. A first magnetic layer and a second magnetic layer that are magnetized mainly in a direction perpendicular to the film surface, and a non-magnetic layer located between the first magnetic layer and the second magnetic layer. In a non-volatile magnetic memory device having a magnetoresistive effect element and a bit line located above the magnetoresistive element and in which a current for applying a magnetic field flows, an upper surface of the magnetoresistive element and the bit line are A magnetic memory device characterized by being in direct contact. 2. The magnetic memory device according to claim 1, wherein an upper surface of the magnetoresistive element in contact with the bit line is made of Pt, Au, or W. 3. The magnetic memory device according to claim 1, further comprising a write line which is located below the magnetoresistive element and through which a current for applying a magnetic field flows. 4. An outer periphery of the magnetoresistive element is covered with an insulating film, and the polished upper surface of the insulating film and the upper surface of the magnetoresistive element are located at the same height. The magnetic memory device according to claim 1, wherein the bit line is formed on the magnetoresistive element. 5. The magnetic memory device according to claim 1, wherein the magnetoresistive effect element is a spin-dependent tunnel magnetoresistive effect element. 6. A first magnetic layer and a second magnetic layer which are magnetized mainly in a direction perpendicular to the film surface, and a non-magnetic layer located between the first magnetic layer and the second magnetic layer. A method of manufacturing a non-volatile magnetic memory device having a magnetoresistive effect element and a bit line located above the magnetoresistive element and in which a current for applying a magnetic field is flowed, wherein the magnetoresistive effect element is formed. A step of depositing an insulating material to cover the magnetoresistive element to form an insulating film, and a step of polishing the insulating film covering the magnetoresistive element until the upper surface of the magnetoresistive element is exposed. And a step of forming the bit line on the insulating film and the magnetoresistive element, the method of manufacturing a magnetic memory device. 7. The method of manufacturing a magnetic memory device according to claim 6, wherein the polishing step exposes the upper surface of the magnetoresistive element in a self-aligned manner. 8. The polishing step according to claim 6 or 7, wherein polishing is performed using the upper surface of the magnetoresistive element as a stop layer so that the upper surface of the insulating film and the upper surface of the magnetoresistive element have the same height. A method for manufacturing the magnetic memory device described. 9. The insulating film is polished by using a slurry in the polishing step, the polishing speed of the upper surface of the magnetoresistive element being lower than the polishing speed of the insulating film. Item 7. A method for manufacturing a magnetic memory device according to item. 10. The magnetic layer according to claim 6, wherein the first and second magnetic layers have perpendicular magnetic anisotropy.
A method of manufacturing a magnetic memory device according to any one of 1. 11. The method of manufacturing a magnetic memory device according to claim 6, wherein an upper surface of the magnetoresistive element in contact with the bit line is made of Pt, Au, or W.