JP2005142252A - Forming method of alignment mark, semiconductor device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To discriminate an alignment mark at the time of alignment even if a film including a metal film is formed on the alignment mark by forming the alignment mark having a recess on the surface of an insulating film at the same time as a groove wiring and a plug, which are formed by embedding a conductive film in the insulating film. <P>SOLUTION: In a method, the alignment mark 19 used for positioning a pattern 18 lower than the film 21 including the metal film at the time of patterning the film 21 including the metal film formed on the whole face of a substrate where the insulating film 11 is formed on a surface is formed. The pattern 18 on a lower layer being an object of alignment at the time of patterning the film 21 including the metal film is embedded in a recessed part 12 formed in the insulating film 11 so as to be formed. The alignment mark 19 in a state where at least a part is depressed compared to the surface of the insulating film 11 is formed in the other recessed part 13 formed in the insulating film 11 in the same layer as the pattern 18. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for forming an alignment mark, a method for manufacturing a semiconductor device, and a semiconductor device that can easily form an alignment mark on a film surface including a metal film.

  With the rapid spread of information communication equipment, especially small personal devices such as portable terminals, the elements such as memory elements and logic elements are becoming more integrated, faster and have lower power consumption. There is a demand for higher performance. In particular, nonvolatile memories are considered to be indispensable elements in the ubiquitous era.

  For example, the nonvolatile memory can protect important personal information even when the power source is consumed or troubled, or the server and the network are disconnected due to some trouble. Increasing the density and capacity of non-volatile memory is becoming increasingly important as a technology for replacing hard disks and optical discs that are essentially impossible to miniaturize due to the presence of moving parts.

  In addition, recent portable devices are designed to reduce power consumption as much as possible by setting unnecessary circuit blocks to the standby state. However, if a non-volatile memory that can serve both as a high-speed network memory and a large-capacity storage memory can be realized. The waste of power consumption and memory can be eliminated. In addition, a so-called instant-on function that can be started instantly when the power is turned on becomes possible if a high-speed, large-capacity nonvolatile memory can be realized.

Examples of the nonvolatile memory include a flash memory using a semiconductor and an FRAM (Ferro electric Random Access Memory) using a ferroelectric. However, the flash memory has a disadvantage that it is slow because the writing speed is in the order of microseconds. In addition, since the structure is complicated, it is difficult to achieve high integration, and the access time is as slow as about 100 ns. On the other hand, it has been pointed out that the FRAM has a low endurance to replace the static random access memory (DRAM) or the dynamic random access memory (SRAM) with the number of rewritable times of 10 ¹² to 10 ¹⁴ completely. . In addition, it has been pointed out that it is difficult to finely process ferroelectric capacitors.

  A magnetic memory called MRAM (Magnetic Random Access Memory) or MR (Magneto Resistance) memory is attracting attention as a non-volatile memory that does not have these drawbacks, and is a recent tunnel magnetoresistive element (hereinafter referred to as TMR). : TMR is an abbreviation of Tunnel Magnetic Resistance) and has been attracting attention due to improved material properties (for example, see Non-Patent Document 1).

  The MRAM has a simple structure and can be easily integrated. Further, since the memory is stored by rotating the magnetic moment, the number of rewrites is predicted to be large. The access time is also expected to be very high, and it has already been reported that it can operate at 100 MHz (for example, see Non-Patent Document 2). In addition, at the present time when high output can be obtained by the GMR effect, it has been greatly improved.

  Next, an MRAM composed of a conventional 1-select element and 1TMR element (1T1J structure) will be described with reference to the schematic cross-sectional view of FIG. FIG. 7 shows an example in which a MOS transistor is used as the selection element.

  As shown in FIG. 7, there is a semiconductor element substrate 110 on which elements, wirings, insulating films and the like are formed. Although not shown, for example, a field effect transistor is formed on the semiconductor element substrate 110 as a selection element. This field effect transistor functions as a switching element for reading. In addition to the n-type or p-type field effect transistor, various switching elements such as a diode and a bipolar transistor can be used. Although not shown, a first insulating film is formed on the semiconductor element substrate 110 so as to cover the field effect transistor, and a contact (for example, a tungsten plug) connected to the selection element is formed on the first insulating film. Has been. Further, a connection electrode 131 connected to the contact, a sense line (not shown), and the like are formed on the first insulating film.

  A second insulating film 142 is formed on the first insulating film. The second insulating film 142 in the memory cell region 103 covers the sense line (not shown), the connection electrode 131, and the like. Further, a contact (for example, a tungsten plug) 132 connected to the connection electrode 131 is formed on the second insulating film 142. Further, on the second insulating film 142, a connection electrode 133 connected to the contact 132, a first wiring (write word line) 111, and the like are formed. In the following, description will be given as a write word line. On the other hand, a first wiring 161 of the peripheral circuit region 8 is formed on the second insulating film 142 in the peripheral circuit region 105.

  A third insulating film 143 is formed on the second insulating film 142 in the memory cell region 103 to cover the write word line 111, the connection electrode 133, the first wiring 161 in the peripheral circuit region 105, and the like. The third insulating film 143 has a structure in which, for example, an insulating film that serves as an etching stopper, an interlayer insulating film, an insulating film that serves as an etching stopper, and an interlayer insulating film are stacked in this order from the lower layer, and the surface is planarized. Yes. When the write word line 111 and the first wiring 161 are formed of, for example, a buried copper wiring, an insulating film serving as an upper etching stopper is a film that prevents diffusion of copper and prevents oxygen from entering the copper wiring. Also preferably function, for example, formed of a nitride film. In the third insulating film 143, a plug 134 connected to the connection electrode 133 and a plug 171 connected to the first wiring 161 in the peripheral circuit region 105 are formed. These plugs 134, 171 and the like are generally formed by embedding using copper.

  Further, a lower electrode layer 305 connected to the plug 134 from above the write word line 111 is formed on the third insulating film 143 in the memory cell region 103, and on the lower electrode layer 135 and the write word line. A storage element (hereinafter referred to as a TMR element) 113 is formed above 111. As an example, the memory element 113 has a magnetization fixed layer made of a ferromagnetic layer, a tunnel insulating layer formed on the magnetization fixed layer, and a magnetization formed on the tunnel insulating layer. The magnetization rotates relatively easily. And a cap layer formed on the storage layer. The lower electrode layer 135 is formed of, for example, an antiferromagnetic layer. In the lower electrode layer 135, a bypass line (shown integrally with the lower electrode layer 135 in the drawing) is formed with the magnetization fixed layer extended on the antiferromagnetic material layer.

  A fourth insulating film 144 is formed on the third insulating film 143 in the memory cell region 103 to cover the memory element 113 and the like. The surface of the fourth insulating film 144 is flattened, and the uppermost cap layer surface of the memory element 113 is exposed. On the fourth insulating film 144, a second wiring (which is connected to the upper surface of the memory element 113 and crosses three-dimensionally (for example, orthogonally) between the write word line 111 and the memory element 113. Bit line) 112 is formed.

  On the other hand, the second wiring 162 of the peripheral circuit region 105 is formed on the fourth insulating film 144 in the peripheral circuit region 105. A plug 171 connected to the first wiring 161 and a plug 172 connected to the second wiring 162 are formed in the fourth insulating film 144. The plugs 171 and 172 may be integrally formed.

  Here, a general example of a method for forming a copper wiring and a copper plug will be described with reference to FIG. As shown in FIG. 8A, after a groove (or connection hole) 212 is formed in the insulating film 211, a barrier metal layer 213 is formed on the inner surface of the groove (or connection hole) 212 by sputtering, for example. Next, a copper film 214 serving as a copper plating seed is formed. Thereafter, copper is deposited by electrolytic plating so as to fill the groove (or connection hole) 212 to form a copper film 215. Next, as shown in FIG. 8B, an excessive copper film 215 (seeding copper film 214) on the insulating film 211 is formed using a chemical mechanical polishing (CMP, CMP is an abbreviation for Chemical Mechanical Polishing) method. And the barrier metal layer 213 are removed to form a copper wiring (or copper plug) 216 made of the copper film 215 through the barrier metal layer 213 in the groove (or connection hole) 212.

  In addition, as a method for forming an alignment mark using a metal film, the alignment pattern forming groove and the circuit pattern forming groove formed in the insulating film are filled with the metal film, and the alignment mark and circuit pattern forming pattern are formed. A technique is disclosed in which the height of the upper surface of the alignment mark protrudes from the height of the upper surface of the insulating film by etching back the upper surface of the insulating film after forming the buried metal film (for example, Patent Documents). 1).

Republished patent WO99 / 08314 Wang et al., “Feasibility of Ultra-Dense Spin-Tunneling Random Access Memory” IEEE Transaction on Magnetics 33 [6] (Nov. 1997) p4498-4512 R. Scheuerlein et al, “TA7.2 A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell” 2000 IEEE International Solid-State Circuits Conference Digest of Papers (Feb.2000) p128- 129

  The problems to be solved are as follows. That is, when a copper film is formed using a plating method and a copper wiring is formed in a groove or a copper plug is formed in a connection hole, a recess that becomes a wide alignment mark formed simultaneously with the groove or connection hole is also plated. A copper film is formed conformally. For this reason, after the CMP process, a copper film is embedded in the concave portion serving as the alignment mark, and the step with the field portion is eliminated. Thereafter, the lower electrode layer and the TMR layer are formed, and the TMR element is patterned. At this time, it is necessary to align the patterning position of the TMR element with the underlying copper plug or copper wiring (for example, write word line). In other words, it is necessary to detect an alignment mark without a step embedded with copper in a state where a film including a metal film such as a lower electrode layer and a TMR layer is formed, but the alignment measurement light is reflected by the metal film. Therefore, it is difficult to detect the alignment mark. When the technique disclosed in Patent Document 1 is applied to the MRAM manufacturing technique, the copper plug or copper wiring (for example, write word line) portion also protrudes from the upper surface of the insulating film. When viewed from the surface, a step is produced in the copper plug or copper wiring (for example, write word line). When a TMR layer formed by laminating a thin film on the upper part having such a step is patterned, there is a problem that the patterning accuracy is lowered.

  The alignment mark forming method of the present invention is positioned with respect to a pattern below the film including the metal film when patterning the film including the metal film formed on the entire surface of the substrate having the insulating film formed on the surface. In the method of forming an alignment mark used for alignment, the insulating film is simultaneously formed by embedding the lower layer pattern to be aligned when the film including the metal film is patterned into a recess formed in the insulating film. The most important feature is that an alignment mark having at least a part recessed from the surface of the insulating film is formed in the same layer as the lower layer pattern in another recess formed in step (b).

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming a first conductive portion in a first insulating film formed on a substrate in a state where an upper surface thereof is exposed, and the first conductive portion on the first insulating film. Forming a second insulating film covering the portion, forming a connection hole leading to the first conductive portion in the second insulating film and forming a recess from the second insulating film to the first insulating film And forming a conductive film so as to bury the connection hole on the second insulating film and at least partially lower the surface of the second insulating film in the recess, and on the second insulating film The conductive film is removed to form a second conductive portion with the conductive film buried in the connection hole, and at least a part of the conductive film is lower in the recess than the surface of the second insulating film. Form an alignment mark The most important feature that a degree.

  A semiconductor device according to the present invention includes a first conductive portion embedded in a first insulating film formed on a substrate, and a second insulating layer that covers the first conductive portion and is formed on the first insulating film. A film, a second conductive part connected to the first conductive part through a connection hole communicating with the first conductive part formed in the second insulating film, and an alignment mark at the time of alignment. A conductive film of the same layer as the conductive film constituting the second conductive portion is embedded in a recess formed simultaneously with the connection hole from the insulating film to the first insulating film so as to be lower than the surface of the second insulating film. The most important feature is that it is provided with the formed alignment mark.

  In the method for forming an alignment mark according to the present invention, a so-called mask process is simultaneously performed because an alignment mark is formed at the same time as a lower layer pattern to be aligned when a film including a metal film is patterned. That is, since the lower layer pattern and the alignment mark can be formed with the same mask, there is an advantage that mask misalignment does not occur between the lower layer pattern and the alignment mark. In addition, since the alignment mark is formed in a state in which at least a part is recessed from the surrounding insulating film surface, even if a film including a metal film is formed on the alignment mark, the alignment mark is formed on the film surface including the metal film. Since the depression of the alignment mark is transferred and the depression is formed on the surface of the film including the metal film, the alignment between the pattern formed using the film including the metal film and the pattern of the lower layer can be performed accurately. There are advantages. Therefore, an alignment mark having a depression with respect to the surface of the insulating film can be formed simultaneously with the trench wiring and plug formed by burying the conductive film in the insulating film, and a film including a metal film is formed on the alignment mark. However, it is possible to determine the alignment mark at the time of alignment.

  According to the method of manufacturing a semiconductor device of the present invention, the connection hole leading to the first conductive portion is formed in the second insulating film and the recess is formed from the second insulating film to the first insulating film. Therefore, there is an advantage that mask misalignment does not occur between the connection hole and the concave portion. In addition, the conductive film is formed on the second insulating film so that the connection hole is embedded and at least a part of the concave portion is lower than the surface of the second insulating film in the recess, and then the conductive film on the second insulating film is removed. The second conductive portion is formed of the conductive film embedded in the connection portion and the alignment mark is formed in the recess so that at least a part of the conductive film is lower than the surface of the second insulating film. Since it is formed in a state in which at least a part is recessed from its surroundings, even if a film including a metal film is formed on the alignment mark, the depression of the alignment mark is transferred to the film surface including the metal film, Since the depression is formed on the film surface including the metal film, there is an advantage that the pattern formed by the film including the metal film and the lower connection hole can be accurately aligned.

  The semiconductor device of the present invention includes a conductive film that constitutes the second conductive portion such that the alignment mark is lower than the surface of the second insulating film in a recess formed simultaneously with the connection hole from the second insulating film to the first insulating film. Since the conductive film of the same layer is embedded, even if a film including a metal film is formed on the alignment mark, the depression of the alignment mark is transferred to the surface of the film including the metal film. Since the depression is formed on the surface of the film including the film, there is an advantage that alignment between the pattern formed of the film including the metal film and the connection hole in the lower layer can be performed accurately.

  At the same time as forming the lower layer pattern to be aligned with the film including the metal film, the purpose is to perform alignment with a pattern (for example, embedded wiring or embedded plug) below the metal layer in a state where the metal layer is formed. This is realized by forming an alignment mark in which at least a part is recessed from the periphery.

  One embodiment of the alignment mark forming method of the present invention will be described with reference to the cross-sectional view of the manufacturing process of FIG.

  As shown in FIG. 1A, a recess 12 for forming a lower layer pattern (for example, a connection hole or a wiring) is formed in the insulating film 11, and a recess 13 in which an alignment mark is formed is formed. At this time, the recess 13 where the alignment mark is formed is formed wider and deeper than the recess 12 where the lower layer pattern is formed. That is, the width and depth of the recess 13 are formed such that when the recess 12 is embedded with the metal film, a recess is formed on the surface of the metal film embedded in the recess 13.

  Next, as shown in FIG. 1B, a metal film for forming a lower layer pattern is deposited in the recess 12. For example, after depositing the barrier metal layer 14 by sputtering, a plating seed layer (not shown) is formed, and the conductive film 16 is formed so as to completely fill the recess 12 by a plating method. At this time, since the recess 13 is formed wider and deeper than the recess 12, a recess 17 that is lower than the surface of the insulating film 11 is formed on the surface of the conductive film 16.

  Next, as shown in FIG. 1C, the conductive film 16 on the insulating film 11 is removed, and the surface of the insulating film 11 is planarized. The step of removing the conductive film 16 is performed by, for example, a chemical mechanical polishing method. As a result, a conductive portion 18 made of a conductive film 16 (including a plating seed layer) with a barrier metal layer 14 interposed therebetween is formed in the concave portion 12, and at least one of the concave portion 13 is larger than the periphery, that is, the surface of the insulating film 11. An alignment mark 19 is formed in a state where the portion is depressed.

  Next, as shown in FIG. 1 (4), a film 21 including a metal film is formed on the insulating film 11. When the film 21 including the metal film is formed in this way, since the recess 20 is formed on the alignment mark 19, the recess 20 is transferred to the surface of the film 21 including the metal film and includes the metal film. A recess 22 is also formed on the surface of the film 21. The recess 22 serves as an alignment mark when the film 21 including the metal film is patterned.

  In the method of forming the alignment mark, the so-called mask process is also performed at the same time as the formation of the alignment mark 19 at the same time as the formation of the lower conductive portion 18 to be aligned with the film 21 including the metal film. That is, since the concave portion 12 in which the lower conductive portion 18 is formed and the concave portion 13 in which the alignment mark 19 is formed are formed with the same mask, the mask misalignment between the lower conductive portion 18 and the alignment mark 19 is formed. There is an advantage that does not occur. Further, since the alignment mark 19 is formed in a state in which at least a part thereof is recessed from the periphery thereof, even if the film 21 including the metal film is formed on the alignment mark 19, the surface of the film 21 including the metal film is formed. Since the depression 20 of the alignment mark 19 is transferred and the depression 22 is formed on the surface of the film 21 including the metal film, the alignment between the pattern formed using the film 21 including the metal film and the lower conductive portion 18 is performed. There is an advantage that it can be performed accurately. In addition, the alignment mark forming method of the present invention forms a film that does not transmit alignment light (a film that is opaque to alignment light) or a film that does not easily transmit, instead of forming a film including a metal film. It is also effective in some cases.

  Next, an embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the manufacturing process sectional views of FIGS. 2 to 5, an example of a method for manufacturing an MRAM using a so-called trench wiring structure will be described.

  As shown in FIG. 2A, there is a semiconductor element substrate 30 on which elements, wirings, insulating films and the like are formed.

  Although not shown in the figure, for example, a field effect transistor is formed as a selection element on the semiconductor element substrate 30. This field effect transistor functions as a switching element for reading. As the switching element, various switching elements such as a diode and a bipolar transistor can be used in addition to the n-type field effect transistor or the p-type field effect transistor. Further, an insulating film is formed on the semiconductor element substrate 30 so as to cover the field effect transistor, and contacts, sense lines, and the like connected to the selection element are formed on the insulating film.

A first insulating film 41 is formed on the semiconductor element substrate 30 configured as described above. The first insulating film 41 is formed to have a two-layer structure of an etching stopper layer 411 and an interlayer insulating film 412. For example, the etching stopper layer 411 is formed of a silicon nitride (SiN) film or a silicon carbide (SiC) film. Then, the interlayer insulating film 412 is formed of a silicon oxide film. This interlayer insulating film can also be formed of an oxide insulating film (for example, SiO ₂ film, SiOF film, SiOC film), an organic insulating film, or a laminated film appropriately combining them. A groove 413 for forming a word line and a groove 414 for forming a first electrode connected to the contact are formed in the first insulating film 41 using a technique for forming a normal groove wiring. After depositing a conductive material layer 512, such as copper or a copper alloy, in the trenches via the barrier metal layer 511, unnecessary conductive material layers and barrier metal layers on the first insulating film 41 are removed to remove the trenches. A first electrode 51 (first conductive portion) made of a conductive material layer, a word line 31 and the like are formed inside through a barrier metal layer. The barrier metal layer can be formed of the same material as a barrier metal layer described later. The conductive material layer and the barrier metal layer can be removed by chemical mechanical polishing, for example.

  Next, a second insulating film 42 is formed on the first insulating film 41. Similar to the first insulating film 41, the second insulating film 42 is formed to have a two-layer structure of an etching stopper layer 421 and an interlayer insulating film 422. The surface of the second insulating film 42 is flattened. The insulating film to be the etching stopper layer 421 that constitutes the second insulating film 42 preferably functions as a film that prevents diffusion of copper and also prevents oxygen from entering the copper wiring. It is formed with a carbonized film.

  Next, a step of forming a connection hole leading to the first electrode 51 in the second insulating film 42 and forming a recess for forming an alignment mark from the second insulating film 42 to the first insulating film 41 is performed. Details thereof will be described below.

  First, as shown in FIG. 2B, a first resist film 61 is formed on the second insulating film. Then, a normal lithography process (exposure process, development process, etc.) is performed to form a recess for forming a contact portion (hereinafter referred to as a connection hole) and an alignment mark for alignment with the next layer. Openings 62 and 63 are formed for forming recesses to be formed. Thereafter, using the first resist film 61 as an etching mask, the interlayer insulating film 422 is etched to form a connection hole 71 for forming a contact and a recess 72 for forming an alignment mark.

  Next, as shown in FIG. 2 (3), a second resist film 65 is further formed with the first resist film 61 remaining. The first resist film 61 and the second resist film 65 may use the same type of resist, but may use different types of resist. Next, a normal lithography process (exposure process, development process, etc.) is performed to form the opening 66 only on the recess 72 for forming the alignment mark. Accordingly, the connection hole 71 formed using the first resist film 61 is covered with the second resist film 65.

  Next, as shown in FIG. 3D, the etching stopper layer 421 and the interlayer insulating film 412 of the first insulating film 41 are etched using the second resist film 65 and the first resist film 61 as an etching mask. The recess 72 is formed to extend downward. Thereafter, the first resist film 61 and the second resist film 65 are removed.

  Thereafter, as shown in FIG. 3 (5), the etching stopper layers 421 and 411 formed on the bottoms of the connection hole 71 and the recess 72 are removed by etching. In this way, the connection hole 71 that leads to the first electrode 51 of the first conductive portion is formed in the second insulating film 42, and the recess 72 that forms the alignment mark from the second insulating film 42 to the first insulating film 41 is formed. It is formed. The recess 72 needs to be formed deeper and wider than the connection hole 71. In the above description, the recess 72 has a depth equivalent to the bottom surface of the word line 11, that is, a depth obtained by removing the first insulating film 41. However, the recess 72 is formed deeper than the connection hole 71. If it is, it does not ask | require in particular to which layer it etches.

  Next, as shown in FIG. 3 (6), the connection hole 71 is embedded in the second insulating film 42 and at least a part of the recess 72 is lower than the surface of the second insulating film 42. A conductive film 81 is formed. The conductive film 81 includes, for example, a barrier metal layer 82 and a conductive material layer 83. Hereinafter, the film forming process of the conductive film 81 will be described in detail.

  First, the barrier metal layer 82 is formed on the second insulating film 42 so as to cover the inner surfaces of the connection hole 71 and the recess 72. The barrier metal layer 82 is formed by sputtering, for example, and is formed of a material that prevents copper diffusion and reaction. Examples of such a material include tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), titanium (Ti), and titanium nitride (TiN). Next, after forming a seed layer (not shown) of copper plating, a conductive material layer 83 which is a main material to be embedded is formed by a plating method. The conductive material layer 83 is formed by depositing, for example, copper (Cu). At this time, although the conductive material layer 83 is deposited on the second insulating film 42, the conductive material layer 83 is formed so as to fill the connection hole 71 and to be at least partially lower than the surface of the second insulating film 42 in the recess 72. It is important that The conductive material layer 83 can be formed of a copper alloy in addition to copper (Cu).

  Next, as shown in FIG. 4 (7), the conductive film 81 (conductive material layer 83 and barrier metal layer 82) on the second insulating film 42 is removed, and the conductive film 81 embedded in the connection hole 71 is used. A second conductive part (plug) 52 is formed, and an alignment mark 53 in a state where at least a part of the conductive film 81 is lower than the surface of the second insulating film 42 is formed in the recess 72. The removal of the conductive film 81 is performed by, for example, a chemical mechanical polishing method.

  Next, as shown in FIG. 4 (8), a lower electrode layer 84 that covers the plug 52 and the alignment mark 53 is formed on the second insulating film 42. Further, a TMR layer 85 constituting a memory element is formed on the lower electrode layer 84.

  Although not shown in detail, the lower electrode layer 84 has, for example, a single layer structure of a conductive layer or a stacked structure of a conductive layer and an antiferromagnetic material layer. Examples of the conductive layer include titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The antiferromagnetic layer may be, for example, an iron / manganese (Fe—Mn) alloy, a nickel / manganese (Ni—Mn) alloy, a platinum / manganese (Pt—Mn) alloy, an iridium / manganese (Ir—Mn) alloy, A rhodium-manganese (Rh—Mn) alloy, a cobalt oxide and a nickel oxide, or a laminated structure thereof can be given.

  Although not shown in detail, the TMR layer 85 is, for example, a magnetization fixed layer made of a ferromagnetic layer, a tunnel insulating layer formed on the magnetization fixed layer, and formed on the tunnel insulating layer. It is composed of a storage layer whose magnetization rotates relatively easily. Although not shown, a cap layer made of a conductive material is formed on the TMR layer 85.

  The memory layer and the first magnetization fixed layer are, for example, at least two of nickel (Ni), iron (Fe) or cobalt (Co), or nickel (Ni), iron (Fe) and cobalt (Co) It is made of a ferromagnetic material such as an alloy made of The conductor layer is made of, for example, ruthenium (Ru), copper (Cu), chromium (Cr), gold (Au), silver (Ag), or the like. The first magnetization pinned layer is formed in contact with the antiferromagnetic layer, and the first magnetization pinned layer exhibits a strong unidirectional magnetic anisotropy due to exchange interaction between these layers. Have.

  The tunnel insulating layer is made of, for example, aluminum oxide, magnesium oxide, silicon oxide, aluminum nitride, magnesium nitride, silicon nitride, aluminum oxynitride, magnesium oxynitride, or silicon oxynitride. The tunnel insulating layer has a function of cutting the magnetic coupling between the storage layer and the magnetization fixed layer and flowing a tunnel current. These magnetic films and conductor films are mainly formed by sputtering. The tunnel insulating layer can be obtained by oxidizing, nitriding or oxynitriding a metal film formed by a sputtering method.

  The cap layer has functions of preventing mutual diffusion between the memory element 13 and a wiring connecting another memory element 13, reducing contact resistance, and preventing oxidation of the memory layer. Usually, it is formed of a material having a barrier property such as tantalum nitride (TaN), tantalum (Ta), titanium nitride (TiN), titanium (Ti), or the like. Alternatively, it can be formed of copper, a copper alloy, or the like.

  Next, as shown in FIG. 4 (9), a resist film is formed on the TMR layer 85, and a normal lithography process (exposure process, development process, etc.) is performed to form a memory element (TMR element). A pattern 67 is formed. In the exposure process of this lithography process, the step (depression 86) of the TMR layer 85 formed by transferring the step (depression 54) of the alignment mark 53 is detected, and the second conductive portion (plug) 52 and TMR element formation are detected. The alignment of the location is taken and the resist film is exposed. In this way, a resist pattern 67 made of a resist film is formed.

  Next, as shown in FIG. 5 (10), the TMR layer 85 is etched using the resist pattern 67 as an etching mask, and a memory element (TMR element) 33 is formed by the TMR layer 85. Thereafter, the resist pattern 67 is removed. The TMR layer 85 and the cap layer (not shown) can be patterned at the same time.

  Next, as shown in FIG. 5 (11), a resist film is formed on the lower electrode layer 84, and a normal lithography process (exposure process, development process, etc.) is performed to form a resist pattern (FIG. 5). (Not shown). In the exposure process of this lithography process, the step (depression) of the lower electrode layer 84 formed by transferring the step (depression 54) of the alignment mark 53 is detected to form the second conductive portion (plug) 52 and the lower electrode. The alignment of the location is taken and the resist film is exposed. In this way, the resist pattern made of a resist film is formed. Next, using the resist pattern as an etching mask, the lower electrode layer 84 is etched to form the lower electrode 34 with the lower electrode layer 84. Note that the lower electrode 34 may be configured with the magnetization fixed layer extended on the antiferromagnetic material layer.

  Thereafter, as shown in FIG. 5 (12), after forming a third insulating film 43 covering the memory element 33, a cap layer (not shown) formed on the upper surface of the memory element 33 is exposed. The surface of the third insulating film 43 is planarized. Thereafter, bit lines 32 that form a three-dimensional intersection (eg, orthogonal) between the word lines 31 and the storage elements 33 are formed using a normal wiring formation technique. Alternatively, although not shown, after the third insulating film 43 is formed so as to cover the memory element 33, a connection hole reaching the cap layer of the memory element 33 is opened in the third insulating film 43, and the cap is passed through the connection hole. The bit line 32 may be formed so as to be connected to a layer. Alternatively, the bit line 32 may be formed after a plug is formed in the connection hole.

  The memory element 33 described above is not limited to the above configuration as long as it has a tunnel magnetic resistance (TMR) effect. As an example, a pinned magnetic layer formed on the antiferromagnetic layer includes a conductor layer and a second pinned magnetic layer in which the first pinned magnetic layer and the magnetic layer are antiferromagnetically coupled. It can also be formed by laminating in order. This magnetization fixed layer may be a laminated structure, a single layer structure of a ferromagnetic layer, or a structure in which three or more ferromagnetic layers are laminated with a conductor layer interposed therebetween. Also good. It is also possible to form a base conductive layer (not shown) used for connection with the switching element connected in series with the TMR element on the base of the antiferromagnetic material layer. In addition, the base conductive layer can also be used as an antiferromagnetic material layer.

  Further, when the TMR layer 85 is patterned, an insulating film such as an oxide film or a nitride film may be formed and processed on the TMR layer 85 as a hard mask. Further, when processing the lower electrode, as in the case of processing the TMR layer, for example, an insulating film such as an oxide film or a nitride film may be formed and processed using a hard mask.

  In the semiconductor device manufacturing method, the connection hole 71 that communicates with the first electrode 51 of the first conductive portion is formed in the second insulating film 42 and the recess 72 is formed from the second insulating film 42 to the first insulating film 41. Since the connection hole 71 and the concave portion 72 can be formed with the same mask, there is an advantage that the mask misalignment does not occur between the connection hole 71 and the concave portion 72. A conductive film 81 having a recess is formed on the second insulating film 42 so that the connection hole 71 is buried and at least a part of the concave portion 72 is lower than the surface of the second insulating film 42. The conductive film 81 on the film 42 is removed to form the second conductive part 52 with the conductive film 81 embedded in the connection hole 71, and at least a part of the conductive film 81 in the recess 72 is the surface of the second insulating film 42. Since the alignment mark 53 in a lower state is formed, the alignment mark 53 is formed in a state in which at least a part thereof is recessed from the periphery thereof, so that a metal film, for example, the lower electrode layer 84, is formed on the alignment mark 53. Even when the TMR layer 85 is formed, the depression 54 of the alignment mark 53 is transferred to the surface of the lower electrode layer 84 and the TMR layer 85, so that the lower electrode layer 84 and the TMR layer 85 are transferred. Since the recess is formed on the surface, the lower electrode layer 84, the lower electrode 34 formed of the TMR layer 85, the memory element 33, and the first conductive portion 51 (connection hole 71) in the lower layer can be accurately aligned. There is an advantage that you can.

  Therefore, a device corresponding to miniaturization and high integration can be created, and highly reliable wiring can be formed. The manufacturing method of the semiconductor device of the present invention is not limited to MRAM, and even when copper (Cu) wiring or copper (Cu) plug is used, it is possible to form a step with respect to the field only for the alignment mark. In particular, it is possible to detect a lower alignment mark in a state where a lower electrode considered to be a general structure in an MRAM device or a TMR layer is formed. Further, the formation process of copper (Cu) wiring and copper (Cu) plug does not greatly change the conventionally used film forming process, polishing process, etc., so there is a concern that the reliability of the wiring, the yield, etc. may be deteriorated. Can be introduced without.

  Next, an embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the schematic sectional view of FIG. In FIG. 6, an MRAM using a so-called trench wiring structure will be described as an example.

  As shown in FIG. 6, there is a semiconductor element substrate 30 on which elements, wirings, insulating films and the like are formed. Although not shown in the figure, for example, a field effect transistor is formed as a selection element on the semiconductor element substrate 30. This field effect transistor functions as a switching element for reading. As the switching element, various switching elements such as a diode and a bipolar transistor can be used in addition to the n-type field effect transistor or the p-type field effect transistor. Further, an insulating film is formed on the semiconductor element substrate 30 so as to cover the field effect transistor, and contacts, sense lines, and the like connected to the selection element are formed on the insulating film.

A first insulating film 41 is formed on the semiconductor element substrate 30 configured as described above. The first insulating film 41 is formed to have a two-layer structure of an etching stopper layer 411 and an interlayer insulating film 412. For example, the etching stopper layer 411 is formed of a silicon nitride (SiN) film or a silicon carbide (SiC) film. The interlayer insulating film 412 is formed of a silicon oxide film. This interlayer insulating film can also be formed of an oxide insulating film (for example, SiO ₂ film, SiOF film, SiOC film), an organic insulating film, or a laminated film appropriately combining them. In the first insulating film 41, a word line 31 having a trench wiring structure, a first electrode 51 (first conductive portion) connected to the contact, and the like are formed.

  A second insulating film 42 is formed on the first insulating film 41. Similar to the first insulating film 41, the second insulating film 42 is formed to have a two-layer structure of an etching stopper layer 421 and an interlayer insulating film 422. The surface of the second insulating film 42 is flattened. The insulating film to be the etching stopper layer 421 that constitutes the second insulating film 42 preferably functions as a film that prevents diffusion of copper and also prevents oxygen from entering the copper wiring. It is formed with a carbonized film.

  In the second insulating film 42, a second conductive portion (plug) 52 is formed inside the connection hole 71 that communicates with the first electrode 51 and is formed from the second insulating film 42 to the first insulating film 41. An alignment mark 53 that is at least partially lower than the surface of the second insulating film 42 is formed in the recess 72. The surface of the second insulating film 42 on the memory region where the second conductive portion (plug) 52, the word line 31, the selection element, and the like are formed is flattened, and a step is formed only on the alignment mark 53 portion. A recess 54 is formed.

  Further, a lower electrode 34 connected to the second conductive portion 52 is formed on the second insulating film 42 so as to be drawn above the word line 31. Further, a memory element 33 is formed on the lower electrode 34 above the word line 31. The lower electrode 34 and the memory element 33 can have the same configuration as that described in the second embodiment.

  That is, although not shown in detail, the lower electrode 34 has, for example, a single layer structure of a conductive layer or a laminated structure of a conductive layer and an antiferromagnetic material layer. Examples of the conductive layer include titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The antiferromagnetic layer may be, for example, an iron / manganese (Fe—Mn) alloy, a nickel / manganese (Ni—Mn) alloy, a platinum / manganese (Pt—Mn) alloy, an iridium / manganese (Ir—Mn) alloy, A rhodium-manganese (Rh—Mn) alloy, a cobalt oxide and a nickel oxide, or a laminated structure thereof can be given. Note that the lower electrode 34 may be configured with the magnetization fixed layer extended on the antiferromagnetic material layer.

  Further, although not shown in detail, the memory element 33 is formed by, for example, a magnetization fixed layer made of a ferromagnetic layer, a tunnel insulating layer formed on the magnetization fixed layer, and a tunnel insulating layer. It is composed of a storage layer whose magnetization rotates relatively easily. A cap layer made of a conductive material is formed on the memory layer.

  The memory layer and the first magnetization fixed layer are, for example, at least two of nickel (Ni), iron (Fe) or cobalt (Co), or nickel (Ni), iron (Fe) and cobalt (Co) It is made of a ferromagnetic material such as an alloy made of The conductor layer is made of, for example, ruthenium (Ru), copper (Cu), chromium (Cr), gold (Au), silver (Ag), or the like. The first magnetization pinned layer is formed in contact with the antiferromagnetic layer, and the first magnetization pinned layer exhibits a strong unidirectional magnetic anisotropy due to exchange interaction between these layers. Have.

  The tunnel insulating layer is made of, for example, aluminum oxide, magnesium oxide, silicon oxide, aluminum nitride, magnesium nitride, silicon nitride, aluminum oxynitride, magnesium oxynitride, or silicon oxynitride. The tunnel insulating layer has a function of cutting the magnetic coupling between the storage layer and the magnetization fixed layer and flowing a tunnel current. These magnetic films and conductor films are mainly formed by sputtering. The tunnel insulating layer can be obtained by oxidizing, nitriding or oxynitriding a metal film formed by a sputtering method.

  The cap layer has functions of preventing mutual diffusion between the memory element 13 and a wiring connecting another memory element 13, reducing contact resistance, and preventing oxidation of the memory layer. Usually, it is formed of a material having a barrier property such as tantalum nitride (TaN), tantalum (Ta), titanium nitride (TiN), titanium (Ti), or the like. Alternatively, it can be formed of copper, a copper alloy, or the like.

  Further, a third insulating film 43 that covers the memory element 33 is formed. The surface of the third insulating film 43 is flattened so as to expose a cap layer (not shown) formed on the upper surface of the memory element 33. On the third insulating film 43, there are formed bit lines 32 that intersect three-dimensionally with the word line 31 and the storage element 33 in between. Alternatively, although not shown, the third insulating film 43 is formed so as to cover the memory element 33, and a connection hole reaching the cap layer of the memory element 33 is opened in the third insulating film 43, and the cap is passed through the connection hole. The bit line 32 may be formed so as to be connected to the layer. Alternatively, the bit line 32 may be formed so as to be connected to a plug formed in the connection hole.

  The memory element 33 described above is not limited to the above configuration as long as it has a tunnel magnetic resistance (TMR) effect. As an example, a pinned magnetic layer formed on the antiferromagnetic layer includes a conductor layer and a second pinned magnetic layer in which the first pinned magnetic layer and the magnetic layer are antiferromagnetically coupled. It can also be formed by laminating in order. This magnetization fixed layer may be a laminated structure, a single layer structure of a ferromagnetic layer, or a structure in which three or more ferromagnetic layers are laminated with a conductor layer interposed therebetween. Also good. It is also possible to form a base conductive layer (not shown) used for connection with the switching element connected in series with the TMR element on the base of the antiferromagnetic material layer. In addition, the base conductive layer can also be used as an antiferromagnetic material layer.

  In the semiconductor device (MRAM), the second conductive film is formed so that the alignment mark 53 is lower than the surface of the second insulating film 42 in the recess 72 formed simultaneously with the connection hole 71 from the second insulating film 42 to the first insulating film 41. Since the conductive film of the same layer as the conductive film constituting the portion 52 is embedded, a film including a metal film for forming the lower electrode 34 and the memory element 33 is formed on the alignment mark 53. Since the depression 54 of the alignment mark 53 is transferred to the film surface including the metal film, and the depression is formed on the film surface including the metal film, the lower electrode 34 or the storage element formed of the film including the metal film or the like. There is an advantage that the alignment of the connecting hole 33 and the lower connection hole 71 can be performed accurately. As a result, the alignment between the word line 31 and the storage element 33 can be accurately performed, and the effect that the writing efficiency to the storage element 33 can be improved, and the performance of the MRAM can be improved.

  In the above embodiment, the case where the position of the TMR element is aligned with respect to the copper or copper alloy plug has been described as an example. However, the copper or copper alloy is embedded in the recess for forming the element, wiring, electrode, or the like by plating. In addition, copper or copper alloy is embedded in the concave portion where the alignment mark is to be formed, and at least part of the alignment mark is formed deeper than the surrounding surface, thereby forming a step in the alignment mark. If it is characterized, the location which applies the formation method of the alignment mark of this invention and the manufacturing method of a semiconductor device is not limited to the location demonstrated above.

  In the alignment mark forming method, the semiconductor device manufacturing method, and the semiconductor device according to the present invention, a film including a metal film is formed on an upper layer in which at least a part of the surface is planarized, such as a buried copper wiring or a buried copper plug. The present invention can be applied to a technique for detecting a lower alignment mark in a state, and in particular, can be applied to an MRAM (Magnetic Random Access Memory) device.

It is manufacturing process sectional drawing which showed one Example which concerns on the formation method of the alignment mark of this invention. It is manufacturing process sectional drawing which showed one Example which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Example which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Example which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Example which concerns on the manufacturing method of the semiconductor device of this invention. 1 is a schematic cross-sectional view showing an embodiment of a semiconductor device according to the present invention. It is a schematic structure sectional view showing the example of composition of the conventional MRAM. It is manufacturing process sectional drawing which shows the formation method of a copper wiring and a copper plug.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Insulating film, 12 ... Recessed part, 13 ... Recessed part, 18 ... Lower layer pattern, 19 ... Alignment mark, 21 ... Film containing metal film

Claims (5)

Formation of an alignment mark used for alignment with a lower layer pattern than a film including a metal film when patterning a film including a metal film formed on the entire surface of a substrate having an insulating film formed on the surface In the method
The lower layer pattern to be aligned when patterning the film including the metal film is formed by being embedded in a recess formed in the insulating film, and at the same time, in another recess formed in the insulating film than the surface of the insulating film. An alignment mark forming method comprising: forming an alignment mark in a state where at least a part thereof is depressed in the same layer as the lower layer pattern. The method for forming an alignment mark according to claim 1, wherein the film including the metal film is formed by transferring a depression of the alignment mark. Forming a first conductive portion in the first insulating film formed on the substrate in a state where an upper surface thereof is exposed;
Forming a second insulating film covering the first conductive portion on the first insulating film;
Forming a connection hole leading to the first conductive portion in the second insulating film and forming a recess from the second insulating film to the first insulating film;
Forming a conductive film on the second insulating film so as to fill the connection hole and at least partially lower the surface of the second insulating film in the recess;
The conductive film on the second insulating film is removed to form a second conductive portion with the conductive film embedded in the connection hole, and at least a part of the conductive film is formed in the recess in the second portion. And a step of forming an alignment mark in a state of being lower than the surface of the insulating film. Forming a connection hole leading to the first conductive portion in the second insulating film and forming a recess from the second insulating film to the first insulating film;
Forming a first resist film on the second insulating film, and then forming an opening for forming the connection hole and the recess in the first resist film;
Forming the connection hole and the upper portion of the recess in the second insulating film using the first resist film as an etching mask;
Forming a second resist film on the first resist film, and then forming an opening in the second resist film only on the opening for forming a recess formed in the first resist film;
Forming a recess by extending an upper portion of the recess formed in the second insulating film using the second resist film and the first resist film as an etching mask to the first insulating film;
The method for manufacturing a semiconductor device according to claim 3, comprising: removing the first resist film and the second resist film. A first conductive portion embedded in a first insulating film formed on the substrate;
A second insulating film covering the first conductive portion and formed on the first insulating film;
A second conductive portion connected to the first conductive portion through a connection hole communicating with the first conductive portion formed in the second insulating film;
The second conductive portion is used as an alignment mark at the time of alignment, and is lower than the surface of the second insulating film in a recess formed simultaneously with the connection hole from the second insulating film to the first insulating film. And an alignment mark formed by embedding a conductive film in the same layer as the conductive film constituting the semiconductor device.

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