KR20040099605A - Method of detecting input clock error - Google Patents

Abstract

PURPOSE: A method for detecting an input clock of an LCD device including a liquid crystal layer having dielectric anisotropy is provided to detect an error due to an abnormal input clock such as a non-toggling state or an abnormal high-frequency state by using a signal controller. CONSTITUTION: A fixed clock is received from an oscillator(S10). A first signal of a predetermined period having a predetermined signal level is generated during a predetermined period of fixed clocks(S20). A second signal and a third signal are generated by delaying the first signal according to predetermined periods(S30). After a rising edge of the second signal and after a falling edge of the second signal, a clock synchronous signal synchronized with a first clock of external input signals is generated respectively(S40). A clock counter value is increased according to the clock number of the input clocks when the clock synchronous signal is the predetermined signal level whereas the clock counter is reset when the clock synchronous signal is an opposite signal level to the predetermined signal level(S50). A difference value between the clock counter value and an initial clock counter value is stored into the counter and the previous memorized counter value is stored into the previous counter value when the first signal is the predetermined signal level(S60). An error of the input clock is detected by using a counter value and a previous counter value when the clock synchronous signal is the predetermined signal level(S70).

Description

How to detect input clock error {METHOD OF DETECTING INPUT CLOCK ERROR}

The present invention relates to an input clock error detection method, and more particularly, to an input clock error detection method of a liquid crystal display device.

A general liquid crystal display device includes two display panels and a liquid crystal layer having dielectric anisotropy interposed therebetween. An electric field is applied to the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. Such liquid crystal displays are typical among portable flat panel displays (FPDs) that are easy to carry. Among them, TFT-LCDs using thin film transistors (TFTs) as switching elements are mainly used.

Control signals and image data for driving a TFT-LCD are in most cases transmitted from a computer or a graphics controller to a signal controller of a liquid crystal display in the form of CMOS or low voltage differential signal (LVDS), and data restoration or image processing from the signal controller. After the process, it is converted into CMOS data and transmitted to the data driver of the TFT-LCD.

As such, the TFT-LCD is digitally driven due to its characteristics. The signal controller is a digital logic chip that is digitally driven and is usually composed of an application specific integrated circuit (ASIC). However, in order for the signal controller to operate properly, there should be no problem in the internal logic. Input signals such as accurate clock, horizontal sync signal (H _sync ), and data enable signal (DE) complying with the standard are input. Should be. In particular, the clock functions to synchronize all operations of each component operating in the liquid crystal display, to adjust an operation time for a specific operation, and the like. Therefore, when there is a problem in the input clock input to the signal control unit, the signal control unit may not operate properly, thereby causing a defect in the liquid crystal display screen.

However, when a liquid crystal display is actually used, an abnormal clock may be input due to various causes. Examples of abnormal clocks include clocks that do not toggle, or abnormal high frequency clocks.

An object of the present invention is to provide a method for detecting an abnormal clock when it is input to the signal controller.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a flowchart illustrating an input clock error detection method according to an embodiment of the present invention.

4 is a waveform diagram of various signals according to an embodiment of the present invention.

5 is a waveform diagram of various signals when the input clock MCLK does not toggle.

6 is a waveform diagram of various signals when the input clock MCLK is an abnormal high frequency clock.

In accordance with an aspect of the present invention, there is provided a method for detecting an input clock error, the method comprising: receiving a fixed clock generated from an oscillator and having a predetermined signal level only for a predetermined number of periods of the fixed clock; Generating a first signal of a predetermined period, generating a second signal and a third signal of sequentially delaying the first signal by the predetermined number of periods, after a rising edge and a falling edge of the second signal, respectively Generating a clock synchronizing signal that toggles in synchronization with the first clock of an input clock from an external source; and when the clock synchronizing signal is at a predetermined signal level, a value of a clock counter according to the number of clocks of the input clock Increasing a value and resetting the clock counter when the signal level is opposite to the predetermined signal level. In the case of the signal level, storing the value obtained by subtracting the value of the initial clock counter from the value of the clock counter in the counter value, and storing the previously stored counter value in the previous counter value, and the second signal Detecting an error of the input clock using the counter value and the previous counter value when the signal level is predetermined, wherein the initial clock counter comprises the clock counter while the third signal is the predetermined signal level. Remember the value of.

According to the present invention, the predetermined number of periods is preferably at least two periods.

According to an aspect of the present invention, if the counter value is greater than the previous counter value multiplied by a predetermined first coefficient or the counter value is less than the previous counter value multiplied by a predetermined second coefficient, It is desirable to detect errors.

In addition, the predetermined first coefficient may be 2 and the predetermined second coefficient may be 0.5.

In the present invention, when the counter value is "0", it is preferable to detect an error of the input clock MCLK.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

An input clock error detection method according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver The gray voltage generator 800 connected to the signal generator 500, a signal controller 600 for controlling them, and an oscillator 40 are included.

The liquid crystal panel assembly 300 includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels connected to the plurality of display signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. .

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a data signal line or data for transmitting a data signal. Line D ₁ -D _m . The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel includes a switching element Q connected to a display signal line G ₁ -G _n , D ₁ -D _m , and a liquid crystal capacitor C _LC and a storage capacitor C _ST connected thereto. It includes. The holding capacitor C _ST can be omitted as necessary.

The switching element Q is provided on the lower panel 100, and the control terminal and the input terminal are connected to the gate line G ₁ -G _n and the data line D ₁ -D _m, respectively. The output terminal is connected to the liquid crystal capacitor C _LC and the storage capacitor C _ST .

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _ST is formed by overlapping a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100, and a predetermined voltage such as a common voltage V _com is applied to the separate signal line. Is approved. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front end gate line directly above the insulator.

Meanwhile, in order to implement color display, each pixel must display color, which is possible by providing a red, green, or blue color filter 230 in a region corresponding to the pixel electrode 190. In FIG. 2, the color filter 230 is formed in a corresponding region of the upper panel 200. Alternatively, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

A polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the two display panels 100 and 200 of the liquid crystal panel assembly 300.

The gray voltage generator 800 generates two sets of gray voltages related to the transmittance of the pixel. One of the two sets has a positive value for the common voltage (V _com ) and the other set has a negative value.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to receive a gate signal formed by a combination of a gate on voltage V _on and a gate off voltage V _off from the outside. It is applied to the gate lines G ₁ -G _n and usually consists of a plurality of integrated circuits.

The data driver 500 is connected to the data lines D ₁ -Dm of the liquid crystal panel assembly 300 to select the gray voltage from the gray voltage generator 800 and apply the gray voltage to the pixel as a data signal. Is made of.

The signal controller 600 generates control signals for controlling operations of the gate driver 400 and the data driver 500, and provides the corresponding control signals to the gate driver 400 and the data driver 500.

Next, the display operation of the liquid crystal display will be described in more detail.

The signal controller 600 inputs an input control signal for controlling the RGB image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical sync signal V _sync and a horizontal sync signal. (H _sync ), an input clock MCLK, a data enable signal DE, and the like. The signal controller 600 generates a gate control signal CONT1 and a data control signal CONT2 based on the input control signal, and adjusts the image signals R, G, and B to match the operating conditions of the liquid crystal panel assembly 300. After appropriately processing, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signals R ', G', and B 'are sent to the data driver 500.

The gate control signal CONT1 includes a vertical synchronization start signal STV for indicating the start of output of the gate-on pulse (high period of the gate signal), a gate clock signal CPV for controlling the output timing of the gate-on pulse, and a gate-on pulse. And an output enable signal OE that defines the width of the signal.

The data control signal CONT2 is a load for applying a corresponding data voltage to the horizontal synchronization start signal STH indicating the start of input of the image data R ', G', and B 'and the data lines D ₁ -D _m . Signal LOAD, inverted signal RVS and data that inverts the polarity of the data voltage with respect to common voltage V _com (hereinafter referred to as " polarity of data voltage " by reducing " polarity of data voltage with respect to common voltage "). Clock signal HCLK and the like.

The data driver 500 sequentially receives image data R ′, G ′, and B ′ corresponding to one row of pixels according to the data control signal CONT2 from the signal controller 600, and generates a gray voltage generator ( The image data R ', G', B 'is converted into the corresponding data voltage by selecting the gray voltage corresponding to each of the image data R', G ', and B' among the gray voltages from the 800.

The gate driver 400 applies the gate-on voltage V _on to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n. Turn on the switching element (Q) connected to.

The gate-on voltage V _on is applied to one gate line G ₁ -G _n so that a row of switching elements Q connected thereto is turned on (this period is "1H" or "1 horizontal period). (horizontal period) "and equal to one period of the horizontal sync signal Hsync, the data enable signal DE, and the gate clock CPV], and the data driver 500 converts each data voltage to a corresponding data line D. ₁ -D _m ). The data voltage supplied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q.

In this manner, the gate-on voltages V _{on are} sequentially applied to all the gate lines G ₁ -G _n during one frame to apply data voltages to all the pixels. At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel is opposite to that of the previous frame ("frame inversion). "). In this case, the polarity of the data voltage flowing through one data line may be changed (“line inversion”) within one frame or the polarity of the data voltage applied to one pixel row may be different according to the characteristics of the inversion signal RVS ( "Dot reversal").

Meanwhile, as shown in FIG. 1, the liquid crystal display according to the exemplary embodiment of the present invention includes an oscillator 40 generating a fixed clock osc_clk. The signal controller 600 receives the fixed clock osc_clk from the oscillator 40 to determine whether the input clock MCLK inputted from the external device to the signal controller 600 is abnormal. The oscillator 40 may use an LC oscillator circuit, an RC oscillator circuit, a Wien bridge type oscillator, a crystal oscillator, or the like. Although the oscillator 40 is illustrated as being outside the signal controller 600 in FIG. 1, the signal controller 600 may include the oscillator 40. The fixed clock frequency from the oscillator 40 is selected similar to the frequency of the input clock MCLK.

Next, an input clock error detection method of the liquid crystal display according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4.

3 is a flowchart illustrating a method of detecting an input clock error according to an embodiment of the present invention, and FIG. 4 is a waveform diagram of various signals according to an embodiment of the present invention.

As shown in FIG. 3, the fixed clock osc_clk generated from the oscillator 40 is received (S10).

Next, the first synchronization signal osc_sync1 having a predetermined signal level is generated only during a predetermined number of periods of the fixed clock osc_clk (S20). Here, the predetermined number of periods of the fixed clock osc_clk is preferably at least two periods. This is to prevent an error when generating the clock synchronizing signal clk_sync to be described later as the input clock MCLK toggles. Meanwhile, in step S20, the predetermined signal level may be a low ("L") level or a high ("H") level, but the present embodiment will be described based on the "L" level. The predetermined frequency may be any if the frequency is considerably smaller than the frequencies of the input clock MCLK and the fixed clock osc_clk. For example, if the input clock MCLK is 65 MHz, the predetermined frequency is about 2.5 kHz to 4 kHz.

Next, the first synchronization signal osc_sync1 is sequentially delayed by a predetermined number of cycles in step S20 to generate the second synchronization signal osc_sync2 and the third synchronization signal osc_sync3 (S30). That is, the above-mentioned signal is generated such that the second synchronization signal osc_sync2 falls on the rising edge of the first synchronization signal osc_sync1 and the third synchronization signal osc_sync3 falls on the rising edge of the second synchronization signal osc_sync2. do. Each synchronization signal is shown in FIG.

In each case after the rising edge and the falling edge of the second synchronization signal osc_sync2, a clock synchronization signal clk_sync is toggled in synchronization with the first clock of the input clock MCLK from the outside (S40). ). For example, the clock synchronization signal clk_sync falls on the first rising edge of the input clock MCLK after the falling edge of the second synchronization signal osc_sync2. Thereafter, the clock synchronization signal clk_sync rises on the first rising edge of the input clock MCLK after the rising edge of the second synchronization signal osc_sync2.

When the clock synchronizing signal clk_sync is at a predetermined signal level, the value of the clock counter clk_cnt is increased according to the number of clocks of the input clock MCLK. When the clock synchronizing signal clk_sync is at a predetermined signal level, the clock counter clk_cnt is reset. (S50). Although the predetermined signal level may be either an "H" level or an "L" level, the present embodiment will be described based on the "H" level.

When the first synchronization signal osc_sync1 is at the predetermined signal level as in step S20, that is, at the "L" level, the value obtained by subtracting the value of the initial clock counter start_clk_cnt from the value of the clock counter clk_cnt is countered. The value cnt_value is stored, and the previously stored counter value cnt_value is stored in the previous counter value pre_cnt_value (S60). Here, the initial clock counter start_clk_cnt stores the value of the clock counter clk_cnt while the third synchronization signal osc_sync3 is at the predetermined signal level as in step S20, that is, at the "L" level. The reason for calculating by setting the initial clock counter start_clk_cnt is that if the input clock MCLK does not toggle after the falling edge of the second synchronization signal osc_sync2, the clock synchronization signal clk_sync does not become “L” level. This is because the clock counter clk_cnt is not reset and has a wrong value. Therefore, the value of the clock counter clk_cnt while the third synchronization signal osc_sync3 is at the "L" level is stored in the initial clock counter start_clk_cnt, and the interval is the "L" level of the next period of the first synchronization signal osc_sync1. If the value obtained by subtracting it from the clock counter clk_cnt is stored in the counter value cnt_value, the clock sync signal clk_sync does not become the “L” level, and thus the clock sync clk_cnt is not reset. The correct clock number of the input clock MCLK is stored in the counter value cnt_value within one period.

When the second synchronization signal osc_sync2 is at the predetermined signal level as in step S20, that is, at the "L" level, the counter clock cnt_value and the previous counter value pre_cnt_value are used to determine the input clock MCLK. An error is detected (S70). In step S70, when the counter value cnt_value is larger than the value obtained by multiplying the previous counter value pre_cnt_value by a predetermined first coefficient, it is determined that the input clock MCLK is an error. In other words, the input clock MCLK is an abnormal high frequency clock. In this case, when the predetermined first coefficient is 2, the number of clocks of the input clock MCLK is almost twice or more than the number of normal input clocks. In operation S70, when the counter value cnt_value is smaller than the value obtained by multiplying the previous counter value pre_cnt_value by a predetermined second coefficient, it is determined that an error of the input clock MCLK is obtained. In other words, the input clock MCLK does not normally toggle. Herein, when the predetermined second coefficient is 0.5, the input clock MCLK does not toggle more than half of the normal input clock within one period of the first synchronization signal osc_sync1. Further, even when the counter value cnt_value is " 0 ", it is determined that the input clock MCLK is an error. This is mainly to prepare for the case where the proper counter value pre_cnt_value becomes "0" because the input clock MCLK is not toggled for two or more consecutive periods of the first synchronization signal osc_sync1 and thus an appropriate comparison cannot be performed. . The above mentioned coefficient values are values that can be changed.

A method of detecting an error when the input clock MCLK does not toggle will be described with reference to FIG. 5.

5 is a waveform diagram of various signals when the input clock MCLK does not toggle.

In this example, it is assumed that the clock number of the input clock MCLK normally input during one period of the first synchronization signal osc_sync1 is approximately 16,386 times. Since error is detected using two clocks which are not synchronized, errors of 1 to 2 clocks may occur during counting. However, since the present invention detects a larger range of clock errors, a small number of clock errors is ignored.

First, the first part where the input clock MCLK is normally input will be described. When the signal level of the first synchronization signal osc_sync1 becomes "L", the previously stored counter value cnt_value 16,380 is stored in the previous counter value pre_cnt_value, and the initial clock counter at the value 16,382 of the clock counter clk_cnt. The value 16,380 minus the value 2 of (start_clk_cnt) is stored in the counter value (cnt_value). When the signal level of the second synchronization signal osc_sync2 becomes "L", it is determined whether an error has occurred using the stored counter value cnt_value and the previous counter value pre_cnt_value. Since the counter value cnt_value 16,380 is less than twice the previous counter value pre_cnt_value 16,380, is greater than 1/2 times, and not zero, the input clock MCLK is determined to be normal.

When the clock synchronizing signal clk_sync reaches the "L" level, the clock counter clk_cnt is reset to "0". After that, when the clock synchronizing signal clk_sync reaches the " H " level, the clock counter clk_cnt starts counting again. The value "2" of the clock counter clk_cnt while the signal level of the third synchronization signal osc_sync3 is "L" is stored in the initial clock counter start_clk_cnt.

If only four input clocks MCLK are input after the clock counter clk_cnt is reset and not toggled thereafter, the value of the clock counter clk_cnt is 4 at the next period " L " level of the first synchronization signal osc_sync1 and the initial value is 4. Since the value of the clock counter start_clk_cnt is 2, the counter value cnt_value is 2. Since the previous counter value (pre_cnt_value) is 16,380, the counter value (cnt_value) is less than 1/2 times the previous counter value (pre_cnt_value). Therefore, it is determined that an abnormal input clock MCLK is input.

Next, a method of detecting an error when the input clock MCLK is the abnormal high frequency clock will be described with reference to FIG. 6.

6 is a waveform diagram of various signals when the input clock MCLK is an abnormal high frequency clock.

When the clock synchronization signal clk_sync is normally at the "L" level, the clock counter clk_cnt is reset, the input clock MCLK is input to up to four normally, and then the first synchronization signal osc_sync1 is at the "L" level. It is assumed that the value of the clock counter clk_cnt is 32,862, which is inputted into an abnormal high frequency clock until The value of the initial clock counter start_clk_cnt is 2 as in the above case. Then, the counter value cnt_value becomes 32,860 at the next " L " level of the first synchronization signal osc_sync1 and is greater than twice the previous counter value pre_cnt_value 16,380, thereby determining that an abnormal input clock MCLK has been input. .

The counter value cnt_value described above is a value that changes according to the frequencies of the input clock MCLK and the fixed clock osc_clk, and the values of the variables in the above example are merely arbitrary examples.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, an error can be detected when an abnormal input clock is input to the signal controller, such as when the input clock is not toggled or at an abnormal high frequency.

Claims (5)

Receiving a fixed clock generated from an oscillator, Generating a first signal of a predetermined period having a predetermined signal level only for a predetermined number of periods of the fixed clock; Generating a second signal and a third signal which sequentially delay the first signal by the predetermined number of periods, Generating a clock synchronizing signal that toggles in synchronization with the first clock of an input clock from outside in each case after the rising edge and the falling edge of the second signal, Increasing a value of a clock counter according to the number of clocks of the input clock when the clock synchronization signal is at a predetermined signal level, and resetting the clock counter when the clock synchronization signal is at a signal level opposite to the predetermined signal level; When the first signal is at the predetermined signal level, storing a value obtained by subtracting an initial clock counter value from a value of the clock counter in a counter value, and storing the previously stored counter value in a previous counter value; And Detecting an error of the input clock by using the counter value and the previous counter value when the second signal is at the predetermined signal level. Including, The initial clock counter stores a value of the clock counter while the third signal is at the predetermined signal level. Input clock error detection method. In claim 1, And the predetermined number of periods is at least two periods. The method of claim 1 or 2, An input clock error detection for detecting an error of the input clock when the counter value is greater than the previous counter value multiplied by a predetermined first coefficient or when the counter value is smaller than the previous counter value multiplied by a predetermined second coefficient Way. In claim 3, And the predetermined first coefficient is two and the predetermined second coefficient is 0.5. The method of claim 1 or 2, And detecting the error of the input clock (MCLK) when the counter value is "0".