KR20040093553A - Method for forming metal line of semiconductor device - Google Patents
Method for forming metal line of semiconductor device Download PDFInfo
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- KR20040093553A KR20040093553A KR1020030027467A KR20030027467A KR20040093553A KR 20040093553 A KR20040093553 A KR 20040093553A KR 1020030027467 A KR1020030027467 A KR 1020030027467A KR 20030027467 A KR20030027467 A KR 20030027467A KR 20040093553 A KR20040093553 A KR 20040093553A
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- thin film
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- tungsten
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- 238000000034 method Methods 0.000 title claims abstract description 73
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 18
- 239000002184 metal Substances 0.000 title claims abstract description 18
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 45
- 239000010937 tungsten Substances 0.000 claims abstract description 44
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 42
- 238000000151 deposition Methods 0.000 claims abstract description 29
- 239000010409 thin film Substances 0.000 claims abstract description 26
- 230000008021 deposition Effects 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000010408 film Substances 0.000 claims description 39
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 17
- 238000004140 cleaning Methods 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 9
- 238000005498 polishing Methods 0.000 claims description 6
- 229910008484 TiSi Inorganic materials 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims 2
- 238000005530 etching Methods 0.000 abstract description 4
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 16
- 239000011229 interlayer Substances 0.000 description 13
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 230000004888 barrier function Effects 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000002002 slurry Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76858—After-treatment introducing at least one additional element into the layer by diffusing alloying elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Condensed Matter Physics & Semiconductors (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로서, 보다 상세하게는 미세크기의 텅스텐 비트라인 배선 형성에 있어 텅스텐 CMP공정후 발생되는 배선의 손실을 최소화하기 위해 CVD 텅스텐을 이용하는 반도체소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring of a semiconductor device. More particularly, the metal wiring of a semiconductor device using CVD tungsten in order to minimize the loss of wiring generated after a tungsten CMP process in forming a fine-sized tungsten bit line wiring. It relates to a formation method.
종래기술에 따른 반도체소자의 금속배선 형성방법에 대해 도 1a 내지 도 1j를 참조하여 설명하면 다음과 같다.A method of forming metal wirings of a semiconductor device according to the prior art will now be described with reference to FIGS. 1A to 1J.
도 1a 내지 도 1i는 종래기술에 따른 반도체소자의 금속배선 형성방법을 설명하기 위함 공정별 단면도이다.1A to 1I are cross-sectional views of processes to explain a method of forming metal wirings of a semiconductor device according to the related art.
종래기술에 따른 반도체소자의 금속배선 형성방법은, 도 1a에 도시된 바와 같이, 실리콘기판(11)상에 제1층간절연막(13)을 형성한후 이를 선택적으로 제거하여 상기 실리콘기판(11)의 일부분을 드러나도록하는 플러그콘택홀(15)을 형성한다.In the method of forming a metal wiring of a semiconductor device according to the related art, as shown in FIG. 1A, after forming a first interlayer insulating layer 13 on a silicon substrate 11, the silicon substrate 11 is selectively removed. A plug contact hole 15 is formed to expose a portion of the plug contact hole 15.
그다음, 상기 플러그콘택홀(15)내에 폴리실리콘을 이용한 콘택플러그(17)를 형성한후 전체 구조의 상면에 층간산화막(19)을 증착하여 평탄화시킨다.Next, after forming the contact plug 17 using polysilicon in the plug contact hole 15, the interlayer oxide film 19 is deposited and planarized on the upper surface of the entire structure.
이어서, 도 1b에 도시된 바와같이, 상기 층간산화막(19)상에 비트라인을 형성하기 위해 제1감광막패턴(21)을 형성한다. 이때, 상기 제1감광막패턴(21)은 포토리소 그라피 공정기술에 의해 노광 및 현상공정을 진행을 통해 형성한다.Subsequently, as illustrated in FIG. 1B, a first photoresist layer pattern 21 is formed on the interlayer oxide layer 19 to form a bit line. In this case, the first photoresist layer pattern 21 is formed through an exposure and development process by a photolithography process technology.
그다음, 도 1c에 도시된 바와같이, 상기 제1감광막패턴(21)을 마스크로한 건식식각에 의해 상기 층간산화막(19)을 선택적으로 제거하여 상기 콘택플러그(17) 상면을 노출시키는 트렌치(23)를 형성한다. 이때, 상기 트렌치(23)의 라인폭은 200∼250nm 정도의 CD를 갖는다.Next, as shown in FIG. 1C, a trench 23 which selectively exposes the upper surface of the contact plug 17 by selectively removing the interlayer oxide layer 19 by dry etching using the first photoresist pattern 21 as a mask. ). At this time, the line width of the trench 23 has a CD of about 200 to 250nm.
이어서, 도 1d에 도시된 바와같이, 상기 제1감광막패턴(21)을 제거한후 비트라인의 폭을 조절 즉, 100 nm 이하의 라인을 형성하기 위해 도포성이 우수한 저기압 방식에 의해 상기 트렌치(23)를 포함한 층간산화막(19)표면에 산화막(25)을 증착한다. 이때, 라인폭은 콘택홀 형성시에 세정에 의한 폭의 증가량과 Ti/TiN 구조의 배리어증착 전 세정시 식각되므로써 증가되는 폭을 고려하여 증착하는 두께를 결정한다.Subsequently, as shown in FIG. 1D, the trench 23 is removed by the low pressure method having excellent applicability in order to adjust the width of the bit line after the first photoresist pattern 21 is removed, that is, to form a line of 100 nm or less. The oxide film 25 is deposited on the surface of the interlayer oxide film 19 including (). At this time, the line width is determined in consideration of the increased amount of the width by cleaning at the time of forming the contact hole and the width increased by etching before the deposition of the barrier of the Ti / TiN structure.
그다음, 도 1e에 도시된 바와같이, 상기 산화막(25)상에 실리콘기판과의 콘택홀을 형성하기 위하여 제2감광막패턴(27)을 형성한다.Next, as shown in FIG. 1E, a second photosensitive film pattern 27 is formed on the oxide film 25 to form a contact hole with a silicon substrate.
이어서, 도 1f에 도시된 바와같이, 상기 제2감광막패턴(27)을 마스크로 건식방식에 의해 셀부와 셀주변부에 콘택홀(29a)(29b)을 형성한다. 이때, 상기 콘택홀(29a)은 라인보다 큰 폭을 갖는다.Subsequently, as shown in FIG. 1F, contact holes 29a and 29b are formed in the cell portion and the cell periphery by the dry method using the second photoresist pattern 27 as a mask. In this case, the contact hole 29a has a width larger than that of the line.
그다음, 후속공정에서 Ti/TiN을 증착하기 전에 자연산화막을 제거하기 위하여 세정공정을 실시한다.Next, a cleaning process is performed to remove the native oxide film before depositing Ti / TiN in a subsequent process.
이어서, 도 1g에 도시된 바와같이, 상기 콘택홀(29a)(29b)을 포함한 전체 구조의 상면에 소오스 및 드레인부와의 콘택을 위해 배리어막(31), 즉 Ti/TiN을 증착한후 실리콘기판과의 콘택 저항을 낮추기 위하여 고온 열처리르 실시하여 TiSi2막을형성한다.Subsequently, as illustrated in FIG. 1G, the barrier layer 31, that is, Ti / TiN is deposited on the upper surface of the entire structure including the contact holes 29a and 29b for contact with the source and drain portions. In order to lower the contact resistance with the substrate, a high temperature heat treatment is performed to form a TiSi 2 film.
그다음, 도 1h에 도시된 바와같이, 상기 전체 구조의 상면에 상기 콘택홀 (29a)(29b)을 매립할 정도로 텅스텐박막(33)을 CVD 방식으로 증착한다.Then, as shown in FIG. 1H, the tungsten thin film 33 is deposited by CVD to the extent that the contact holes 29a and 29b are buried in the upper surface of the entire structure.
이어서, 도 1i에 도시된 바와같이, 상기 텅스텐박막(33)을 CMP공정을 통해 선택적으로 제거하여 플러그(33a)(33b)를 형성한다.Subsequently, as shown in FIG. 1I, the tungsten thin film 33 is selectively removed through a CMP process to form plugs 33a and 33b.
그러나, 종래기술에 의하면, 다마신 공정방식에 의한 비트라인 형성방식에 있어서 가장 중요한 프로세스는 Ti/TiN 증착전 세정후에 라인폭을 원하는 정도로 유지시키는 것이다. 10nm 이하의 디램기술에서는 비트라인으로 80∼90nm폭의 기술을 사용한다.However, according to the prior art, the most important process in the bit line formation method by the damascene process method is to maintain the line width to a desired degree after cleaning before Ti / TiN deposition. DRAM technology of less than 10nm uses 80-90nm width as the bit line.
또한, 중요한 것은 CMP균일도를 향상시키는 것인데, 측벽 증착후에 전세정을 실시하면 네거티브 프로파일이 형성되어 이로 인하여 배리어/CVD W 증착후 키 홀(key hole)이 크게 형성된다. 키홀은 CMP 진행시에 과도 폴리싱(over polishing)될 경우 도 2에서와 같이 슬러리(즉, 텅스텐 CMP 슬러리는 H2O2를 포함한다)에 의한 텅스텐의 과도한 식각이 진행되어 안정적인 비트라인 형성이 불가능하다.In addition, it is important to improve the CMP uniformity. When pre-cleaning is performed after the sidewall deposition, a negative profile is formed, which causes a large key hole after the barrier / CVD W deposition. When the keyhole is over polished during CMP, the tungsten is excessively etched by the slurry (ie, the tungsten CMP slurry contains H 2 O 2 ) as shown in FIG. Do.
종래기술에 의하면, CMP 공정의 마진이 적기 때문에 과도 폴리싱이 불가피하게 된다.According to the prior art, excessive polishing is inevitable because the margin of the CMP process is small.
따라서, 플러스 형성시 과도한 폴리싱으로 만족할 신뢰성 있는 라인 형성이 불가능하며, 양산 공정적용이 불가능하다.Therefore, it is impossible to form a reliable line to be satisfied with excessive polishing during the plus formation, and mass production process is impossible.
또한, CMP 공정후 라인 프로파일 및 높이 1800∼3000Å으로 유지되나 H2O2에 의한 텅스텐 배선 공격으로 인한 큰 키홀 문제가 발생한다.In addition, after the CMP process, the line profile and the height are maintained at 1800 to 3000 GPa, but a large keyhole problem occurs due to tungsten wiring attack by H 2 O 2 .
한편, 종래의 스퍼터링방식의 배리어를 증착할 때 발생하는 오버행은 CVD 텅스텐을 증착할 때에 심(seam) 발생을 유발하게 된다.On the other hand, the overhang generated when depositing a conventional sputtering barrier causes seam to be deposited when depositing CVD tungsten.
따라서, 플러그를 형성하기 위해 CMP 공정진행시에 과도폴리싱을 진행하면서 심(seam)부위로 슬러리가 침투해 들어가 텅스텐을 화학적 에칭을 하게 된다.Therefore, the slurry penetrates into the seam while performing the overpolishing during the CMP process to form the plug, thereby chemically etching tungsten.
이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 텅스텐을 이용한 배선 형성시에 텅스텐의 거칠기를 개선시켜 배선의 손실 을 최소화시킬 수 있는 반도체소자의 금속배선 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems of the prior art, to provide a method for forming a metal wiring of a semiconductor device that can minimize the loss of the wiring by improving the roughness of the tungsten when forming the wiring using tungsten. There is a purpose.
도 1a 내지 도 1i는 종래기술에 따른 반도체소자의 금속배선 형성방법을 설명하기 위함 공정별 단면도,1A to 1I are cross-sectional views of processes for explaining a method of forming metal wirings of a semiconductor device according to the prior art;
도 2는 종래기술에 따른 반도체소자의 금속배선 형성시에 과도한 폴리싱시에 슬러리에 의한 텅스텐의 과도 식각이 진행된 상태를 보여 주는 사진,2 is a photograph showing a state in which the excessive etching of tungsten by the slurry during the excessive polishing during the formation of metal wiring of the semiconductor device according to the prior art progressed;
도 3a 내지 도 3j는 본 발명에 따른 반도체소자의 금속배선 형성방법을 설명하기 위한 공정단면도,3A to 3J are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device according to the present invention;
도 4는 본 발명에 따른 반도체소자의 금속배선 형성방법에 있어서, CVD 텅스텐 증착시에 질소량 증가에 따른 거칠기(roughness) 특성을 나타낸 그래프.FIG. 4 is a graph showing roughness characteristics with increasing nitrogen content during CVD tungsten deposition in the method for forming metal wirings of a semiconductor device according to the present invention. FIG.
[도면부호의설명][Description of Drawing Reference]
41 : 실리콘기판 43 : 층간절연막41 silicon substrate 43 interlayer insulating film
45 : 플러그 콘택홀 47 : 콘택플러그45: plug contact hole 47: contact plug
49 : 층간산화막 51 : 제1감광막패턴49: interlayer oxide film 51: first photosensitive film pattern
53 : 트렌치 55 : 산화막53: trench 55: oxide film
57 : 제2감광막패턴 59a, 59b : 콘택홀57: second photoresist pattern 59a, 59b: contact hole
61 : 배리어막 63 : 텅스텐막61 barrier film 63 tungsten film
상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 금속배선 형성방법 은, 반도체기판상에 형성된 제1절연막내에 콘택플러그를 형성하는 단계;According to another aspect of the present invention, there is provided a method of forming a metal wiring of a semiconductor device, the method including: forming a contact plug in a first insulating film formed on a semiconductor substrate;
상기 콘택플러그를 포함한 제1절연막상에 제2절연막을 형성하는 단계;Forming a second insulating film on the first insulating film including the contact plug;
상기 제2절연막상에 트렌치를 형성하는 단계;Forming a trench on the second insulating layer;
상기 트렌치를 포함한 제2절연막상에 산화막을 형성하는 단계;Forming an oxide film on the second insulating film including the trench;
상기 산화막을 선택적으로 패터닝하여 트렌치내에 콘택홀을 형성하는 단계;Selectively patterning the oxide layer to form a contact hole in a trench;
상기 콘택홀을 포함한 산화막상에 텅스텐박막을 형성하되, 상기 텅스텐박막 형성시에 질소(N2)를 선택적으로 첨가하는 단계; 및Forming a tungsten thin film on the oxide film including the contact hole, and selectively adding nitrogen (N 2 ) when the tungsten thin film is formed; And
상기 텅스텐박막을 평탄화시켜 상기 콘택홀내에 텅스텐박막패턴을 형성하는 단계;를 포함하여 구성되는 것을 특징으로한다.Planarizing the tungsten thin film to form a tungsten thin film pattern in the contact hole.
(실시예)(Example)
이하, 본 발명에 따른 반도체소자의 금속배선 형성방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming metal wirings of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3i는 종래기술에 따른 반도체소자의 금속배선 형성방법을 설명하기 위함 공정별 단면도이다.3A to 3I are cross-sectional views of processes to explain a method of forming metal wirings of a semiconductor device according to the related art.
본 발명에 따른 반도체소자의 금속배선 형성방법은, 도 3a에 도시된 바와 같이, 실리콘기판(41)상에 층간절연막(43)을 형성한후 이를 선택적으로 제거하여 상기 실리콘기판(41)의 일부분을 드러나도록하는 플러그콘택홀(45)을 형성한다.In the method of forming a metal wiring of a semiconductor device according to the present invention, as shown in FIG. 3A, a part of the silicon substrate 41 is formed by selectively removing the interlayer insulating layer 43 on the silicon substrate 41 and then removing the interlayer insulating layer 43. To form a plug contact hole 45 to reveal.
그다음, 상기 플러그콘택홀(45)내에 폴리실리콘을 이용한 콘택플러그(47)를 형성한후 전체 구조의 상면에 층간산화막(49)을 증착하여 평탄화시킨다.Next, after forming the contact plug 47 using polysilicon in the plug contact hole 45, the interlayer oxide film 49 is deposited and planarized on the upper surface of the entire structure.
이어서, 도 3b에 도시된 바와같이, 상기 층간산화막(49)상에 비트라인을 형성하기 위해 제1감광막패턴(51)을 형성한다. 이때, 상기 제1감광막패턴(51)은 포토리소 그라피 공정기술에 의해 노광 및 현상공정을 진행을 통해 형성한다.Subsequently, as illustrated in FIG. 3B, a first photoresist layer pattern 51 is formed on the interlayer oxide layer 49 to form a bit line. In this case, the first photoresist layer pattern 51 is formed through an exposure and development process by a photolithography process technology.
그다음, 도 3c에 도시된 바와같이, 상기 제1감광막패턴(51)을 마스크로한 건식식각에 의해 상기 층간산화막(49)을 선택적으로 제거하여 상기 콘택플러그(47) 상면을 노출시키는 트렌치(53)를 형성한다. 이때, 상기 트렌치(53)의 라인폭은 200 ∼250nm 정도의 CD를 갖는다.3C, a trench 53 for selectively removing the interlayer oxide layer 49 by dry etching using the first photoresist layer pattern 51 as a mask to expose an upper surface of the contact plug 47. ). At this time, the line width of the trench 53 has a CD of about 200 to 250nm.
이어서, 도 3d에 도시된 바와같이, 상기 제1감광막패턴(51)을 제거한후 비트라인의 폭을 조절 즉, 100 nm 이하의 라인을 형성하기 위해 도포성이 우수한 저압 증착 방식에 의해 상기 트렌치(53)를 포함한 층간산화막(49)표면에 산화막(55)을 증착한다. 이때, 라인폭은 Ti/TiN 구조의 배리어증착 전 세정공정시에 식각되는 양을 고려하여 증착해야 한다. 또한, 플로파일은 위쪽 부분이 다소 라운딩되게 형성 한다. 그리고, 상기 산화막(55)의 두께는 850∼2000 Å정도로 한다.Subsequently, as illustrated in FIG. 3D, the trench may be removed by the low pressure deposition method having excellent coating property in order to adjust the width of the bit line, that is, to form a line of 100 nm or less after removing the first photoresist pattern 51. An oxide film 55 is deposited on the surface of the interlayer oxide film 49 including 53. At this time, the line width should be deposited in consideration of the amount to be etched during the cleaning process before the deposition of the barrier of the Ti / TiN structure. In addition, the flow pile is formed so that the upper portion is somewhat rounded. The oxide film 55 is about 850 to 2000 micrometers thick.
그다음, 도 3e에 도시된 바와같이, 상기 산화막(55)상에 실리콘기판과의 콘택 홀을 형성하기 위하여 제2감광막패턴(57)을 형성한다.Next, as shown in FIG. 3E, a second photosensitive film pattern 57 is formed on the oxide film 55 to form a contact hole with a silicon substrate.
이어서, 도 3f에 도시된 바와같이, 상기 제2감광막패턴(57)을 마스크로 건식 방식에 의해 셀부와 셀주변부에 콘택홀(59a)(59b)을 형성한다. 이때, 상기 콘택홀은 라인보다 큰 폭을 갖는다.Subsequently, as shown in FIG. 3F, contact holes 59a and 59b are formed in the cell portion and the cell peripheral portion by a dry method using the second photoresist pattern 57 as a mask. In this case, the contact hole has a width larger than that of the line.
그다음, 후속공정에서 Ti/TiN을 증착하기 전에 자연산화막을 제거하기 위하여 세정공정을 실시한다. 이때, 트렌치의 라인 폭은 증가되며, 라인 프로파일은 항아리 모양으로 형성된다. 또한, Ti/TiN은 라인폭을 고려하여 측벽의 스텝커버리지 (side wall step coverage)가 가장 나쁜 방식을 선택해야 하며, 오버행을 가장 적게 할 수 있는 방식을 선택한다.Next, a cleaning process is performed to remove the native oxide film before depositing Ti / TiN in a subsequent process. At this time, the line width of the trench is increased, and the line profile is formed in a jar shape. In addition, Ti / TiN should select a method having the worst side wall step coverage in consideration of the line width, and select a method that can minimize the overhang.
이어서, 도 3g에 도시된 바와같이, 상기 콘택홀(59a)(59b)을 포함한 전체 구조의 상면에 소오스 및 드레인부와의 콘택을 위해 배리어막(61), 즉 Ti/TiN을 증착한후 실리콘기판과의 콘택 저항을 낮추기 위하여 고온 열처리를 실시하여 TiSi2막을 형성한다. 이때, 상기 열처리하는 동안 Ti/TiN박막에 미세한 크랙이 형성되며, 이것이 CVD W 증착시 WF6에 의한 어택(attack) 및 후속 열처리시에 W과 Si의 반응 방지를 위한 배리어 역할을 할 수 없어 TiN을 재증착하므로써 배리어를 강화 시켜 준다. 또한, 상기 열처리공정은 500∼900℃온도 및 N2, NH3분위기하에서 10∼90초동안 진행한다. 또한, 상기 Ti/TiN막은 진공이 깨지지 않은 상태에서 인시튜로 증착하며, Ti/TiN막 또는 TiN막은 20∼200Å두께 정도로 증착한다.Subsequently, as shown in FIG. 3G, the barrier layer 61, that is, Ti / TiN is deposited on the upper surface of the entire structure including the contact holes 59a and 59b for contact with the source and drain portions. In order to lower the contact resistance with the substrate, a high temperature heat treatment is performed to form a TiSi 2 film. At this time, fine cracks are formed in the Ti / TiN thin film during the heat treatment, which may not serve as a barrier for preventing the reaction between W and Si during attack and subsequent heat treatment by WF 6 during CVD W deposition. By re-depositing, the barrier is strengthened. In addition, the heat treatment process is performed for 10 to 90 seconds at 500 ~ 900 ℃ temperature and N 2 , NH 3 atmosphere. In addition, the Ti / TiN film is deposited in situ in a vacuum-free state, and the Ti / TiN film or TiN film is deposited at a thickness of 20 to 200 kPa.
그다음, 도 3h에 도시된 바와같이, 상기 전체 구조의 상면에 상기 콘택홀 (59a)(59b)을 매립할 정도로 텅스텐박막(63)을 CVD 방식으로 증착한다. 이때, CVD 텅스텐의 거칠기(roughness)를 향상시키기 위해 CVD 텅스텐 증착시에 N2를 일정량 첨가하여 플러그에 심(seam)을 최소화한다. 단, N2첨가는 증착초기에만 공급하여 과도하게 텅스텐의 스트레스가 증가하는 것을 막아준다. 이때, N2첨가 유량은 100∼4000 sccm 정도가 가장 바람직하다. 또한, CVD 텅스텐박막의 증착두께는 4000Å 정도가 된다. 특히, 상기 텅스텐박막은 N2첨가시의 1차 증착시에 200∼500Å 두께를 증착한후 2차 증착시에는 1000∼4000Å 두께로 증착하는 것이 바람직하다.Then, as shown in FIG. 3H, the tungsten thin film 63 is deposited by CVD to the extent that the contact holes 59a and 59b are buried in the upper surface of the entire structure. At this time, in order to improve the roughness of the CVD tungsten, a certain amount of N 2 is added during CVD tungsten deposition to minimize the seam in the plug. However, the addition of N 2 is supplied only at the beginning of the deposition to prevent excessive increase in stress of tungsten. At this time, the N 2 addition flow rate is most preferably about 100 to 4000 sccm. In addition, the deposition thickness of the CVD tungsten thin film is about 4000 kPa. In particular, the tungsten thin film is preferably deposited at a thickness of 200 to 500 kPa during the first deposition when N 2 is added and then at a thickness of 1000 to 4000 kPa during the second deposition.
이어서, 도 3i에 도시된 바와같이, 상기 텅스텐박막(53)을 CMP공정을 통해 선택적으로 제거하여 플러그(63a)(63b)를 형성한다.Subsequently, as shown in FIG. 3I, the tungsten thin film 53 is selectively removed through a CMP process to form plugs 63a and 63b.
그다음, 후속 O2분위기하에서의 열처리시에 W의 산화방지를 위하여 CVD 방식의 Si3N4를 증착하여 O2확산방지막(미도시)을 증착한다.Then, in order to prevent oxidation of W during the heat treatment in the subsequent O 2 atmosphere, CVD-type Si 3 N 4 is deposited to deposit an O 2 diffusion barrier (not shown).
도 4는 텅스텐 증착시에 N2첨가량에 따른 CVD 텅스텐의 거칠기의 변화를 나타낸 그래프인데, 도면에서와 같이, N2량이 증가하면서 텅스텐의 거칠기 (roughness)가 개선되는 것을 확인할 수가 있다. 따라서, 텅스텐증착시에 N2를 첨가해 주므로써 거칠기를 개선할 수 있고, 심(seam)을 최소화할 수 있으므로써 H2O2에 의한 화학적 식각을 방지할 수 있는 것이다.4 is a graph showing a change in the roughness of CVD tungsten according to the amount of N 2 added during tungsten deposition, as shown in the figure, it can be seen that the roughness (roughness) of the tungsten is improved as the N 2 amount increases. Therefore, by adding N 2 at the time of tungsten deposition, the roughness can be improved, and the seam can be minimized, thereby preventing chemical etching by H 2 O 2 .
상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 금속배선 형성방법에 의하면, 다마신 방식에 의해 비트라인 형성방법에서 CMP 공정에 의한 프로세스 의존성을 줄일 수 있다. 즉, 정확한 폴리싱 뿐만 아니라 과도 폴리싱 상태의 CMP 프로세스에서도 안정적인 비트라인을 형성할 수 있어 공정 창(process window)을 넓힐 수 있다.As described above, according to the method for forming the metal wiring of the semiconductor device according to the present invention, the process dependency by the CMP process can be reduced in the bit line forming method by the damascene method. That is, stable bit lines can be formed not only in accurate polishing but also in a CMP process in an over-polishing state, thereby widening a process window.
또한, 기존 CVD 텅스텐의 공정조건에 N2를 첨가하므로써 기존 공정의 문제점, 즉 텅스텐의 거칠기가 개선된다.In addition, by adding N 2 to the process conditions of the conventional CVD tungsten, the problem of the existing process, that is, the tungsten roughness is improved.
그리고, 라인과 플러그 사이의 심(seam) 또는 보이드(void)를 제거하므로서 배선의 신뢰성을 높일 수 있다.In addition, the reliability of the wiring can be improved by removing the seam or void between the line and the plug.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
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| KR100808369B1 (en) * | 2006-10-17 | 2008-02-27 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
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| US9202794B2 (en) | 2012-04-19 | 2015-12-01 | Samsung Electronics Co., Ltd. | Pad structure of a semiconductor device, method of manufacturing the pad structure and semiconductor package including the pad structure |
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| KR100606539B1 (en) * | 2004-12-22 | 2006-08-01 | 동부일렉트로닉스 주식회사 | Method of fabricating metal layer of semiconductor device |
| KR100808369B1 (en) * | 2006-10-17 | 2008-02-27 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
| KR100883566B1 (en) * | 2008-04-28 | 2009-02-13 | (주)포테이토밸리 | The healthy and funtional foods for the cancer prevention of using new type of solanum tuberosum l cv. gogu valley |
| US9202794B2 (en) | 2012-04-19 | 2015-12-01 | Samsung Electronics Co., Ltd. | Pad structure of a semiconductor device, method of manufacturing the pad structure and semiconductor package including the pad structure |
| US9570411B2 (en) | 2012-04-19 | 2017-02-14 | Samsung Electronics Co., Ltd. | Pad structure of a semiconductor device, method of manufacturing the pad structure and semiconductor package including the pad structure |
| US9847297B2 (en) | 2014-12-17 | 2017-12-19 | SK Hynix Inc. | Electronic device and method for fabricating the same |
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