KR20040084234A - Method of manufacturing a semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to minimize the resistance of a word line and the overlap between a gate electrode and a source/drain by widening the width of the gate electrode. CONSTITUTION: A floating gate electrode(114) is formed on a semiconductor substrate(110). A dielectric film(116), the first conductive layer(118), the second conductive layer(120) and a hard mask layer are sequentially formed on the floating gate electrode. A hard mask pattern(122) is formed by patterning the hard mask layer. A spacer(130) is formed to widen the effective channel length at both sidewalls of the hard mask pattern. A stacked gate electrode is then formed by etching the second and first conductive layer, the dielectric film and the floating gate electrode using the hard mask pattern with the spacer as a mask.

Description

Method of manufacturing a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device capable of securing a sufficient gate margin.

As the design rule is reduced, the cell size is reduced, and the chip size is increased, the gate length is reduced in the NAND flash cell. Word Line) There are many difficulties to secure resistance. As the gate length decreases, the effective channel length (Leff) is reduced together to secure the effective channel length, and in the case of the gate line, the sheet resistance should not be changed but tungsten silicide is used as the word line metal. This causes a problem in that the word line resistance rapidly increases at a sub 100 nm.

The above problem causes a problem in that the specification of the random access time at which the first data comes out of the NAND flash memory cannot be satisfied. In addition, Noah flash is the biggest reason for the lack of lead margin. This places a lot of constraints on NAND flash cell shrinkage and chip performance.

In the case of the offset spacer, which is a technique for securing the effective channel length, the effective channel length can be secured. However, since it has the same characteristics as conventional techniques in terms of wordline resistance, it cannot be satisfied in terms of random access time. By using another circuit, a problem arises in that the area of the chip is increased.

Accordingly, in order to solve the above problems, the present invention is to first pattern a hard mask layer for forming a gate of a semiconductor device, and then form spacers on the sidewalls thereof, thereby widening the width of the gate electrode to be patterned by a subsequent process. Fabrication of semiconductor devices capable of minimizing resistance, minimizing overlap of gate and source / drain, securing effective channel length, increasing productivity and realizing uniform floating gate The purpose is to provide a method.

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

<Explanation of symbols for the main parts of the drawings>

110 semiconductor substrate 112 tunnel oxide film

114, 118, 120: conductive film 116: dielectric film

122: hard mask film 130: spacer

Forming a floating gate electrode on the semiconductor substrate having the device isolation film according to the present invention; sequentially forming a dielectric film, a first conductive film, a second conductive film, and a hard mask film on the entire structure; The second conductive layer through patterning, forming a spacer on the sidewall of the patterned hard mask layer to extend an effective channel length of the device, and etching the hard mask layer on which the spacer is formed as an etch mask; And etching the first conductive layer, the dielectric layer, and the floating gate electrode to form a gate electrode.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Referring to FIG. 1A, a device isolation layer (not shown) is formed on a semiconductor substrate 110 in which a cell region A, a high voltage device region B, and a low voltage device region B are defined. The implantation process is performed to form wells (not shown) in the semiconductor substrate 110.

After the tunnel oxide film 112 and the first conductive film 114 are deposited on the semiconductor substrate 110, the tunnel oxide film 112 and the first conductive film 114 are patterned to form a floating gate electrode. The dielectric film 116, the second conductive film 118, the third conductive film 120, and the hard mask film 122 are sequentially formed on the entire structure where the floating gate electrode is formed.

Specifically, a pad oxide film (not shown) and a pad nitride film (not shown) are sequentially formed on the semiconductor substrate 110. After the photoresist is deposited on the entire structure, a photolithography process using a photoresist mask is performed to form a photoresist pattern (not shown). A trench (not shown) is formed by performing a STI (Sallow Trench Isolation) etching process using the photoresist pattern and the pad nitride layer as an etching mask, and a device isolation layer is formed by filling the trench using an insulating layer. As a result, the semiconductor substrate 110 is separated into an active region and an inactive region (ie, an isolation region) by the isolation layer.

In the present exemplary embodiment, a trench (not shown) is formed by etching the semiconductor substrate 110 to a depth of 2000 to 3000 mA to ensure a leakage current margin of the cell. An oxidation process is performed to compensate for the damage of the etching for forming the trench, and a wet or dry oxidation process is performed at a temperature between 750 and 1000 ° C. An HDP (High Density Plasma) oxide film is deposited on the entire structure where the trench is formed so that voids are not formed in the trench at a thickness of 3000 to 7000 Å. After removing the HDP oxide film formed on the pad nitride film, the remaining pad nitride film and the pad oxide film are etched to form a device isolation film protruding over the semiconductor substrate. The HDP oxide film formed on the pad nitride film is removed by a CMP process. The present invention is not limited thereto, and the device isolation layer may be formed through various types of processes. For example, the device isolation film may be formed using only the photosensitive film pattern without depositing the above-described pad oxide film and pad nitride film.

In this case, the pad oxide layer may be used as a screen oxide layer to serve as a buffer layer when implanting ions for subsequent well formation by remaining a portion thereof without etching the pad oxide layer completely. After forming an ion implantation mask (not shown) that opens the region where the semiconductor device is to be formed, the well may be formed in the exposed region of the semiconductor substrate 110 through an ion implantation process. In this case, in order to form the PMOS transistor and the NMOS transistor, n wells and p wells must be formed, respectively, so that n wells and p wells are formed through two ion implantation mask formation processes and two ion implantation processes, respectively.

The above-described conditions of the ion implantation process are not limited thereto, and the ion implantation is performed under such a condition that a junction is formed on the surface of the semiconductor substrate 110 so as not to cause other leakage currents and leakage between the well and the junction does not occur. do. In addition, the photoresist pattern may be formed to implant ions only in a predetermined region.

The present invention is not limited thereto, and a screen oxide film (not shown) may be deposited on the semiconductor substrate 110 to serve as a buffer layer for suppressing crystal defects or surface treatment and implanting ions, followed by ion implantation.

In addition, the ion implantation process for adjusting the threshold voltage may be performed using various process methods and techniques.

In addition, ion implantation for well or threshold voltage adjustment may be performed first, and then a device isolation layer may be formed.

A tunnel oxide film 112 is formed on the entire structure in which the device isolation film is formed, and a polysilicon film is formed using the first conductive film 114. The first conductive layer 114 is deposited to a thickness of 1000-1500 Å to remove residues during subsequent gate etching.

A planarization process using the HDP oxide film as a stop film is performed to isolate the floating gate electrodes.

The floating gate electrode may be formed by patterning the tunnel oxide layer 112 and the first conductive layer 114 through a patterning process using the mask for the floating gate electrode.

A dielectric film 116 having an oxide / nitride / oxide (ONO) structure is formed on the semiconductor substrate 110 on which the floating gate electrode is formed. The present invention is not limited thereto, and various types of dielectric films 116 used in the manufacture of semiconductor devices may be used. For example, an ONON structure dielectric film can be used. The second conductive film 118, the third conductive film 120, and the hard mask film 122 are sequentially formed on the dielectric film 116.

The second conductive film 118 is formed using polysilicon, but is formed to have a thickness of 1000 to 2000 Å to prevent cracking of the third conductive film 120 on the second conductive film 118. A tungsten silicide film is used as the third conductive film 120. The present invention is not limited thereto, and a double structure of a polysilicon film doped with the second conductive film 118 and an undoped polysilicon film may be used to improve adhesion between the second conductive film 118 and the third conductive film 120. Form. The doped polysilicon film is formed to a thickness of 500 to 1800 GPa, and the undoped polysilicon film is formed to a thickness of 100 to 500 GPa. The hard mask layer 122 is formed using at least one of a nitride layer-based material layer and an oxide layer-based material layer. The hard mask film 122 is formed to a thickness of 700 to 2500Å by CVD.

The films described above may be formed using various types of deposition methods used in the manufacture of semiconductor devices. In addition, an anti-reflection film may be formed on the hard mask layer 122 using an arcoxynitride, which may serve as a barrier layer for scattering of the gate mask and a self-aligned etch (SAE). .

1B and 1C, the hard mask layer 122 is patterned through a patterning process using a mask for a control gate. A spacer 130 is formed on the sidewall of the patterned hard mask layer 122 to secure an effective channel length margin and a word line resistance margin.

Specifically, a photoresist film is coated on the hard mask film 122, and then a photolithography process using a mask for a control gate is performed to form a photoresist pattern (not shown). The hard mask film 122 is etched by performing an etching process using the photoresist pattern as an etching mask. At this time, the patterned hard mask layer 122 is formed like a target control gate pattern.

A first insulating layer (not shown) for a spacer is formed on the semiconductor substrate 110 on which the patterned hard mask layer 122 is formed. A spacer is formed on the sidewall of the hard mask film 122 by etching the first insulating film for the spacer in a region other than the first insulating film for the spacer on the sidewall of the hard mask film 122. The spacers may be formed using at least one of a nitride film-based material film and an oxide film-based material film. For example, LP-TEOS is formed to a thickness of 50 to 250 kHz with the first insulating film for spacers. In addition, although the spacers 130 may be formed on the sidewalls of the hard mask film 122 using various methods and techniques, in this embodiment, the spacers 130 are formed by depositing an insulating film and then performing an entire surface etching. The word line resistance formed by the process can be reduced, the overlap of gate and source / drain can be reduced, the effective channel length can be secured, and the cell size can be reduced. In addition, when the third conductive layer 120 is etched in a subsequent process, the first insulating layer for the spacer is etched to form the spacer 130 on the sidewall of the hard mask layer 122, and at the same time, the third conductive layer 120 is formed. Can be patterned

Referring to FIG. 1D, a gate electrode is formed by performing an etching process using the hard mask layer 122 having the spacers 130 formed on the sidewalls as an etching mask. Specifically, the third conductive film 120, the second conductive film 118, the dielectric film 116, and the floating gate electrode (the first conductive film 114 and the tunnel oxide film 112) are sequentially etched to control the gate. And a floating gate electrode are stacked to form a gate electrode. As a result, a gate electrode having an effective channel length (T2 in FIG. 1D) that is wider than the conventional effective channel length (T1 in FIG. 1D) may be formed. By controlling the thickness of the spacer 130 on the sidewall of the hard mask layer 122, the effective channel length can be adjusted, and a word line resistance margin can be secured.

The third conductive layer 120 is formed by an etching process using the dielectric layer 116 having the ONO structure as the first etch stop layer and using the hard mask layer 122 having the spacer 130 formed on the sidewall as an etch mask. The second conductive film 118 is etched. The dielectric film 116, the first conductive film 114, and the tunnel oxide film 112 having the ONO structure are sequentially etched. The etching method and order may be variously performed using the method and order used to manufacture the semiconductor device.

When the second and third conductive layers 118 and 120 are etched, damage to the tungsten silicide layer used as the third conductive layer 120 may occur, so it is necessary to control the ratio of the source / drain space well. That is, in order to prevent damage to the third conductive layer 120, the gate electrode is etched using Hbr and O ₂ . The damage of the third conductive film 120 is closely related to the IR drop (voltage drop due to current and resistance) related to the speed of the read operation of the device. When etching the dielectric film 116 and the first conductive film 114, when the dielectric film 116 proceeds to the B / T step (Break Through Step) of the first conductive film 114, care should be taken in directional etching. In addition, when the first conductive layer 114 is etched, the phenomenon in which the first conductive layer 114 remains in the moat region should be prevented.

The oxidation process may be performed to compensate for the damage occurring during the etching for forming the gate electrode and to secure the retention characteristic, which is an important characteristic of the flash device. In addition, it is possible to compensate for the damage due to etching by performing a heat treatment process using a furnace or rapid heat treatment equipment instead of the oxidation process.

By the above-described method, gate electrodes for flash memory cells are formed in the cell region A, and gate electrodes for high voltage elements and low voltage elements are formed in the high voltage element region B and the low voltage element region C. FIG. The present invention is not limited thereto, and gate electrodes can be formed simultaneously in the cell region A, the high voltage element region B, and the low voltage element region, and different gate oxide films (tunnel oxide films) are formed in the respective regions. Next, the same process may be performed to form a gate electrode. In addition, gate electrodes may be formed in respective regions through different processes.

Next, an ion implantation process is performed to form a cell junction (not shown) in the cell region A through a subsequent process. A gate spacer (not shown) is formed on sidewalls of the gate electrodes of the high voltage device region B and the low voltage device region C, and then a junction (not shown) for the high voltage device and the low voltage device is formed through ion implantation.

Specifically, cell junctions are formed on the semiconductor substrates on both sides of the cell gate electrode by performing ion implantation using elements of Group 3 or Group 5 elements. In this embodiment, arsenic (As) is implanted at a dose of 2E14 to 2E15 to form a cell junction. In addition, 5KeV-40KeV is used as ion implantation energy. To minimize the drain disturbance (punch through) phenomenon and drain through the ion implantation for the cell junction. A second insulating layer for the spacer is deposited on the high voltage device region B and the low voltage device region C, and then a front surface etching process is performed to form gate spacers on sidewalls of the gate electrodes for the high voltage device and the low voltage device. Ion implantation using elements of Group 3 or Group 5 is performed to form junctions for the high voltage element and the low voltage element on the semiconductor substrates on both sides of the gate electrode for the high voltage element and the low voltage element. The second insulating film for the spacer is formed using at least one of a nitride film-based material film and an oxide film-based material film. That is, the second insulating film for the spacer may be formed using a high temperature oxide film (HTO) having a thickness of 50 to 300 kPa and a nitride film having a thickness of 400 to 1000 kPa, or a nitride film having a thickness of 400 to 1500 kPa.

The present invention is not limited thereto, and various types of gate spacers may be formed on the sidewalls of the gate electrodes through various types of process technologies and process steps, and junctions may be formed. For example, the junction region may be formed in a shape such as LDD and DDD.

A third insulating film (not shown) for a self-aligned contact process and a fourth insulating film (not shown) for interlayer insulation between the lower element and the upper metal wiring are formed on the entire structure.

Specifically, in the third insulating film, a nitride film having a thickness of 100 to 300 Å is formed along the level of the entire structure for the margin of the contact and the gate to be formed by the subsequent process and the margin of the contact and the active region. The fourth insulating layer is used as a pre metal dielectric layer (P.MD), and at least one of boron phosphorus silicate glass (PBSG), phosphorus silicate glass (PSG), and high density plasma (HDP) is used. Form.

In order to activate the planarization and junction of the fourth insulating film, an annealing process is performed at high temperature using a rapid heat treatment equipment, and then a planarization process using chemical mechanical polishing is performed to form contact holes for plugs. The annealing step is carried out at a temperature of 950 ° C or higher.

Plug contact holes (not shown) are formed under the patterning of the third and fourth insulating films. The contact hole is filled with a conductive material to form a plug. Bit lines are formed on the plugs to form flash memory cells.

Specifically, after the photoresist is coated on the planarized fourth insulating film, a photolithography process is performed using a contact hole mask to form a photoresist pattern for exposing the junction part. An etching process using the photoresist pattern as an etching mask is performed to remove the fourth and third insulating layers to form contact holes for plugs. The present invention is not limited thereto, and not only the junction but also the gate contact region may be etched together. The etching process for forming a contact hole for a plug includes an etching step having no etch selectivity between the nitride film and an oxide film, an etching step having an etch selectivity between the nitride film and the oxide film, an etching step for removing by-products generated during etching of the fourth insulating film, and 3 etching is performed to remove the insulating film.

In order to compensate for the damage of the etching process, plug ion implantation is performed, and an annealing process is performed within a range capable of activating without changing the shape of the plug contact hole. That is, in order to prevent damage to the semiconductor substrate generated during the etching process, the plug ion implantation is performed using Ph which is well activated. After the formation of the contact hole, the annealing process uses a rapid annealing at 800 to 900 ° C. to prevent activation of the plug ion implantation and change of contact etching (PBSG Re-Flow), thereby improving barrier metal deposition power in a subsequent process, and preventing contact hole deposition. When buried, suppress the occurrence of visible. Instead of rapid annealing can be carried out using a tube of 650 to 900 ℃.

A barrier first metal film (not shown) and a second metal film (not shown) are deposited along the entire structure to fill a plug contact hole, and then an etch back and a CMP process are performed to form a barrier agent on the fourth insulating film. The first metal film and the second metal film are removed to form a metal plug. The barrier first metal film is formed using 50 to 300 microns thick Ti and 200 to 800 microns thick TiN of CVD or PVD to improve adhesion to contacts during deposition. Ti and TiN can be used at the same time, respectively.

After depositing a third metal film (not shown) on the semiconductor substrate on which the plug is formed, the third metal film is patterned to form a bit line. The present invention is not limited thereto, and a bit line trench may be formed by depositing a fifth insulating film (not shown) on the entire structure, and then patterning the fifth insulating film to form a bit line trench and filling the trench with a metal material. The barrier first metal film, the second metal film, and the third metal film may be formed of various kinds of conductive metal films, but in this embodiment, at least one of tungsten (W), aluminum (Al), and copper (Cu) may be formed. To form. Also, in the case of NAND flash, no contact is formed in the region between the gates, and the contact is formed in the outer region maintaining a large space. In addition, the contact is made to the floating gate when the gate contact is formed in the high voltage element region and the low voltage element region. Can be formed to form a poly gate.

As described above, the present invention can minimize the resistance of the word line by widening the width of the gate electrode to be patterned by a subsequent process by first patterning a hard mask film for forming the gate of the semiconductor device and then forming a spacer on the sidewall thereof. As a result, random access speeds and margins can be secured in the case of NAND flash, and sufficient margin of lead speed can be secured in the case of NOR flash.

In addition, by minimizing overlap between gate and source / drain, effective channel length can be secured, cell size can be reduced, productivity can be increased by increasing net die, and overall wafer A uniform floating gate can be implemented over.

In addition, the effective channel length can be adjusted to enable cell implementation and various process margins of the next generation of highly integrated flash devices, and can be applied to MOS transistors.

Claims (3)

(a) forming a floating gate electrode on the semiconductor substrate on which the device isolation layer is formed; (b) sequentially forming a dielectric film, a first conductive film, a second conductive film, and a hard mask film on the entire structure; (c) patterning the hard mask layer; (d) forming spacers on the patterned sidewalls of the hard mask layer to extend the effective channel length of the device; And (e) forming a gate electrode by etching the second conductive layer, the first conductive layer, the dielectric layer, and the floating gate electrode through an etching process using the hard mask layer having the spacer as an etch mask. The manufacturing method of the semiconductor element characterized by the above-mentioned. The method of claim 1, wherein step (c) comprises: Applying a photoresist film on the hard mask film; Forming a photoresist pattern by performing a photolithography process using a mask for a gate electrode; Removing the hard mask layer by performing an etching process using the photoresist pattern as an etching mask; And removing the photosensitive film pattern. The method of claim 1, The spacer is a method of manufacturing a semiconductor device, characterized in that at least one of the nitride film-based material film and the oxide film-based material film.