KR20040077010A - Liquid crystal display - Google Patents

Abstract

PURPOSE: An LCD device is provided to remove noise components included in various driving signals or control signals by a filter, and to transmit the signals without noise to an LCD assembly. CONSTITUTION: A signal controller(600) drives an LCD device in an upper part of an LCD assembly(300). A PCB(550) has circuit components including a driving voltage generator(700). The LCD assembly(300) and the PCB(550) are electrically connected through an FPC(Flexible Printed Circuit)(511). A data driver including plural data driving ICs receives plural data signals or various driving signals transmitted from the PCB(550).

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

The present invention relates to a liquid crystal display device.

A general liquid crystal display (LCD) includes a liquid crystal layer having dielectric anisotropy interposed between two display panels. The desired image is obtained by applying an electric field to the liquid crystal layer and adjusting the intensity of the electric field to adjust the transmittance of light passing through the liquid crystal layer. Such liquid crystal displays are typical among portable flat panel displays (FPDs) that are easy to carry. Among them, TFT-LCDs using thin film transistors (TFTs) as switching elements are mainly used.

In the display panel on which the thin film transistor is formed, a plurality of gate lines and data lines are formed in row and column directions, respectively, and pixel electrodes connected to the gate lines and data lines are formed through the thin film transistors. The thin film transistor controls the data signal transmitted through the data line according to the gate signal transmitted through the gate line and transmits the data signal to the pixel electrode. The gate signal is generated by combining a plurality of gate driving integrated circuits (ICs) supplied with the gate on voltage V _on and the gate off voltage V _off generated by the driving voltage generator according to control from the signal controller. The data signal is obtained by converting the gradation signal from the signal controller into a plurality of data driving ICs into analog voltages.

The signal control unit and the driving voltage generator are usually provided on a printed circuit board (PCB) located outside the display panel, and the driving IC is a flexible printed circuit (FPC) board located between the PCB and the display panel. It is mounted on the top. Two PCBs are usually placed in this case, one above and one left of the display panel. The left one is called a gate PCB and the top one is called a data PCB. A gate driver IC is positioned between the gate PCB and the display panel, and a data driver IC is positioned between the data PCB and the display panel, and receives signals from the corresponding PCB.

However, instead of using a gate PCB, only a data PCB can be used. In this case, the gate-side FPC substrate and the gate driver IC thereon may be left as it is. In this case, in order to transfer signals from the signal control unit and the driving voltage generator located in the data PCB to all the gate driver ICs, signal lines are separately formed on the data side FPC board and the display panel, and signal lines are also formed on the gate side FPC board. To allow the signal to be transmitted. In addition, the gate driver IC may be directly mounted on the liquid crystal panel assembly without using the gate side FPC substrate, and the data driver IC may also be directly mounted on the liquid crystal panel assembly (chip on glass). When the gate driver IC is mounted directly on the liquid crystal panel assembly, signal lines need only be made on the data side FPC substrate and the display panel to transfer signals to all the gate driver ICs. In addition, even when the data driver IC is mounted directly on the liquid crystal panel assembly, the data driver IC receives all signals through the data side FPC board.

In order to reduce the cost or reduce the size of the liquid crystal display, all signals necessary for the gate driver IC are supplied from the data PCB through the data side FPC board using only the data PCB (hereinafter referred to as a "montblanc structure"). Is expanding. Since the plurality of driving signal lines in the Mont Blanc structure are connected from the data PCB to the corresponding gate driving ICs, their lengths become longer. Accordingly, the length of the driving signals is also long, so that these signals are exposed to noise or interference of neighboring signals, and thus electromagnetic interference (EMI) is generated. However, since the Montblanc structure is not a general structure of the liquid crystal display device, there are no noise countermeasures or EMI countermeasures for such a structure. In particular, since the driving signal lines serve as antennas in a specific frequency band according to the length of the driving signal lines, a phenomenon of radiating many high frequency noise components occurs.

Therefore, the technical problem to be achieved by the present invention is to remove the noise of the signal applied to the driving IC of the liquid crystal display device.

Another technical problem to be achieved by the present invention is to reduce EMI.

1 is a conceptual diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a block diagram schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

A liquid crystal display according to an embodiment of the present invention

A liquid crystal panel having a plurality of first signal lines, and

A printed circuit board having at least one element for generating a plurality of signals and a plurality of second signal lines for respectively transmitting the plurality of signals from the elements to the plurality of first signal lines;

The printed circuit board further includes a plurality of filter units connected between the device and the second signal line.

The device may include a signal controller configured to generate at least one signal among the plurality of signals and transmit the signal to at least one filter unit of the plurality of filter units, wherein the plurality of signals are gate clocks generated from the signal controller. Signal, a vertical synchronization start signal, and an output enable signal. Also, in the present invention, the device may include a driving voltage generator, and the plurality of signals may include a power supply voltage and a ground voltage generated from the driving voltage generator.

The filter unit may include a filter including a capacitor and a resistor connected between the signal controller and the first signal line, and a coil and a bead mounted between the driving voltage generator and the first signal line. bead) and at least one capacitor.

Preferably, the power supply voltage is transmitted to the second signal line through a filter including the coil and at least one capacitor, and the ground voltage is transmitted to the second signal line through the grounded bead.

The liquid crystal display of the present invention may further include at least one flexible printed circuit board electrically connected to each other between the liquid crystal panel and the printed circuit board, and the first signal line on the flexible printed circuit board. And a plurality of third signal lines connected to the second signal lines are formed.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A liquid crystal display according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400 connected thereto, and a driving voltage connected to the gate driver 400. A driving voltage generator 700, a data driver 500, a gray voltage generator 800 connected to the data driver 500, and a signal controller 600 for controlling them are included.

The liquid crystal panel assembly 300 includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels connected to the plurality of display signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. .

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a data signal line or data for transmitting a data signal. Line D ₁ -D _m . The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel includes a switching element Q connected to a display signal line G ₁ -G _n , D ₁ -D _m , a liquid crystal capacitor C _lc , and a storage capacitor C _st connected thereto. It includes. The holding capacitor C _st can be omitted as necessary.

The switching element Q is provided on the lower panel 100, and the control terminal and the input terminal are connected to the gate line G ₁ -G _n and the data line D ₁ -D _m, respectively. The output terminal is connected to the liquid crystal capacitor C _lc and the storage capacitor C _st .

The liquid crystal capacitor C _lc has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270 It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the entire surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _st is formed by superimposing a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100, and a predetermined voltage such as a common voltage V _com is applied to the separate signal line. Is approved. However, the storage capacitor C _st may be formed such that the pixel electrode 190 overlaps the front gate line directly above the insulator.

Meanwhile, in order to implement color display, each pixel should be able to display color, which is possible by providing a red, green, or blue color filter 230 in a region corresponding to the pixel electrode 190. In FIG. 2, the color filter 230 is formed in a corresponding region of the upper panel 200. Alternatively, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

The liquid crystal molecules change their arrangement according to the electric field generated by the pixel electrode 190 and the common electrode 270, and thus the polarization of light passing through the liquid crystal layer 3 changes. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

Referring back to FIG. 1, the driving voltage generator 700 including a DC / DC converter may turn on a gate on voltage V _on to turn on the switching element Q and a gate off to turn off the switching element Q. FIG. The voltage V _off , the power supply voltage VDD or the ground voltage GND applied to the gate driver 400 is generated.

The gray voltage generator 800 generates a plurality of gray voltages V + and V− of the positive (+) and the negative (-) related to the luminance of the liquid crystal display.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to receive a gate signal formed by a combination of a gate on voltage V _on and a gate off voltage V _off from the outside. It is applied to the gate lines G ₁ -G _n .

The data driver 500 selects the gray voltages V + and V− from the gray voltage generator 800 and applies them to the pixel as data signals.

The signal controller 600 generates control signals for controlling operations of the gate driver 400 and the data driver 500, and provides the corresponding control signals to the gate driver 400 and the data driver 500.

Next, the display operation of the liquid crystal display will be described in more detail.

The signal controller 600 inputs an input control signal for controlling the RGB image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical sync signal V _sync and a horizontal sync signal. (H _sync ), a main clock (MCLK), a data enable signal (DE) is provided. The signal controller 600 generates a gate control signal CONT1 and a data control signal CONT2 based on the input control signal, and adjusts the image signals R, G, and B to match the operating conditions of the liquid crystal panel assembly 300. After appropriately processing, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signals R ', G', and B 'are sent to the data driver 500.

The gate control signal CONT1 includes a vertical synchronization start signal STV for indicating the start of output of the gate-on pulse (high period of the gate signal), a gate clock signal CPV for controlling the output timing of the gate-on pulse, and a gate-on pulse. And an output enable signal OE that defines the width of the signal.

The data control signal CONT2 is a load for applying a corresponding data voltage to the horizontal synchronization start signal STH indicating the start of input of the image data R ', G', and B 'and the data lines D ₁ -D _m . Signal LOAD, inverted signal RVS and data that inverts the polarity of the data voltage with respect to common voltage V _com (hereinafter referred to as " polarity of data voltage " by reducing " polarity of data voltage with respect to common voltage "). Clock signal HCLK and the like.

The gray voltage generator 800 generates a plurality of gray voltages related to the luminance of the liquid crystal display and applies them to the data driver 500.

The data driver 500 sequentially receives image data R ′, G ′, and B ′ corresponding to one row of pixels according to the data control signal CONT2 from the signal controller 600, and generates a gray voltage generator ( The image data R ', G', B 'is converted into the corresponding data voltage by selecting the gray voltage corresponding to each of the image data R', G ', and B' among the gray voltages from the 800.

The gate driver 400 applies the gate-on voltage V _on to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n. Turn on the switching element (Q) connected to.

The gate-on voltage V _on is applied to one gate line G ₁ -G _n so that a row of switching elements Q connected thereto is turned on (this period is "1H" or "1 horizontal period). (horizontal period) "and the same as one period of the horizontal sync signal H _sync , the data enable signal DE, and the gate clock CPV], and the data driver 400 stores each data voltage as a corresponding data line ( D ₁ -D _m ). The data voltage supplied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q.

In this manner, the gate-on voltages V _{on are} sequentially applied to all the gate lines G ₁ -G _n during one frame to apply data voltages to all the pixels. At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel is opposite to that of the previous frame ("frame inversion). "). In this case, the polarity of the data voltage flowing through one data line may be changed (“line inversion”) within one frame or the polarity of the data voltage applied to one pixel row may be different according to the characteristics of the inversion signal RVS ( "Dot reversal").

3 is a block diagram schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 3, a signal controller 600 for driving a liquid crystal display device is disposed above the liquid crystal panel assembly 300 including the gate lines G ₁ -G _n and the data lines D ₁ -D _m . ), A printed circuit board (PCB) 550 having circuit elements such as the driving voltage generator 700 is located. The liquid crystal panel assembly 300 and the PCB 550 are electrically and physically connected to each other through a flexible printed circuit (FPC) substrate 511. Although only one FPC board 511 is illustrated in FIG. 3, a plurality of FPC substrates 511 may be sequentially installed in the horizontal direction. Therefore, the data driver 500 including a plurality of data driver ICs (not shown) receives a plurality of data signals or various driving signals transmitted from the printed circuit board 550 through these FPC boards 511.

A plurality of driving signal lines 521 are formed on the leftmost FPC board 511. The driving signal line 521 may include a plurality of gate driving units 400 through the driving signal lines 323 formed in the assembly 300 to control signals from the signal controller 600 and power voltages from the driving voltage generator 700. To a gate drive IC (not shown). These driving signal lines 323 are formed long in the vertical direction from the upper left part of the assembly 300 to the left part so as not to invade the display area D.

The other FPC board 511 may be provided with a plurality of signal lines for transmitting driving and control signals to the data driver IC connected thereto.

A plurality of driving signal transmission lines 551 are provided between each of the output terminals OE1, OE2, STV1, STV2, CPV1, and CPV2 of the signal controller 600 mounted on the printed circuit board 550 and the driving signal line 521. The resistors R1-R7 and the capacitors C1-C6 are connected to each transmission line 551. That is, one transmission line 551 has a pair of output terminals OE1, OE2, STV1, STV2, CPV1 of the signal controller 600 through each of the resistors R1, R7 and R2, R3 and R4, R5 and R6. , CPV2). A capacitor C1-C3 is connected between one of the pair of output terminals OE1 and OE2, STV1 and STV2, CPV1 and CPV2, respectively, and a capacitor C4 between each transmission line 551 and ground, respectively. -C6) is connected. Thus, these capacitors C1-C3, C4-C5 and resistors R1, R7, R4, R5 or R2, R3, R6 make an RC filter.

In the present embodiment, the output terminals OE1 and OE2 of the signal controller 600 output an output enable signal, the output terminals STV1 and STV2 output a vertical synchronization start signal, and the output terminals CPV1 and CPV2 output a gate clock signal. The output signals from the terminals OE1 and OE2, STV1 and STV2, CPV1 and CPV2 outputting the same signals are output in the same manner except that they are output with a slight time difference. Therefore, only one suitable signal is selected from two signals having a time difference according to the charging characteristic of the switching element formed in the liquid crystal panel assembly 300. In the embodiment of the present invention, a signal output from the output terminals OE2, STV1, and CPV2 is used.

A driving voltage supply line 552 is formed between each output terminal VDD and GND of the driving voltage generator 700 and each driving signal line 521. Grounded capacitors C1 and C2 are connected in parallel to the power supply terminal VDD, and a coil L1 is connected between the two capacitors C1 and C2. These capacitors C1 and C2 and the coil L1 form a low pass filter. In addition, a grounded bead BL1 is formed at the ground terminal GND.

Therefore, each output enable signal OE, vertical sync start signal STV, and gate clock signal CPV output through the corresponding output terminal OE1 or OE2, STV1 or STV2, CPV1 or CPV2 of the signal controller 600. After passing through each connected RC filter, is transmitted to the driving signal transmission line 551, and is transmitted to the driving signal line 323 formed on the liquid crystal panel assembly 300 through the driving signal line 511 of the FPC board 511. At this time, the noise of the high frequency component included in the signal OE, STV, CPV due to the operation of the signal controller 600 or the interference with the peripheral device is output to each output terminal OE1 or OE2, STV1 or STV2, CPV1 or CPV2. Since it is removed by the RC filter connected to), only the corresponding signals (OE, STV, CPV) without noise components are transmitted.

In addition, the power output from the power supply terminal VDD of the driving voltage generator 700 removes noise, which is also a high frequency component, by the LC filter including the capacitors C7 and C8 and the coil L1, thereby reducing the power supply voltage VDD. Is transferred to the driving signal line 323 through the driving voltage supply line 522 and is applied to each gate driving IC of the gate driver 400.

In addition, noise is removed from the ground terminal GND of the driving voltage generator 700 by the bead BL1 that radiates high frequency components to heat, and is transmitted to the driving signal line 323 through the driving voltage supply line 522.

As such, when various control signals or driving signals generated from the signal controller 600 or the driving voltage generator 700 mounted on the printed circuit board 550 are transmitted to the corresponding gate driving ICs of the gate driver 400, The noise of the high frequency components included in these signals is removed and then transmitted.

It is apparent that the concept of the present invention can be applied not only to a liquid crystal display but also to all other electronic devices.

According to the present invention, noise components included in various driving signals or control signals generated from the respective devices mounted on the printed circuit board and transmitted to the respective gate driving ICs are removed by a filter installed according to each signal characteristic. As a result, a stable and accurate signal supply is achieved. In addition, the noise component contained in the signal is removed, reducing the EMI problem.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (7)

A liquid crystal panel having a plurality of first signal lines, and Printed circuit board having at least one element for generating a plurality of signals and a plurality of second signal lines for respectively transmitting the plurality of signals from the element to the plurality of first signal lines Including The printed circuit board further includes a plurality of filter units connected between the device and the second signal line. Liquid crystal display. In claim 1, The device includes a signal control unit for generating at least one signal of the plurality of signals to pass to at least one filter unit of the plurality of filter units, The plurality of signals include a gate clock signal, a vertical synchronization start signal, and an output enable signal generated from the signal controller. In claim 2, The plurality of filter units includes a filter including a capacitor and a resistor connected between the signal controller and the first signal line. In claim 1, The device includes a driving voltage generator, The plurality of signals include a power supply voltage and a ground voltage generated from the driving voltage generator. In claim 4, The plurality of filter units includes a coil, a bead, and at least one capacitor mounted between the driving voltage generator and the first signal line. In claim 5, The power supply voltage is transmitted to the second signal line through a filter consisting of the coil and at least one capacitor, and the ground voltage is transferred to the second signal line through the grounded bead. In claim 1, At least one flexible printed circuit board electrically connected to each other between the liquid crystal panel and the printed circuit board; And a plurality of third signal lines connected to the first signal line and the second signal line on the flexible printed circuit board.