KR20050005672A - Liquid crystal display and driving method thereof - Google Patents

Abstract

PURPOSE: An LCD(Liquid Crystal Display) and a method for driving the same are provided to supply stable control signal to a data driving part and a gate driving part even though frequency of a main clock changes by generating the fixed clock of a predetermined frequency through an oscillator and generating the control signal based on the fixed clock. CONSTITUTION: An LCD panel(300) has a plurality of gate lines, data lines, and pixels electrically connected to the gate lines and the data lines. A gate driving part(400) applies gate on signal to the gate lines to turn on a plurality of switching elements in the pixels. A data driving part(500) applies data voltage to the data lines corresponding to image data. A signal control part(600) includes an oscillator generating the fixed clock of a predetermined frequency. The signal control part generates control signal based on the fixed clock and supplies the control signal to the gate driving part and the data driving part.

Description

Liquid crystal display and driving method thereof {LIQUID CRYSTAL DISPLAY AND DRIVING METHOD THEREOF}

The present invention relates to a liquid crystal display and a driving method thereof.

A general liquid crystal display device includes two display panels and a liquid crystal layer having dielectric anisotropy interposed therebetween. An electric field is applied to the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. Such liquid crystal displays are typical among portable flat panel displays (FPDs) that are easy to carry. Among them, TFT-LCDs using thin film transistors (TFTs) as switching elements are mainly used.

Control signals and image data such as an input clock for driving a TFT-LCD, a horizontal sync signal (H _sync ), a data enable signal (DE), and the like are in most cases a signal controller of a liquid crystal display in a computer or a graphic controller. The control unit processes the control signal and the image data according to the control signal and image data type required by the data driver and the gate driver of the liquid crystal display and transmits the control signal and the image data to each driver.

The signal controller generates various control signals required by the data driver and the gate driver of the liquid crystal display according to the number of input clocks based on the data enable signal DE input from an external device. This method is called DE ONLY MODE driving.

However, when the frequency of the input clock changes due to a problem in the input clock when driving the DE ONLY MODE, the rising edge timing and the pulse width of the control signal change. When the rising edge of the control signal and the pulse width change, the operation of the data driver and the gate driver adversely affects the operation of the data driver and the gate driver. It causes a defect such as distortion.

In particular, when the frame frequency decreases from 60Hz to 30Hz to 50Hz, such as when operating in a power save mode in a notebook PC, the probability of failure is increased.

An object of the present invention is to provide a liquid crystal display device and a driving method thereof which can generate a stable control signal and prevent screen defects even when an abnormality occurs in the main clock when the DE ONLY MODE is driven and the frequency is changed.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a waveform diagram of a control signal generated by a signal controller of a liquid crystal display according to an exemplary embodiment of the present invention.

4A is a waveform diagram illustrating a horizontal synchronization start signal according to a frequency change of a conventional main clock.

4B is a waveform diagram illustrating a horizontal synchronization start signal due to a fixed clock in a liquid crystal display according to an exemplary embodiment of the present invention.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels connected to the gate lines and the data lines and arranged in a matrix form. A liquid crystal panel assembly comprising: a gate driver for turning on a switching element included in the pixel by applying a gate-on voltage to the gate line; a data driver for applying a data voltage corresponding to image data to the pixel; An oscillator for generating a fixed clock, and a signal control unit for generating a control signal based on the fixed clock to provide to the gate driver and the data driver.

It is preferable to further include a synchronization means for synchronizing the fixed clock to the main clock from the outside while synchronizing based on a data enable signal indicating that the image data is input from the outside.

The synchronization means may be a phase locked loop (PLL) circuit.

The control signal is preferably generated based on the data enable signal.

According to another exemplary embodiment of the present invention, a method of driving a liquid crystal display includes a pixel, a gate driver to turn on a switching element included in the pixel, and a data driver to apply a data voltage corresponding to image data to the pixel. Generating a fixed clock having a predetermined frequency, generating a control signal for controlling the data driver and the gate driver based on the fixed clock, and displaying the image data according to the control signal.

The method may further include synchronizing the fixed clock to the main clock based on a data enable signal indicating that the image data is input.

The control signal is preferably generated based on the data enable signal.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A liquid crystal display and a driving method thereof according to an embodiment of the present invention will now be described in detail with reference to the drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels connected to the plurality of display signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. .

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a data signal line or data for transmitting a data signal. Line D ₁ -D _m . The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel includes a switching element Q connected to a display signal line G ₁ -G _n , D ₁ -D _m , and a liquid crystal capacitor C _LC and a storage capacitor C _ST connected thereto. It includes. The holding capacitor C _ST can be omitted as necessary.

The switching element Q is provided on the lower panel 100, and the control terminal and the input terminal are connected to the gate line G ₁ -G _n and the data line D ₁ -D _m, respectively. The output terminal is connected to the liquid crystal capacitor C _LC and the storage capacitor C _ST .

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _ST is formed by overlapping a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100, and a predetermined voltage such as a common voltage V _com is applied to the separate signal line. Is approved. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front gate line directly above the insulator.

Meanwhile, in order to implement color display, each pixel must display color, which is possible by providing a red, green, or blue color filter 230 in a region corresponding to the pixel electrode 190. In FIG. 2, the color filter 230 is formed in a corresponding region of the upper panel 200. Alternatively, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

A polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the two display panels 100 and 200 of the liquid crystal panel assembly 300.

The gray voltage generator 800 generates two sets of gray voltages related to the transmittance of the pixel. One of the two sets has a positive value for the common voltage (V _com ) and the other set has a negative value.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to receive a gate signal formed by a combination of a gate on voltage V _on and a gate off voltage V _off from the outside. It is applied to the gate lines G ₁ -G _n and usually consists of a plurality of integrated circuits.

The data driver 500 is connected to the data lines D ₁ -Dm of the liquid crystal panel assembly 300 to select the gray voltage from the gray voltage generator 800 and apply the gray voltage to the pixel as a data signal. Is made of.

A plurality of gate drive integrated circuits or data drive integrated circuits may be mounted in a tape carrier package (TCP) (not shown) to attach TCP to the liquid crystal panel assembly 300, or to integrate these onto a glass substrate without using TCP. Circuits may be directly attached (chip on glass, COG mounting method), and circuits performing the same functions as those integrated circuits may be directly mounted on the liquid crystal panel assembly 300.

The signal controller 600 generates control signals for controlling operations of the gate driver 400 and the data driver 500, and provides the corresponding control signals to the gate driver 400 and the data driver 500.

Next, the display operation of the liquid crystal display will be described in more detail.

The signal controller 600 inputs an input control signal for controlling the RGB image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical sync signal V _sync and a horizontal sync signal. (H _sync ), a main clock (MCLK), a data enable signal (DE) is provided. The signal controller 600 properly processes the image signals R, G, and B according to the operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate control signal. After generating the CONT1 and the data control signal CONT2 and the like, the gate control signal CONT1 is sent to the gate driver 400 and the data control signal CONT2 and the processed image signals R ', G', and B 'are processed. ) Is sent to the data driver 500.

The gate control signal CONT1 includes a vertical synchronization start signal STV for indicating the start of output of the gate-on pulse (high period of the gate signal), a gate clock signal CPV for controlling the output timing of the gate-on pulse, and a gate-on pulse. And an output enable signal OE that defines the width of the signal.

The data control signal CONT2 is a load for applying a corresponding data voltage to the horizontal synchronization start signal STH indicating the start of input of the image data R ', G', and B 'and the data lines D ₁ -D _m . Signal LOAD, inverted signal RVS and data that inverts the polarity of the data voltage with respect to common voltage V _com (hereinafter referred to as " polarity of data voltage " by reducing " polarity of data voltage with respect to common voltage "). Clock signal HCLK and the like.

The data driver 500 sequentially receives image data R ′, G ′, and B ′ corresponding to one row of pixels according to the data control signal CONT2 from the signal controller 600, and generates a gray voltage generator ( The image data R ', G', B 'is converted into the corresponding data voltage by selecting the gray voltage corresponding to each of the image data R', G ', and B' among the gray voltages from the 800.

The gate driver 400 applies the gate-on voltage V _on to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n. Turn on the switching element (Q) connected to.

The gate-on voltage V _on is applied to one gate line G ₁ -G _n so that a row of switching elements Q connected thereto is turned on (this period is "1H" or "1 horizontal period). (horizontal period) "and equal to one period of the horizontal sync signal Hsync, the data enable signal DE, and the gate clock CPV], and the data driver 500 converts each data voltage to a corresponding data line D. ₁ -D _m ). The data voltage supplied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q.

In this manner, the gate-on voltages V _{on are} sequentially applied to all the gate lines G ₁ -G _n during one frame to apply data voltages to all the pixels. At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel is opposite to that of the previous frame ("frame inversion). "). In this case, the polarity of the data voltage flowing through one data line may be changed (“line inversion”) within one frame or the polarity of the data voltage applied to one pixel row may be different according to the characteristics of the inversion signal RVS ( "Dot reversal").

On the other hand, as shown in Figure 1, the signal control unit 600 of the liquid crystal display according to an embodiment of the present invention includes an oscillator (40) for generating a fixed clock (OSC_CLK) of a predetermined frequency. As the oscillator, an LC oscillator circuit, an RC oscillator circuit, a Wien bridge type oscillator, a crystal oscillator, or the like can be used. Although the oscillator 40 is illustrated as being included in the signal controller 600 in FIG. 1, the oscillator 40 may be provided as long as the signal controller 600 can receive the fixed clock OSC_CLK even when located outside the signal controller 600. The frequency of the fixed clock OSC_CLK may be determined at a level equivalent to that of the main clock MCLK.

3 is a waveform diagram of a control signal generated by a signal controller of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 3, the data control signal CONT2 except for the gate control signal CONT1 and the data clock signal HCLK generated by the signal controller 600 when the DE ONLY MODE is driven, is all the data enable signal DE. Based on the number of the fixed clock OSC_CLK, the pulse width of the control signal is determined. For example, the horizontal sync start signal STH goes high ("H") at the second rising edge of the fixed clock OSC_CLK after the data enable signal DE is turned on and after two periods of the input clock. Can be brought to a low level. In addition, the load signal LOAD may be set to the high level at the fourth rising edge of the input clock after the data enable signal DE is turned off and to be set to the low level after three cycles of the input clock. The remaining control signals can also be generated in this way.

The control signal unit 600 also includes synchronization means for synchronizing the fixed clock OSC_CLK with the main clock MCLK. A phase locked loop (PLL) circuit can be used as a synchronization means for synchronizing the clock. The PLL circuit is a phase-synchronizing circuit that includes a phase detector, a low pass filter, an error amplifier, a voltage controlled oscillator, and an input signal and an output signal. This circuit detects the phase difference of and controls the phase of the output signal generator by a voltage proportional to it, and makes the output signal equal to the phase of the input signal.

The fixed clock OSC_CLK is synchronized with the main clock MCLK based on the data enable signal DE. That is, the fixed clock OSC_CLK is synchronized with the main clock MCLK at the rising edge of the data enable signal DE. Then, the signal controller 600 may generate the control signal with the correct timing by the synchronized fixed clock OSC_CLK.

4A is a waveform diagram illustrating a horizontal synchronization start signal STH according to a frequency change of a conventional main clock MCLK. FIG. 4B is a waveform diagram illustrating a fixed clock OSC_CLK in a liquid crystal display according to an exemplary embodiment of the present invention. Is a waveform diagram showing a horizontal synchronization start signal STH.

As shown in FIG. 4A, after the data enable signal DE is turned on, at the second rising edge of the main clock MCLK, the horizontal synchronization start signal STH becomes a high level and two cycles of the main clock MCLK are performed. If the frequency of the main clock MCLK is reduced by half, the rising edge of the horizontal synchronization start signal STH is delayed and the pulse width is doubled, as long as the frequency of the main clock MCLK is reduced by half. . As mentioned above, such problems cause problems such as abnormal image quality and signal distortion.

However, as shown in FIG. 4B, the liquid crystal display according to the exemplary embodiment may generate the horizontal synchronization start signal STH based on the fixed clock OSC_CLK even when the frequency of the main clock MCLK is changed. Thus, a stable control signal may be provided to the data driver 600 and the gate driver 400.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, the liquid crystal display includes an oscillator to generate a fixed clock having a predetermined frequency and generate a control signal based on the oscillator, thereby providing a stable control signal to the data driver and the gate driver even when the frequency of the main clock changes. As a result, screen failure of the liquid crystal display device is prevented.

Claims (7)

A liquid crystal panel assembly comprising a plurality of gate lines, a plurality of data lines, and a plurality of pixels connected to the gate lines and the data lines, respectively, and arranged in a matrix form; A gate driver to turn on a switching element included in the pixel by applying a gate-on voltage to the gate line; A data driver which applies a data voltage corresponding to image data to the pixel, and A signal control unit including an oscillator for generating a fixed clock of a predetermined frequency and generating a control signal based on the fixed clock and providing the control signal to the gate driver and the data driver Containing Liquid crystal display. In claim 1, And a synchronizing means for synchronizing the fixed clock to a main clock from an external source, and synchronizing based on a data enable signal indicating that the image data is input from the external source. In claim 2, And the synchronizing means is a phase locked loop (PLL) circuit. The method according to any one of claims 1 to 3, And the control signal is generated based on the data enable signal. A driving method of a liquid crystal display device comprising a pixel, a gate driver to turn on a switching element included in the pixel, and a data driver to apply a data voltage corresponding to image data to the pixel. Generating a fixed clock of a predetermined frequency, Generating a control signal for controlling the data driver and the gate driver based on the fixed clock; and Displaying the image data according to the control signal Method of driving a liquid crystal display comprising a. In claim 5, And synchronizing the fixed clock to the main clock based on a data enable signal indicating that the image data is input. In claim 5 or 6, And the control signal is generated based on the data enable signal.