KR20040065023A - Method for forming contact hole of semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a contact hole of a semiconductor device is provided to improve productivity and CD uniformity of the contact hole by using resist reflow processing. CONSTITUTION: A contact hole(150) is formed to expose a wafer by using a resist pattern(100), wherein DICD(Development Inspection Critical Dimension) of the contact hole is 180 nm. The first reflow processing is performed to reduce the size of contact hole, wherein the first AFCD(After Reflowing Critical Dimension) is 165 nm. The second reflow processing is performed to reduce the size of the contact hole, wherein the second AFCD is 140 nm.

Description

Method for forming contact hole of semiconductor device

The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device in which a contact hole is reduced by using a resist flow process.

Conventionally, there is a limit to the size of contact holes that can be formed in a single layer resist process using optical lithography.

Rayleigh's proposed resolution (R) is

R = K1 × λ / NA

The resolution R of the photoresist pattern is proportional to the wavelength λ of the light source of the reduction exposure apparatus and the process variable K1 and inversely proportional to the lens aperture NA of the exposure apparatus.

Here, the wavelength of the light source is reduced to improve the photo resolution. For example, in i-line and deep UV lithography with exposure wavelengths of 365 nm and 248 nm, the resolution limits of contact holes are about 0.3 μm × 0.3 μm and 0.20 μm × 0.20 μm, respectively.

Even using ArF lithography having a size of 193 μm, contact holes having a size of 0.13 μm × 0.13 μm are very difficult.

Optical lithography technology is high productivity and easy to apply, but the biggest disadvantage is the pattern resolution due to the given wavelength of light and the numerical aperture of the lens.

As the degree of integration of semiconductor devices increases, the size of the contact hole or the inner cylinder capacitor pattern to be implemented in the device must be reduced, but it is very difficult to obtain a fine contact hole of a desired size.

When forming a semiconductor capacitor by applying a technology of 0.15㎛ or less, the critical dimension shrinkage of the capacitor should be 150nm or less. However, when using KrF exposure equipment, the limit resolution of the contact hole is 180 nm.

In order to increase the limit resolution of the contact hole, a resist flow process has been developed and used.

Such a resist flow process is a process technology currently being introduced into a mass production process with much progress in recent years. As shown in FIGS. 1A and 1B, an exposure process and a development process are performed to use a photosensitive film using a photosensitive agent having a resolution of exposure equipment. After forming the pattern, it refers to a process for applying the thermal energy above the glass transition temperature of the photosensitive agent to allow the photosensitive agent thermal flow (thermal flow).

At this time, the contact hole 15 already formed by the supplied thermal energy is thermally flowed in the direction of decreasing the original size to finally obtain the fine contact hole required for the integration process.

By introducing such a resist flow process, it is possible to form fine contact holes below the resolution of the exposure apparatus as described above.

However, the biggest disadvantage of the resist flow process is that the flow of the photoresist suddenly occurs at a specific temperature, mainly above the glass transition temperature of the photoresist 10 resin, resulting in the profile of the contact hole 15 being bent or collapsed. In this case, the phenomenon that the contact hole 15 is buried (hereinafter referred to as "overflow") occurs when excessive flow occurs.

This is because most of the photosensitizers are very sensitive to the applied heat, so that the temperature control is incorrect, or the flow time is longer than the set value, and excessive heat flow is generated.

That is, when the resist 10 flows and the CD of the contact hole 15 shrinks, the amount of shrinkage is largely due to the temperature of the flow bake. In other words, if the flow temperature is increased by 1 ° C, the contact hole CD is further reduced by 10 nm. As such, since the temperature of the baking oven is sensitive, the uniformity of the baking oven temperature is an important factor that directly affects the uniformity of the contact hole CD.

In addition, the temperature of the wafer is affected by the uniformity of heat supplied from the baking oven and the uniformity of the atmospheric temperature encountered through the top of the wafer.

As shown in FIG. 2, the baking oven used in the related art has a temperature at the wafer edge portion lower than that at the center portion of the wafer due to the heat release.

Therefore, as shown in FIG. 4, when the CD of the contact hole is measured after the flow, less flow occurs at the edge portion of the wafer, so that the CD of the wafer edge portion is about 20 nm larger than the CD of the wafer center portion.

The CD of the wafer edge portion is large, as shown in Figs. 5a and 5b, this poor CD uniformity causes a problem of the device failure resulting in a decrease in yield.

Accordingly, an object of the present invention is to provide a method for forming a contact hole in a semiconductor device capable of forming contact holes having an exposure wavelength of less than or equal to an exposure wavelength, that is, 0.10 μm or less, in a semiconductor device. There is this.

In addition, a second object of the present invention is to provide a method for forming a contact hole in a semiconductor device which can reduce the investment cost by new equipment and increase productivity due to a simple process.

In addition, a third object of the present invention is to provide a method for forming a contact hole in a semiconductor device capable of improving device uniformity and yield by improving CD uniformity of the contact hole.

Figure 1a is a process flow diagram showing a one-step resist flow process according to the prior art.

FIG. 1B is a cross-sectional view illustrating processes of contact holes in the resist flow process of FIG. 1A; FIG.

Figure 2 shows a temperature distribution diagram of a flow bake oven according to the prior art.

Figure 3 is a view showing a wafer CD uniformity in a one-step resist flow process according to the prior art.

Figure 4 is a graph showing the CD shrinkage of the contact hole according to the wafer position according to the prior art.

5A is a graph showing a contact hole CD according to a wafer position before flow in a resist flow process according to the prior art;

5B is a graph showing contact hole CD according to wafer position after flow in a resist flow process according to the prior art;

6A is a process flow diagram illustrating a two-step resist flow process in accordance with the present invention.

6B is a photograph showing a contact hole according to the resist flow process of FIG. 6A.

7 is a view showing a wafer CD uniformity in a two-step resist flow process according to the present invention.

FIG. 8A is a graph showing data of CD uniformity of the wafer edge portion in the first resist flow process of FIG. 6A. FIG.

FIG. 8B is a graph showing data of CD uniformity of the wafer edge portion in the second resist flow process of FIG. 6A. FIG.

(Code description of main parts of drawing)

5: lower layer 10: resist

15 contact hole

The present invention for achieving the above object comprises the steps of forming a contact hole in the wafer using a resist formed on the surface of the wafer; Reducing the contact hole by performing a first flow process on top of the resultant product; And further reducing the contact hole by performing a second flow process.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

6A is a process flow diagram illustrating a two-step resist flow process according to the present invention. FIG. 6B is a photograph showing a contact hole according to the resist flow process of FIG. 5A. FIG. 7 is a two-step resist flow process according to the present invention. It is a figure which shows the wafer CD uniformity in a process.

Referring to the process of forming a contact hole of 140nm by flowing a 180nm contact hole according to the present invention.

Conventionally, in the resist flow process consisting of one step as shown in FIG. 3, 40 nm is flowed in one bake, while in the present invention, the first step is performed in the resist flow process consisting of two steps as shown in FIGS. 6A and 6B. 20 nm flow in the bake and 20 nm flow in the second bake to flow 40 nm overall.

When two bakings are performed in this way, the most vulnerable flow in the first bake flows in a better portion during the second bake, and as shown in FIG. 7, the CD range of the contact hole in the wafer is reduced and the CD is reduced. Uniformity is improved.

At this time, the temperature of the wafer is determined by the temperature of the baking oven and the temperature in the air, but in the conventional one-step flow process, the flow of the most vulnerable part affects the reduction of 40 nm, but according to the present invention. In the two-step flow process, only the 20 nm flow of the first bake is affected. In the subsequent 20 nm flow of the second bake, the flow occurs in a better state.

That is, after the first flow process, the wafer is taken out of the baking oven, cooled to room temperature, and then baked in another baking oven so that the temperature uniformity affecting the CD uniformity is more evenly distributed throughout the wafer.

Hereinafter, as an embodiment of the present invention, a process of forming a contact hole having a size of 140 nm will be described with reference to FIGS. 6A and 6B.

First, in the initial step (S1), in order to increase the adhesion between the resist pattern and the wafer is subjected to a gas phase treatment with HexaMethyl DiSilazane (HMDS) on a hot plate.

Next, in the coating step (S2), a chemically amplified resist (for example, photoresist for KrF) is spin coated to a thickness of 0.2 to 1.5㎛.

Here, as the chemically amplified resist, all photoresists such as deep UV, ArF, EUV, electron beam, X-ray, and ion beam light source may be used.

In addition, the coating thickness of the resist may be thinly coated with 0.2㎛ to 3.0㎛.

Next, in the pre-exposure bake step (S3), the soft bake is performed at 110 ° C. for 90 seconds.

Next, in the exposure step S4, a mask is covered using a KrF stepper (NA = 0.6, off-axis) and exposed to a KrF light source for development.

Here, the KrF exposure source may use ArF, EUV, electron beam, X-rays.

Subsequently, in the post-exposure bake step (S5), the post-exposure bake is performed at 110 ° C. for 90 seconds.

Here, the post-exposure bake may be performed at 80 to 150 ° C. for 60 to 200 seconds.

Then, in the developing step (S6), after developing a fine contact hole of 180nm for 60 seconds in the TMAH developer solution of 2.38% concentration and dried.

Here, the TMAH developer may be used in a concentration range of 0.1 to 10%.

Then, DIW is applied to the wafer and rotated at a low speed of 100 rpm so that DIW is present in the contact hole, but not excessively on the wafer.

Subsequently, in the first resist flow process step S7, a 180 nm contact hole (DICD: Development Inspection Critical Dimension), which is the original contact hole size, is first baked at 126 ° C. for 90 seconds to allow resist flow to occur. After the primary shrinkage to form a contact hole (AFCD: After Flow Critical Dimension) of 165nm and cooled to room temperature.

In this case, the cooling temperature may be cooled to a temperature of 15 to 40 ℃, the first bake may be baked for 10 to 200 seconds at 90 to 200 ℃.

Next, in the second resist flow process step (S8), the 165 nm contact hole is second baked at 134 ° C. for 90 seconds to allow resist flow to occur, thereby reducing the contact hole to the second, and thereby reducing the 140 nm contact hole (AFCD). To form.

At this time, the secondary bake may be baked for 10 to 200 seconds at 90 to 200 ℃.

7 is a view showing a wafer CD uniformity in a two-step resist flow process according to the present invention.

Table 1 and Table 2 show the CD uniformity of the wafer edge and the process conditions in the resist flow process consisting of two steps according to the present invention.

Table 1

1st flow process 2nd flow process DICD 180 nm 180 nm 1st bake 90 ℃ / 90sec 180 nm No flow 126 ℃ / 90sec 168 nm 12nm flow Second bake 132 ℃ / 90sec 140 nm 40nm flow 134.8 ℃ / 90sec 140 nm 28nm flow

TABLE 2

1st flow process 2nd flow process % Improvement inside Mutual block Edge inside Mutual block Edge inside Mutual block Edge Average 141.6 140 140 152 142.3 142 139 146 maximum 162 155 145 175 154 155 143 159 at least 126 125 133 135 129 131 132 135 range 36 30 12 40 25 11 11 24 30.6 20 8.33 40 3-sigma 23.53 14.7 8.9 26 14.9 7.4 7.4 16.7 36.7 27.9 16.9 35.8

As described above, the present invention has an effect that a contact hole below an exposure wavelength can be implemented in a device. That is, the contact hole of 0.10㎛ or less can be implemented through the resist flow process.

In addition, it is possible to reduce the investment cost of new equipment by enabling the contact hole, which is possible with ArF, electron beam, or X-ray technology, with 248 nm lithography technology.

This 248nm lithography technology has the effect of increasing productivity because the process is simpler than ArF, electron beam or X-ray technology.

In addition, by improving the CD uniformity of the contact hole has the effect of improving the device characteristics and yield.

On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (5)

Forming a contact hole in the wafer using a resist formed on a wafer surface; Reducing the contact hole by performing a first flow process on top of the resultant product; And And further reducing the contact hole by performing a second flow process. The method of claim 1, wherein a TMAH developer having a concentration range of 0.1 to 10% is used to form the contact hole. The method of claim 1, wherein the flow process is a baking process. The method of claim 3, wherein the baking process is performed at 90 to 200 ° C. for 10 to 200 seconds, respectively. The method of claim 1, further comprising cooling the wafer to a temperature of 15 to 40 ° C. after the first flow process.