KR20040061974A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR20040061974A KR20040061974A KR1020020088283A KR20020088283A KR20040061974A KR 20040061974 A KR20040061974 A KR 20040061974A KR 1020020088283 A KR1020020088283 A KR 1020020088283A KR 20020088283 A KR20020088283 A KR 20020088283A KR 20040061974 A KR20040061974 A KR 20040061974A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 보다 상세하게는 기존의 DRAM, 로직(Logic), 플래시 메모리소자의 트랜지스터 공정에서 사용되는 반도체 소자의 하드 마스크로 이용되는 실리콘질화막(SiN)을 사용하지 않고, 바로 실리콘 기판상에 게이트전극을 형성시켜 소자 분리막공정을 별도로 진행하지 않고도 소자분리영역을 형성할 수 있는 반도체 소자의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, does not use a silicon nitride film (SiN) used as a hard mask of a semiconductor device used in a transistor process of a conventional DRAM, logic, and flash memory device. Instead, the present invention relates to a method of manufacturing a semiconductor device capable of forming a device isolation region without forming a gate electrode on a silicon substrate and proceeding with a device isolation process.
이하에서 기존의 반도체 소자의 트랜지스터 제조방법을 도 1을 참조하여 간략하게 설명하면 다음과 같다.Hereinafter, a transistor manufacturing method of a conventional semiconductor device will be briefly described with reference to FIG. 1.
도 1은 종래 기술에 따른 트랜지스터 제조과정을 설명하기 위한 공정 단면도이다.1 is a cross-sectional view illustrating a process of fabricating a transistor according to the prior art.
도 1에 도시된 바와 같이, 먼저 소자분리막을 형성하기 위한 공정으로 실리콘 기판(1)상에 패드 산화막과 패드 질화막을 차례로 증착한 뒤 STI식각공정을 진행하여 갭매립산화막을 형성하고 CMP공정으로 평탄화시킴으로써 소자분리막(3)을 형성한다.As shown in FIG. 1, first, a pad oxide film and a pad nitride film are sequentially deposited on a silicon substrate 1 as a process for forming a device isolation film, followed by an STI etching process to form a gap buried oxide film and planarization by a CMP process. In this manner, the device isolation film 3 is formed.
이어서, 패드 산화막과 패드 질화막을 차례로 제거한 후 게이트 산화막(7)과 게이트(5)를 적층하고 게이트측벽에 스페이서(11)를 형성한 뒤, 이어 LDD/접합 이온 주입영역(9),(13)을 차례로 형성하여 트랜지스터를 제조한다.Subsequently, after removing the pad oxide film and the pad nitride film, the gate oxide film 7 and the gate 5 are stacked and spacers 11 are formed on the gate side walls, followed by LDD / junction ion implantation regions 9 and 13. Are sequentially formed to fabricate a transistor.
그러나, 기존의 반도체 소자의 제조 과정에서는 STI식각 공정및 CMP공정등의 각 공정단계마다 사용되는 마스크의 수가 많고, 각 공정의 단계가 복잡하고 많다는 단점이 있으며, 소자 수율에의 영향및 제조단가의 상승에 직접적인 영향을 미치게된다.However, in the conventional semiconductor device manufacturing process, the number of masks used in each process step such as the STI etching process and the CMP process is large, and the steps of each process are complicated and many have disadvantages. Will have a direct impact on the rise.
따라서 본 발명은 상기와 같은 문제점을 해결하기위해 안출된 것으로, 소자분리막공정과정을 따로 진행하지 않고 바로 게이트 전극을 형성한 뒤 RIE를 이용해 STI를 형성시키는 방법을 사용함으로써 공정 단계를 줄임과 동시에 이후 연계공정에 대해서도 많은 장점을 갖고 있어 공정단축및 생산비용 절감에 현저한 효과를 가져올 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Therefore, the present invention was devised to solve the above problems, and the process steps are reduced by using a method of forming an STI using RIE immediately after forming a gate electrode without performing device isolation process. Its purpose is to provide a method for manufacturing a semiconductor device that has a number of advantages over the linking process, which can have a significant effect on process shortening and production cost reduction.
도 1은 종래 기술에 따른 반도체 소자의 제조 과정을 설명하기 위한 공정 단면도.1 is a cross-sectional view for explaining a manufacturing process of a semiconductor device according to the prior art.
도 2a 내지 도 2j는 본 발명의 실시예에 따른 반도체 소자의 제조 과정을 설명하기 위한 단면도.2A to 2J are cross-sectional views illustrating a manufacturing process of a semiconductor device in accordance with an embodiment of the present invention.
-도면의 주요 부분에 대한 부호의 설명-Explanation of symbols on main parts of drawing
10 : 실리콘 기판 24 : P-이온10 silicon substrate 24 P-ion
12 : 패드 산화막 26 : 제 1절연막12 pad oxide film 26 first insulating film
14 : 폴리 실리콘 28 : N+이온14 polysilicon 28 N + ions
16 : 실리콘 질화막 30 : P+이온16: silicon nitride film 30: P + ion
18 : 제1 감광막 패턴 32 : 제 2절연막18: first photosensitive film pattern 32: second insulating film
20 : 제2 감광막 패턴 34 : 트렌치 영역20: second photosensitive film pattern 34: trench region
22 : N-이온 36 : 측벽 산화막22: N-ion 36: sidewall oxide film
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조방법은, 실리콘 기판상에 패드 산화막패턴과 게이트 패턴및 하드마스크 패턴을 형성하는 단계; 상기 실리콘기판의 제1 도전형 MOS지역에 제 2도전형 이온 주입을 실시하는 단계;실리콘 기판의 제2 도전형 MOS지역에 제 1도전형 이온주입을 실시하는 단계; 상기 게이트 패턴 측벽에 절연막 스페이서를 형성하는 단계; 상기 절연막 스페이서를 마스크로 상기 실리콘 기판의 제 1도전형 MOS지역에 제 2도전형 이온 주입을 실시한 후 다시 상기 실리콘기판의 제 2도전형 MOS지역에 제 1도전형 이온주입을 차례로 실시하여 LDD영역과 접합영역을 형성하는 단계;및 상기 기판 전체에 절연막을 형성한후 상기 절연막과 패드 산화막패턴및 실리콘 기판을 순차적으로 제거하여 상기 실리콘 기판내에 소자 분리용 트렌치를 형성하는 단계를 포함하여 구성되는 것을 특징으로 한다.A semiconductor device manufacturing method according to the present invention for achieving the above object comprises the steps of: forming a pad oxide film pattern, a gate pattern and a hard mask pattern on a silicon substrate; Performing a second conductive ion implantation into a first conductive MOS region of the silicon substrate; performing a first conductive ion implantation into a second conductive MOS region of the silicon substrate; Forming an insulating film spacer on sidewalls of the gate pattern; After the second conductive type ions are implanted into the first conductive MOS region of the silicon substrate using the insulating film spacer as a mask, the second conductive type ions are sequentially implanted into the second conductive MOS region of the silicon substrate to sequentially perform the LDD region. And forming a junction region, and forming an isolation layer in the silicon substrate by sequentially removing the insulation layer, the pad oxide layer pattern, and the silicon substrate after forming the insulation layer over the entire substrate. It features.
(실시예)(Example)
이하, 본 발명에 따른 반도체 소자의 제조 방법에 대해 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a내지 도 2j는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위한 공정 단면도이다.2A to 2J are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
본 발명에 따른 반도체 소자의 제조 방법은, 도 2a에 도시된 바와 같이, 실리콘 기판(10)상에 패드 산화막(12)을 증착후 이어 폴리 실리콘(14)을 증착한 다음 상기 폴리실리콘(14)상에 패드 질화막(16)을 증착한다.In the method of manufacturing a semiconductor device according to the present invention, as illustrated in FIG. 2A, after the pad oxide layer 12 is deposited on the silicon substrate 10, the polysilicon 14 is deposited and then the polysilicon 14 is deposited. The pad nitride film 16 is deposited on it.
그 다음, 도 2b에 도시된 바와 같이, 상기 기판위에 감광물질을 도포한 다음, 포토리소그라피 공정기술에 의해 상기 감광물질층을 노광 및 현상 공정을 통해 선택적으로 패터닝하여 감광막 패턴을 형성한다. 이어서 상기 감광막 패턴을 마스크로 상기 패드질화막(16)과 폴리 실리콘(14)및 패드 산화막(12)을 순차적으로 식각하여 게이트영역을 형성한다.Next, as shown in FIG. 2B, a photosensitive material is coated on the substrate, and then the photosensitive material layer is selectively patterned through an exposure and developing process to form a photosensitive film pattern by a photolithography process technique. Subsequently, the pad nitride layer 16, the polysilicon 14, and the pad oxide layer 12 are sequentially etched using the photoresist pattern as a mask to form a gate region.
이어서 도 2c에 도시된 바와 같이,제2감광막패턴을 형성한 후 이를 마스크로 NMOS영역의 게이트 영역상에 0 P(Phosphorous)또는 As(Arsenic)이온으로 N-이온 주입을 실시한다.Subsequently, as shown in FIG. 2C, after forming the second photoresist layer pattern, N-ion implantation is performed with P (Phosphorous) or As (Arsenic) ions on the gate region of the NMOS region using the mask.
그 다음, 도 2d 도시된 바와 같이, 상기 제2감광막 패턴(18)을 제거한 후 반대로 제 3감광막 패턴(20)으로 PMOS지역의 게이트 영역을 덮은 후, 앞의 도 2c에서와 같은 방법으로 보론(Boron)이온을 이용하여 P-이온주입을 실시하면, 도 2e에 도시된 바와 같이, 각 게이트 영역별로 N-이온 지역및(22)및 P- 이온지역(24)이 형성된다.Next, as shown in FIG. 2D, after removing the second photoresist pattern 18, the gate region of the PMOS region is covered with the third photoresist pattern 20, and then boron ( When P-ion implantation is performed using Boron) ion, N-ion regions and 22 and P-ion regions 24 are formed for each gate region as shown in FIG. 2E.
이어서 도 2f에 도시된 바와 같이, 상기 제 3감광막 패턴(20)을 제거한후 상기 기판 결과물상에 LPCVD방법으로 제 1절연막을 증착후 이방성 식각을 실시하여 제 1절연막 스페이서(26)를 형성한다.Subsequently, as shown in FIG. 2F, after removing the third photoresist pattern 20, a first insulating layer is deposited on the substrate by LPCVD and then anisotropically etched to form a first insulating layer spacer 26.
그 다음 도 2g에 도시된 바와 같이, 감광막 패턴을 이용하여 앞의 이온주입과정과 같은 방법으로 N+(28)및, P+(30)이온주입을 실시하면, 각 게이트에 소오스/드레인 LDD(Lightly Doped Drain)와 접합영역이 형성된다.Next, as shown in FIG. 2G, when N + (28) and P + (30) ions are implanted using the photoresist pattern in the same manner as the ion implantation process, a source / drain LDD (Lightly Doped) is applied to each gate. Drain) and junction area are formed.
이어서, 도 2h에 도시된 바와 같이, 후속공정에서 실시될 식각공정에 의해 게이트가 손상되는 것을 방지하기 위한 제 2절연막(32)을 상기 기판 결과물상에 증착한다. 이때 제 2절연막(32)을 증착하는 방법으로 LPCVD(Low Pressure Chemical Vapor Deposition)방법을 이용한다.Subsequently, as shown in FIG. 2H, a second insulating film 32 is deposited on the substrate resultant to prevent the gate from being damaged by an etching process to be performed in a subsequent process. In this case, a low pressure chemical vapor deposition (LPCVD) method is used as a method of depositing the second insulating layer 32.
그 다음, 도 2i에 도시된 바와 같이, 상기 기판상에 감광물질을 도포하여 포토리소그라피 기술에의해 STI가 될 지역을 패터닝하여 감광막 패턴을 형성한후 상기 감광막 패턴을 마스크로 상기 제 2절연막(32), 게이트 산화막(12)및 실리콘 기판(10)을 차례로 식각하여 상기 실리콘 기판내에 트렌치(34)를 형성한다.이때 앞서 증착한 제 2절연막은 식각시 보호막 역할을 하며, 트렌치영역의 깊이는 약 4000Å정도로 이방성 식각을 실시한다.Next, as shown in FIG. 2I, a photosensitive material is coated on the substrate to pattern an area to be STI by photolithography to form a photoresist pattern, and then the second insulating layer 32 using the photoresist pattern as a mask. ), The gate oxide film 12 and the silicon substrate 10 are sequentially etched to form the trench 34 in the silicon substrate. At this time, the second insulating layer deposited as a protective film during etching and the depth of the trench region are approximately Anisotropic etching is performed at about 4000Å.
마지막으로 도 2j에 도시된 바와 같이, 상기 기판전체에 식각 데미지를 회복하기 위해 측벽 산화막(36)을 증착한 후 후속 공정을 실시한다.Finally, as shown in FIG. 2J, the sidewall oxide layer 36 is deposited to recover etch damage on the entire substrate, and then a subsequent process is performed.
이상에서 본 바와 같이, 본 발명에 따른 반도체 소자의 제조 방법에 의하면, 기존의 하드 마스크 역할을 하였던 질화막을 사용하지 않고 폴리 실리콘을 바로 증착하여 게이트를 형성한뒤 RIE(reactive ion etching)를 이용해 STI를 형성시키는 방법을 이용함으로써 공정 단계를 줄여 양산시 비용 절감및 생산효율 측면에서 상당한효과를 얻을 수가 있으며 동시에 이후 연계공정과정에도 많은 효과를 얻을수 있다.As described above, according to the method of manufacturing a semiconductor device according to the present invention, without forming a gate by directly depositing polysilicon without using a nitride film that used as a conventional hard mask, STI using reactive ion etching (RIE) By using the method of forming the process, it is possible to reduce the process step and achieve significant effects in terms of cost reduction and production efficiency in mass production, and at the same time, it can also have many effects in the subsequent process.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구 범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 주구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, various modifications can be carried out by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
Claims (5)
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| KR1020020088283A KR20040061974A (en) | 2002-12-31 | 2002-12-31 | Method for manufacturing semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100845103B1 (en) * | 2005-12-28 | 2008-07-09 | 동부일렉트로닉스 주식회사 | Method of fabricating the semiconductor device |
| CN108074867A (en) * | 2016-11-08 | 2018-05-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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2002
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100845103B1 (en) * | 2005-12-28 | 2008-07-09 | 동부일렉트로닉스 주식회사 | Method of fabricating the semiconductor device |
| CN108074867A (en) * | 2016-11-08 | 2018-05-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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