KR20040061500A - Thin Film Transistors - Google Patents

Abstract

PURPOSE: A TFT is provided to prevent an etchant from flowing into a step difference portion of a semiconductor layer and gate lines while forming the gate lines in dummy patterns, thereby efficiently preventing disconnection of the gate lines. CONSTITUTION: A semiconductor layer(23) is formed in a predetermined area of a substrate(21). A gate insulating film(24) is formed on a front side of the substrate(21) including the semiconductor layer(23). Gate lines are formed in predetermined areas of the gate insulating film(24). Dummy patterns are spaced from a part overlapped with the gate lines, and are protruded from the semiconductor layer(23) along longitudinal direction of the gate lines. The semiconductor layer(23) defines an impurities area, and forms a source electrode and a drain electrode in connection with the impurities area.

Description

Thin Film Transistors

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a thin film transistor capable of preventing the disconnection of a gate line by changing the patterning of the active layer.

As the information society develops, the demand for display devices is increasing in various forms, and in recent years, liquid crystal display devices (LCDs), plasma display panels (PDPs), electro luminescent displays (ELD), and vacuum fluorescent (VFD) Various flat panel display devices such as displays have been studied, and some of them are already used as display devices in various devices.

Among them, LCD is the most widely used as the substitute for CRT (Cathode Ray Tube) for mobile image display device because of its excellent image quality, light weight, thinness, and low power consumption. In addition to the use of the present invention has been developed in various ways such as a television and a computer monitor for receiving and displaying broadcast signals.

In order to use such a liquid crystal display as a general screen display device in various parts, it is a matter of how high quality images such as high definition, high brightness and large area can be realized while maintaining the characteristics of light weight, thinness and low power consumption. Can be.

A general liquid crystal display device may be largely divided into a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel, wherein the liquid crystal panel includes first and second glass substrates bonded to each other with a predetermined space; It consists of a liquid crystal layer injected between the said 1st, 2nd glass substrate.

Here, the first glass substrate (TFT array substrate) has a plurality of gate lines arranged in one direction at regular intervals, a plurality of data lines arranged at regular intervals in a direction perpendicular to the gate lines, A plurality of pixel electrodes formed in a matrix form in each pixel region defined by crossing a gate line and a data line, and a plurality of thin film transistors switched by signals of the gate line to transfer the signal of the data line to each pixel electrode. Is formed.

In the second glass substrate (color filter array substrate), a light shielding layer for blocking light in portions other than the pixel region, an R, G, and B color filter layer for expressing color colors are common to implement an image. An electrode is formed.

The driving principle of the general liquid crystal display device uses the optical anisotropy and polarization property of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the arrangement of molecules can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal by optical anisotropy, thereby representing image information.

Currently, an active matrix LCD, in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner, is attracting the most attention due to its excellent resolution and ability to implement video.

In an active matrix thin film transistor liquid crystal display (TFT LCD), an electrode of an individual pixel forming a screen of a display device is controlled using a transistor. In this case, the transistor is formed on a substrate using a semiconductor thin film.

The thin film transistor liquid crystal display (TFT LCD) may be roughly divided into an amorphous silicon type and a polysilicon type according to the characteristics of the semiconductor thin film used.

In both cases, efforts are being made to reduce the number of exposure steps in the process in order to reduce the process cost and increase the yield. In the case of amorphous silicon, it is formed by using chemical vapor deposition (CVD) at low temperature. In this case, there is an advantage in the characteristics of the liquid crystal display device using the glass substrate.

However, in the case of amorphous silicon, the carrier mobility is low, and therefore, it is not suitable for forming a transistor element of a driving circuit requiring fast operating characteristics. This fact means that the IC for driving the liquid crystal display device must be manufactured separately and attached to the periphery of the liquid crystal panel, and the manufacturing cost of the liquid crystal display device is increased by adding a process for the driving module.

On the other hand, since polysilicon has a much higher carrier mobility than amorphous silicon, it can be used to manufacture an IC for a driving circuit. Therefore, when polysilicon is used as a semiconductor thin film for forming a thin film transistor of a liquid crystal display device, a thin film transistor element for a pixel electrode and a transistor element for a driving circuit can be formed together on a same glass substrate through a series of processes.

This may reduce the cost of the module process in manufacturing the liquid crystal display and at the same time reduce the power consumption of the liquid crystal display.

However, in the case of using polysilicon, in order to form a polysilicon thin film on a substrate, an amorphous silicon thin film is first formed through a low temperature CVD process, and an additional process for crystallization such as irradiating a laser beam is required, and a carrier The leakage current flows excessively at the moment when the gate voltage is turned off in the transistor formed by the high mobility, thereby preventing a sufficient electric field from being maintained in the pixel portion. Such a method of suppressing the occurrence of leakage current may include a lightly doped drain (LDD) region in which the impurity concentration is ion-implanted at the junction between the source and drain regions of the thin film transistor and the channel, or an offset that is not impurity ion implantation. It is common to use a method in which a region is provided to act as a barrier against leakage current.

Hereinafter, a thin film transistor capable of preventing disconnection of a gate line by changing a patterning of a conventional active layer will be described with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a general polysilicon thin film transistor.

As shown in FIG. 1, a general polysilicon thin film transistor includes a semiconductor layer 13 formed in a predetermined region on a substrate 11 and a gate insulating layer 14 formed on the substrate 11 including the semiconductor layer 13. A gate electrode 15a formed in a predetermined region on the gate insulating film 14, an interlayer insulating film 16 formed on the entire surface of the gate insulating film 14 including the gate electrode 15a, and the gate electrode 15a. The source / drain electrodes 17 are formed to be connected to both semiconductor layers 13.

FIG. 2 is a plan view showing a state after the gate line is formed on the semiconductor layer of FIG. 1, FIG. 3 is a structural cross-sectional view taken along line II ′ of FIG. 2, and FIG. 4A is a cross-sectional view taken along line II-II ′ of FIG. 2. to be.

2 and 3, when the top gate polysilicon thin film transistor is formed, the semiconductor layer 13 is formed in a predetermined region on the substrate 11, and then the gate electrode (eg, through the gate insulating film 14) is formed. A gate line 15 having 15a is formed.

In this case, as shown in FIG. 4A, since the semiconductor layer 13 is selectively formed only in a predetermined region on the substrate 11, a step occurs in a portion of the gate line 15 overlapping with the semiconductor layer 13. .

FIG. 4B is an SEM diagram illustrating a step portion between the semiconductor layer and the gate line of FIG. 4A.

As shown in FIG. 4B, when the stepped portion where the semiconductor layer 13 and the gate line 15 overlap each other is examined through a scanning electron microscope (SEM), it may be confirmed that the gate line 15 of the stepped portion is relatively further entered.

When the etching process for forming the gate line 15 is performed, the metal layer is deposited on the entire surface, and then, the substrate including the metal layer is immersed in an etching solution, or the etching process is performed in a predetermined etching gas atmosphere. The step of leaving only the pattern and selectively removing is performed. In the stepped portion, the etching liquid or the etching gas easily penetrates and the patterning is performed relatively more than other parts.

This is caused by an infiltration of etchant (etching liquid and etching gas) during the etching process for forming the gate line 15 by forming a seam at the edge of the semiconductor layer 13.

Looking in detail with reference to Figure 5 as follows.

FIG. 5 is an SEM diagram showing a structural cross section taken along the line III-III ′ of FIG. 2.

As shown in FIG. 5, when the step A is overlapped with the semiconductor layer 13 and the gate line 15, the pattern is most vulnerably patterned, the gate line 15 pattern is formed to be severely inward from the step. It can be seen that there is a possibility of disconnection.

FIG. 6 is an equivalent circuit diagram of forming a thin film transistor on a line III-III 'of FIG. 2.

As shown in FIG. 6, the gate electrode 15a and the semiconductor layer 13 overlap each other, and a thin film transistor (TFT) including a source / drain electrode (not shown) connected to the semiconductor layer 13 is formed. In this case, it can be seen that a thin film transistor having a low threshold voltage is additionally formed in the region of A (ie, the channel edge portion) in parallel with the thin film transistor.

As described above, when the length of the gate electrode 15a corresponding to the channel edge portion of the semiconductor layer 13 is shortened, the effect of connecting the transistor having the low threshold voltage Vth in parallel to the channel edge portion is generated in parallel. do.

As a result, when the gate voltage Vg is increased, a hump may occur at a value of the drain current Id at a predetermined value. Thus, the thin film transistor manufactured with the possibility of disconnection of the gate line 15 may be The threshold voltage Vth can be lowered, accompanied by a drop in the threshold voltage uniformity of the entire thin film transistor.

The conventional thin film transistor has the following problems.

When the gate length is shortened at the channel edge portion, this causes the transistor having a low threshold voltage Vth to be connected in parallel to the channel edge portion.

Therefore, when the gate voltage Vg is increased, a hump may occur at a value of the drain current Id at a predetermined value, and the thin film transistor manufactured with the possibility of disconnection of the gate line may have a low threshold voltage. This is accompanied by a drop in the threshold voltage uniformity of the overall device.

This is a bigger problem as the design rule becomes smaller and the gate length becomes shorter, which has recently emerged as an urgent problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a thin film transistor which can prevent disconnection of a gate line by changing a patterning of an active layer.

1 is a cross-sectional view showing a typical polysilicon thin film transistor

FIG. 2 is a plan view illustrating a state after a gate line is formed on the semiconductor layer of FIG. 1.

3 is a cross-sectional view taken along line II ′ of FIG. 2;

4A is a cross-sectional view taken along line II-II 'of FIG.

FIG. 4B is an SEM diagram showing a step portion between the semiconductor layer and the gate line of FIG. 4A.

FIG. 5 is an SEM diagram showing a structural cross section taken along line III-III 'of FIG. 2;

FIG. 6 is an equivalent circuit diagram of forming a thin film transistor on a line III-III 'of FIG. 2.

7 is a plan view illustrating a thin film transistor according to a first exemplary embodiment of the present invention.

FIG. 8 is a cross-sectional view taken along line IV-IV 'of FIG.

9 is a cross-sectional view taken along the line VV ′ of FIG. 7.

FIG. 10 is an enlarged view of line VI-VI 'of FIG. 7;

FIG. 11 is a cross-sectional view taken along the line VI-VI of FIG.

12 is a plan view illustrating a thin film transistor according to a second exemplary embodiment of the present invention.

* Description of symbols on the main parts of the drawings *

21 substrate 23 semiconductor layer

23a, 23b: dummy pattern of semiconductor layer 25: gate line

The thin film transistor of the present invention for achieving the above object is a semiconductor layer formed in a predetermined region on the substrate, a gate insulating film formed on the entire surface of the substrate including the semiconductor layer, a gate line formed in a predetermined region on the gate insulating film, It is characterized in that it comprises a dummy pattern formed to protrude from the semiconductor layer at a predetermined interval apart from the overlapping gate line.

The dummy pattern is preferably the same material as the semiconductor layer.

The dummy pattern is preferably formed on the same layer as the semiconductor layer.

The dummy pattern is preferably formed in the longitudinal direction of the gate line.

It is preferable that the width | variety of the said dummy pattern is 1 micrometer-10 micrometers.

The distance between the dummy pattern and the gate line is preferably 0.5 μm to 5 μm.

The dummy pattern may be formed to include a dummy pattern having a width wider than a side adjacent to the gate line.

It is preferable to further include a source / drain electrode connected to the semiconductor layer.

In addition, the thin film transistor of the present invention for achieving the same object includes a semiconductor layer formed in a predetermined region on the substrate, a gate insulating film formed on the entire surface of the substrate including the semiconductor layer, a gate line formed in a predetermined region on the gate insulating film, Another feature is that a dummy pattern is formed to protrude from a semiconductor layer along a length direction of the gate line by spaced apart from the overlapping portion of the gate line.

In addition, the thin film transistor of the present invention for achieving the same object includes a semiconductor layer formed in a predetermined region on the substrate, a gate insulating film formed on the entire surface of the substrate including the semiconductor layer, a gate line formed in a predetermined region on the gate insulating film, The gate line overlaps the gate line with a predetermined distance from the semiconductor layer, and protrudes into the semiconductor layer. The closer to the overlap region, the relatively wide dummy pattern is included.

Hereinafter, the thin film transistor of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 7 is a plan view illustrating a thin film transistor according to a first exemplary embodiment of the present invention, FIG. 8 is a cross-sectional view taken along line IV to IV 'of FIG. 7, and FIG. 9 is a cross-sectional view taken along line V to V ′ of FIG. 7. , FIG. 10 is an enlarged view of line VI-VI 'of FIG. 7, and FIG. 11 is a cross-sectional view of structure line VI-VI of FIG. 7.

As shown in FIGS. 7 and 9, the thin film transistor according to the first exemplary embodiment of the present invention may be formed on the entire surface of the substrate 21 including the semiconductor layer 23 formed in a predetermined region on the substrate 21 and the semiconductor layer 23. The longitudinal direction of the gate line 25 is spaced apart by a predetermined interval between the formed gate insulating film 24, the gate line 25 formed in a predetermined region on the gate insulating film 24, and a portion where the gate line 25 overlaps. The dummy pattern 23a is formed to protrude from the semiconductor layer 23.

Although not shown, an impurity region is defined in the semiconductor layer 23, and is connected to the impurity region to form a source / drain electrode (not shown).

The dummy pattern 23a protruding from the semiconductor layer 23 is simultaneously formed in the process of forming the semiconductor layer 23. In other words, the dummy pattern 23a is simultaneously formed in a process of selectively removing the entire surface deposited semiconductor layer material.

As shown in FIG. 10, when the enlarged portion of the dummy pattern 23a is formed, the dummy pattern primarily prevents an etchant from flowing in the overlapped portion of the gate line 25 and the semiconductor layer 23. This prevents the occurrence of disconnection.

As shown in FIG. 11, when the cross-section of the portion where the dummy pattern 23a is formed is examined, the gate insulating layer 24 is formed higher on the portion where the dummy pattern 23a is further formed. The dummy pattern 23a serves as a barrier to flow into the overlapped portion of the line and the semiconductor layer.

However, the dummy pattern 23a is formed in an adjacent region at a predetermined distance from the overlapped portion of the semiconductor layer 23 and the gate line 25, but is not formed to correspond directly to the overlapped portion. This is because, when formed so as to correspond directly to the overlapping portions, overetching may occur at the overlapping portions when the gate lines are formed by selectively removing the metal layer deposited on the gate insulating layer.

In this case, the dummy pattern 23a may have a width of about 1 μm to 10 μm, and an interval between the overlap portion of the gate line 25 and the semiconductor layer 23 and the dummy pattern 23a may be 0.5 μm or more. 5 micrometers is used to protect the gate line at the overlapped portion.

12 is a plan view illustrating a thin film transistor according to a second exemplary embodiment of the present invention.

As shown in FIG. 12, the thin film transistor according to the second exemplary embodiment of the present invention includes a semiconductor layer 23 formed in a predetermined region on a substrate (not shown) and a gate insulating film formed on the entire surface of the substrate including the semiconductor layer 23. ), The gate line 25 formed in a predetermined region on the gate insulating film, and the semiconductor layer 23 at a predetermined distance from the semiconductor layer 23 where the gate line 25 overlaps the semiconductor layer 23. Protruding from, and closer to the overlap area, the relatively wide dummy pattern 23b.

Similarly to the first embodiment, the second embodiment of the present invention is to form a dummy pattern in the same process of forming the semiconductor layer 23, and the adjacent side overlapping the shape of the dummy pattern 23b is more relative than the far side. By forming a wider width, a right triangle pattern is formed as a dummy pattern 23b on both sides of the semiconductor layer 23.

Here, the dummy pattern 23b is formed to be spaced apart from the region overlapping with the semiconductor layer 23 and the gate line 25 by 0.5 μm to 5 μm to protect the gate line 25 at the overlapped portion. do.

The thin film transistor of the present invention as described above has the following effects.

First, the dummy pattern formed from the semiconductor layer may prevent the inflow of the etchant from the stepped portion of the gate line and the semiconductor layer by the etchant in the process of forming the gate line, thereby effectively preventing the disconnection of the gate line.

Therefore, it is possible to prevent a phenomenon in which the gate length of the channel edge is shortened, which may be caused by the possibility of disconnection of the gate line occurring at the stepped portion between the semiconductor layer and the gate line when forming the thin film transistor.

Third, it is possible to prevent the occurrence of a hum or a relatively low voltage of the device characteristics of the thin film transistor, thereby improving the uniformity of the threshold voltage (Vth).

Claims (10)

A semiconductor layer formed in a predetermined region on the substrate; A gate insulating film formed on an entire surface of the substrate including the semiconductor layer; A gate line formed in a predetermined region on the gate insulating film; And a dummy pattern protruding from the semiconductor layer at a predetermined interval from the overlapping portion of the gate line. The method of claim 1, The dummy pattern is a thin film transistor, characterized in that the same material as the semiconductor layer. The method of claim 1, And the dummy pattern is formed on the same layer as the semiconductor layer. The method of claim 1, And the dummy pattern is formed in a length direction of the gate line. The method of claim 4, wherein The width of the dummy pattern is a thin film transistor, characterized in that 1㎛ to 10㎛. The method of claim 4, wherein And the gap between the dummy pattern and the gate line is 0.5 μm to 5 μm. The method of claim 1, And the dummy pattern is formed to include a dummy pattern having a width wider than a side adjacent to the gate line. The method of claim 1, And a source / drain electrode connected to the semiconductor layer. A semiconductor layer formed in a predetermined region on the substrate; A gate insulating film formed on an entire surface of the substrate including the semiconductor layer; A gate line formed in a predetermined region on the gate insulating film; And a dummy pattern protruding from the semiconductor layer along a length direction of the gate line at a predetermined interval in a portion where the gate line overlaps. A semiconductor layer formed in a predetermined region on the substrate; A gate insulating film formed on an entire surface of the substrate including the semiconductor layer; A gate line formed in a predetermined region on the gate insulating film; The thin film transistor of claim 6, wherein the thin film transistor includes a relatively large dummy pattern protruding from the semiconductor layer at a predetermined interval from the gate line in the semiconductor layer overlapping the gate line.