KR20040045113A - Liquid Crystal Display device and Method for manufacturing at the same - Google Patents

Abstract

PURPOSE: An LCD(Liquid Crystal Display) and a manufacturing method thereof are provided to reduce manufacturing processes by forming a data line, a gate line and a storage line at the same layer, thereby capable of increasing the productivity. CONSTITUTION: Plural gate lines(101) and data lines(102) for defining a pixel region are formed lengthwise and crosswise. A pixel electrode(108) is formed at the pixel region. A storage line(103) and a storage electrode(103a) are formed with a constant distance toward the same direction as that of the gate line(101). An active layer(105) is overlapped with the storage electrode(103a). A thin film transistor(104) switches a voltage applied to the pixel electrode(108). A material for connecting the gate line(101) with a portion crossing the data line(102) and the storage line(103), and a source electrode's material for connecting the data line(102) with the active layer(105) are all transparent conductive materials which are the same as that of the pixel electrode(108).

Description

Liquid crystal display device and method for manufacturing at the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method for manufacturing the same, and more particularly, to a liquid crystal display device and a method for manufacturing the same that form a data line, a gate line and a storage line on the same layer to shorten a manufacturing process. .

BACKGROUND ART In general, liquid crystal displays are widely used as displays that can be miniaturized, lightweight, and thin. Such liquid crystal display devices have a high contrast ratio, are suitable for gray scale display or moving image display, and have low power consumption. It is expanding.

Such a liquid crystal display may be formed in various forms. Currently, an active matrix LCD (AM-LCD) having a thin film transistor and a pixel electrode connected to the thin film transistor is arranged in a matrix manner. And it is attracting the most attention because of its ability to implement video.

The liquid crystal display device has a structure in which a pixel electrode is formed on a lower substrate, and a common electrode is formed on an upper substrate, and the liquid crystal molecules are driven by an electric field perpendicular to the substrate applied between the two electrodes.

Hereinafter, a liquid crystal display of the prior art will be described in detail with reference to the accompanying drawings.

1 is a plan view of a liquid crystal display according to the related art, and FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

As shown in FIG. 1, the liquid crystal display according to the related art includes a plurality of gate lines 1 and data lines 2 perpendicular to each other to define pixel regions arranged in a matrix form, and the gate lines 1. The storage line 20 formed to be parallel to the pixel line, the pixel electrode 8 formed in the pixel region, and the gate line 1 and the data line 2 intersecting each other. And a plurality of thin film transistors 7 which are switched in accordance with a driving signal of the signal line and apply the signal of the data line 2 to the pixel electrode 8.

Here, the gate line 1 and the data line 2 are made of a translucent metal of an aluminum compound to reduce electrical resistance, and the pixel electrode 8 is made of a transparent metal having good light transmittance.

The thin film transistor 7 includes an impurity region electrically connected to the gate line 1 used as a gate electrode, the source electrode 16a connected to the data line 2, and the data line 2. (Not shown) and an active layer (not shown) having a channel region (not shown) overlapping the gate line 1 and another impurity region of the active layer corresponding to the data line 2. It comprises a drain electrode (16b) connected to.

Meanwhile, the cross-sectional structure of the liquid crystal display according to the related art is a buffer layer 11 of a silicon oxide film formed on the lower substrate 10 and a thin film transistor on the buffer layer 11 as shown in FIG. 2. An active layer 12 formed in an island shape in a portion where 7 of 1 is formed, a gate insulating film 13 formed on the entire surface of the substrate including the active layer 12, and a gate line formed in one direction on the gate insulating film 13. (1), a lower substrate 10 including first and second impurity regions 12a and 12b formed in the active layers 12 on both sides of the gate line 1, and the gate line 1. ), An interlayer insulating layer 15 formed on the entire surface of the semiconductor layer, a first contact hole 19a formed to expose a predetermined portion of the surfaces of the first and second impurity regions 12a and 12b, and the first contact. Formed to be electrically connected to the first and second impurity regions 12a and 12b through a hole 19a. A passivation layer 17 formed on the entire surface of the lower substrate 10 including the data line 2 and the drain electrode 16b, the drain electrode 16b, and a surface of the drain electrode 16b. A pixel electrode 8 formed to be electrically connected to the drain electrode 16b through a second contact hole 19b, the second contact hole 19b, and a first alignment layer formed on the pixel electrode 8; It consists of 21a.

In this case, a portion of the gate line 1 formed on the lower substrate 10, an active layer 12, a portion of the data line 2, and a drain electrode 16b may be formed of a thin film transistor (FIG. 7) (Thin Film). Transistor (TFT) is configured.

In addition, on the upper substrate 22 facing the lower substrate 10, the first substrate 22 is formed to prevent light from being transmitted from portions corresponding to the gate line 1, the data line 2, and the thin film transistor 7. The light blocking film 23 and the color filter layer 24 formed to overlap the light blocking film 23 corresponding to each pixel region to realize color, and the common electrode formed on the color filter layer 24 and the light blocking film 23. And a second alignment layer 21b formed on the common electrode 25 for regular arrangement of the liquid crystals.

Although not shown, a spacer is formed between the lower substrate 10 and the upper substrate 22 so that the lower substrate 10 and the upper substrate 22 maintain a constant gap, and the thin film transistor 7 A liquid crystal layer is formed between the two substrates to control the transmission of light by varying the arrangement by application of voltage of the pixel electrode 8 according to driving of the < RTI ID = 0.0 >

The manufacturing method of the lower substrate of the liquid crystal display according to the related art configured as described above is as follows.

3A to 3H are cross-sectional views of manufacturing a liquid crystal display device according to the prior art.

First, as shown in FIG. 3A, a buffer layer 11 is formed on the lower substrate 10 using an insulating material such as silicon oxide, and an amorphous silicon layer is formed on the buffer layer 11 by using a low temperature CVD deposition method. After forming (not shown), the amorphous silicon layer is crystallized into the polycrystalline silicon layer 11a using an excimer laser or the like.

As shown in FIG. 3B, the crystallized polycrystalline silicon layer 11a is patterned through photo printing and etching to form an active layer 12.

Next, as shown in FIG. 3C, a gate insulating layer 13 is formed on the lower substrate 10 including the active layer 12, a metal layer is deposited on the gate insulating layer 13, and the metal layer is formed on the active layer 12. The gate insulating film 13 is patterned to form the gate line 1.

In this case, the storage electrode 18 and the storage line 20 are simultaneously formed in parallel with the gate line 1.

As shown in FIG. 3D, impurities (for example, Phosphorus or Boron) ions are implanted into the entire surface of the lower substrate 10 using the gate line 1 as a mask so that both sides of the gate line 1 are implanted. First and second impurity regions 12a and 12b are formed in the active layer 12.

In this case, since the first and second impurity regions 12a and 12b doped by the ion implantation method are easily damaged by the ions, the surface and the bulk layer of the active layer 12 may be amorphous. It may be activated using excimer laser light or heat for stabilization and crystallization of the surface and bulk layer.

As shown in FIG. 3E, an interlayer insulating layer 15 is formed on the lower substrate 10 including the gate line 1, and the surfaces of the first and second impurity regions 12a and 12b have a predetermined portion. The interlayer insulating layer 15 and the gate insulating layer 13 are selectively patterned to expose the first contact hole 19a.

Next, as illustrated in FIG. 3F, a conductive metal layer is formed on the lower substrate 10 including the interlayer insulating layer 15, and the patterned conductive metal layer is selectively patterned through photo printing and etching to form the first contact hole ( The data line 2 and the drain electrode 16b are formed in electrical contact with the first and second impurity regions 12a and 12b through 19a.

In this case, a portion of the data line 2 electrically connected to the first impurity region 12a is used as the source electrode 16a.

As shown in FIG. 3G, a passivation layer 17 is formed on the lower substrate 10 including the data line 2, and the passivation layer 17 is selectively exposed to expose a portion of the surface of the drain electrode 16b. To form a second contact hole 19b.

As shown in FIG. 3H, a pixel is formed on the lower substrate 10 on which the passivation layer 17 is formed, and the pixel is connected to the drain electrode 16b by selectively removing the transparent conductive metal through a photo printing and etching process. The electrode 8 is formed. Finally, although not shown, the first alignment layer 21a is formed on the lower substrate 10 on which the pixel electrode is formed.

As a result, the lower substrate 10 of the liquid crystal display according to the related art includes a buffer layer 11, an active layer 12, a gate line 1 and a storage line 20, a first contact hole 19a, and a data line 2. And at least six photo masks are used to pattern the drain electrode 16b, the second contact hole 19b and the pixel electrode 8.

That is, since the gate line and the data line are not formed in the same layer but are formed in different layers with the interlayer insulating film interposed therebetween, the number of masks used for patterning increases and productivity is lowered.

The present invention has been made to solve the above problems, the data line, the gate line and the storage line is formed on the same layer, the connection portion of the gate line and the storage line of the portion (hole) intersecting the data line pixel electrode It is an object of the present invention to provide a liquid crystal display device and a method for manufacturing the same, which can increase productivity by simultaneously forming the same.

1 is a plan view of a liquid crystal display according to the prior art.

2 is a cross-sectional view taken along line II ′ of FIG. 1.

3A to 3H are cross-sectional views of manufacturing a liquid crystal display device according to the prior art.

4 is a plan view of a liquid crystal display according to the present invention.

5 is a cross-sectional view taken along line II-II 'of FIG. 4 of the liquid crystal display according to the first embodiment of the present invention.

6A to 6D are plan views illustrating the lower substrate of the liquid crystal display according to the first exemplary embodiment of the present invention, and FIGS. 7A to 7E are cross-sectional views of the manufacturing process of FIG.

* Description of the main parts of the drawings *

100: lower substrate 101: gate line

102: data line 103: storage line

103a: storage electrode 104: thin film transistor

105: active layer 106: buffer layer

107 gate insulating film 108 pixel electrode

109: protective film 110: contact hole

111a: source electrode 111b: drain electrode

113: upper substrate 114: light shielding film

115: color filter 116: common electrode

The liquid crystal display device of the present invention for achieving the above object has a buffer layer formed on a substrate, an active layer formed on the buffer layer, a gate insulating film formed on a substrate including the active layer, and one direction on the gate insulating film A gate line and a storage line formed to disconnect the data line to be formed and a portion crossing the data line, first and second impurity regions formed in the active layers on both sides of the gate line, the first and second impurity regions, A passivation layer formed to have a plurality of contact holes exposing predetermined portions of the data line, the gate line, and the storage line, a source electrode connected to the first impurity region and the data line through the contact hole, and the disconnected gate line. A gate connection for connecting and a storage connection for connecting the disconnected storage line Unit, the second is configured to include a drain electrode and a pixel electrode connected to the impurity region.

The liquid crystal display according to claim 1, wherein the source electrode, the gate connection part, the storage connection part, the drain electrode, and the pixel electrode are made of a transparent conductive metal.

In addition, another aspect of the present invention is to form a buffer layer on a substrate, to form an active layer on the buffer layer, to form a gate insulating film on the entire surface of the substrate including the active layer, the gate insulating film on Simultaneously forming a data line in one direction, a gate line and a storage line in which a portion crossing the data line is disconnected, and forming first and second impurity regions in the active layers on both sides of the gate line; Forming a passivation layer on the entire surface of the substrate including the gate line; and selectively removing the passivation layer to expose a predetermined portion of the first and second impurity regions, the data line, the gate line, and the storage line. Forming a gap between the first impurity region and the data line through the contact hole; And simultaneously forming a source electrode, a gate connection part connecting the disconnected gate line, a storage connection part connecting the disconnected storage line, a drain electrode connected to the second impurity region, and a pixel electrode.

Hereinafter, a liquid crystal display and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a plan view of a liquid crystal display according to the present invention.

As shown in FIG. 4, the liquid crystal display of the present invention includes a plurality of gate lines 101 and data lines 102 formed vertically and horizontally to define a pixel region, and a pixel electrode 108 formed in the pixel region. And a storage line 103 and a storage electrode 103a formed at regular intervals in the same direction as the gate line 101, and an active layer 105 overlapping the storage electrode 103a. And a thin film transistor 104 for switching a voltage applied to the 108.

Here, a material connecting each of the gate line 101 and the storage line 103 at the portion crossing the data line 102 and a source electrode for connecting the data line 102 and the active layer 105 to each other. The material of 111a is the same transparent conductive material as the pixel electrode 108.

That is, although not shown, the gate line 101 and the storage line 103 which are separated from the data line 102 are formed at the same time as the pixel electrode 108 and through the respective contact holes (not shown). At each intersection with the data line 102, each contact hole is connected to each other in the shape of a stepping bridge.

In addition, the data line 102 and the active layer 105 do not overlap to remove the gate insulating layer (not shown) formed between the two layers in the cross-sectional structure of the data line 102 and the active layer 105. After the separation, the layers on the data line 102 and the active layer 105 are removed to form respective contact holes, and then connected to each other using the same material as the pixel electrode 108.

5 is a cross-sectional view taken along the line II-II 'of 4;

As shown in FIG. 5, in the liquid crystal display of the present invention, a buffer layer 106 of a silicon oxide film formed on the lower substrate 100 and an active layer 105 formed of island-like polycrystalline silicon are formed on the buffer layer. have.

In addition, the gate insulating film 107 formed on the entire surface of the lower substrate 100 including the active layer 105, the gate line 101 and the storage electrode 103a formed at regular intervals on the gate insulating film 107. ) And data lines 102 are formed.

In addition, the passivation layer 109 formed on the lower substrate 100 including the data line 102, the gate line 101, and the storage line 103, and the data on the data line 102 and the active layer 105. A source electrode 111a electrically connected to the passivation layer 109 and the gate insulating layer 107 through an etched contact hole 110, and a drain corresponding to the source electrode 111a around the gate line 101. A pixel electrode 112 is formed to be electrically connected to the protective layer 109 and the gate insulating layer 107 on the active layer 105 through the etched contact hole 110.

Although not shown, the gate line 101 and the storage line 103 intersecting the data line 102 are made of a material formed simultaneously with the pixel electrode 108 through the contact hole 110, and are connected to each other. have.

In addition, a light blocking film 114 on the upper substrate 113 facing the lower substrate 100, a color filter 115 for implementing RGB color on the light blocking film 114, and the color filter 115. The common electrode 116 is formed thereon.

Further, respective alignment layers are further formed on the pixel electrode 108 of the lower substrate 100 and the common electrode 116 of the upper substrate 113.

Here, the data line 102, the gate line 101, and the storage electrode 103a are all formed on the same layer, and thus the stepped source electrode connecting the data line 102 and the active layer 105 to each other is formed. 111a is formed of the same material as the pixel electrode 108 such as indium tin oxide (ITO).

In this case, the contact resistance of the data line 102, the gate line 101, the storage line 103, and the active layer 105 in contact with the material forming the pixel electrode 108 should be low.

In addition, the active layer 105 in the portion where the source electrode 111a and the drain electrode 111b are formed should be impurity regions 105a and 105b by ion implantation.

Therefore, in order to form impurity regions corresponding to both sides of the gate line 101, impurities must be implanted onto the lower substrate 100 using the gate line 101 as a mask, so that the gate line 101 is formed. And the data line 102 formed at the same time as or partially overlap the active layer 105.

As a result, the impurity region 105a in which impurities are injected into the data line 102 and the active layer 105 is connected to each other by the source electrode 111a which is simultaneously formed with the pixel electrode 112.

In addition, the data line 102, the gate line 101, and the storage electrode 103a are all formed on the same layer, so that the gate line 101 and the storage line (FIG. 3) intersect the data line 102. A gate connection portion 120 and a storage connection portion 121 that connect each of 103 to 4 are formed.

Looking at the manufacturing process of the liquid crystal display according to the present invention having such a configuration as follows.

6A to 6D are plan views illustrating the lower substrate of the liquid crystal display device of the present invention, and FIGS. 7A to 7E are cross-sectional views of the manufacturing process.

First, as shown in FIG. 7A, a buffer layer 106 is formed on the lower substrate 100 using silicon oxide, amorphous silicon is deposited on the buffer layer 106, and then polycrystalline silicon 106a is formed using an excimer laser or the like. Crystallize

At this time, excimer laser light is irradiated in the direction of the arrow.

6A or 7B, the polycrystalline silicon (106a of FIG. 6A) is selectively removed through photo printing and etching to form an active layer 105.

As shown in FIG. 6B or 7C, the gate insulating layer 107 is formed on the entire surface of the lower substrate 100 on which the active layer 105 is formed, and the conductivity is excellent on the lower substrate 100 on which the gate insulating layer 107 is formed. A metal layer (not shown) is formed by using an aluminum-based metal, and the metal layer is selectively removed through a photo printing and etching process so that the storage electrodes 103a and the data lines are spaced apart from each other on the gate insulating layer 107. 102 and the gate line 101 are formed.

In this case, the gate line 101 and the storage line 103 of the portion crossing the data line 102 are disconnected from the portion of the gate line 101 and the storage line 103.

Next, impurity ions are implanted using the gate line 101 as a mask to form first and second impurity regions 105a and 105b in the active layer 105 at both sides of the gate line 101.

As shown in FIG. 6C or 7D, the passivation layer 109 is formed on the lower substrate 100 including the gate line 101, and the data line 102 and the gate line 101 intersect the data line 102. ) And the passivation layer 109 and the gate insulating layer 107 so that the disconnection portion of the storage line 103 and the surfaces of the first and second impurity regions 105a and 105b of the active layer 105 are partially exposed. To form a contact hole 110.

6D or 7E, after the transparent conductive metal such as ITO is formed on the entire surface of the lower substrate 100 on which the passivation layer 109 including the contact hole 110 is formed, the data line 102 and the first line are formed. A source electrode 111a connecting the impurity region 105a and a gate connection portion 120 and a storage connection portion 121 connecting the gate line 101 and the storage line 103 to each other so as to intersect the data line 102. ) And a drain electrode 111b and a pixel electrode 108 connected to the second impurity region 105b.

Here, the drain electrode 111b and the pixel electrode 108 are integrated.

In this case, the manufacturing method of the liquid crystal display according to the present invention may include forming the active layer 105, forming the data line 102, the gate line 101 and the storage line 103, and forming the contact hole 110. Formation and four patterning operations are required according to the formation of the source electrode 111a, the gate connector 120 and the storage connector 121, the drain electrode 111b and the pixel electrode 108.

Accordingly, in the method of manufacturing the liquid crystal display according to the present invention, the data line 102, the gate line 101, and the storage line 103 are all formed on the same layer by using a top gate method, thereby using four patterning masks. Since the manufacturing cost can be reduced by patterning the substrate 100, productivity can be improved.

As described above, the liquid crystal display of the present invention and its manufacturing method have the following effects.

The liquid crystal display of the present invention and its manufacturing method can increase productivity because data lines, gate lines, and storage lines can be formed on the same layer to reduce the manufacturing process.

Claims (5)

A buffer layer formed on the substrate, An active layer on the buffer layer, A gate insulating film formed on the substrate including the active layer; A gate line and a storage line formed to have a data line formed in one direction on the gate insulating layer and a portion crossing the data line disconnected; First and second impurity regions formed in the active layer on both sides of the gate line; A protective film formed to have a plurality of contact holes through which the first and second impurity regions and predetermined portions of the data line, the gate line, and the storage line are exposed; A source electrode connected to the first impurity region and the data line through the contact hole, a gate connector connecting the disconnected gate line, a storage connector connecting the disconnected storage line, and a second impurity region. And a drain electrode and a pixel electrode. The method of claim 1, The source electrode, the gate connection part, the storage connection part, the drain electrode, and the pixel electrode are made of a transparent conductive metal. The method of claim 2, And the transparent conductive metal is ITO. Forming a buffer layer on the substrate, Forming an active layer on the buffer layer; Forming a gate insulating film on the entire surface of the substrate including the active layer; Simultaneously forming a data line in one direction and a gate line and a storage line in which a portion crossing the data line is disconnected; Forming first and second impurity regions in the active layer on both sides of the gate line; Forming a protective film on an entire surface of the substrate including the gate line; Forming a plurality of contact holes by selectively removing the passivation layer so that predetermined portions of the first and second impurity regions, data lines, gate lines, and storage lines are exposed; A source electrode connected to the first impurity region and the data line through the contact hole, a gate connection portion connecting the disconnected gate line, a storage connection portion connecting the disconnected storage line, and a second impurity region. And forming a drain electrode and a pixel electrode at the same time. The method of claim 4, wherein The source electrode, the gate connection part, the storage connection part, the drain electrode, and the pixel electrode are formed of a transparent conductive metal.