KR100517594B1 - Thin film transistor substrate for liquid crystal display (LCD) and Method of manufacturing the same - Google Patents

Abstract

Disclosed is a thin film transistor substrate for a liquid crystal display device which prevents an increase in defective pixels due to disconnection of a gate line by allowing a black matrix connected through the gate line and a contact hole to take the role of a gate line when the gate line is disconnected. The thin film transistor substrate is formed between adjacent unit pixels on the transparent insulating substrate, and prevents light leakage between the unit pixels, a first oxide film formed on the black matrix, and an active polycrystal formed in an active region on the first oxide film. A second oxide film formed on the resulting substrate comprising a silicon layer pattern, an active polycrystalline silicon layer pattern and including a first contact hole exposing a predetermined portion of the black matrix, a first oxide formed in a predetermined portion of the second oxide film A third oxide film including a gate line electrically contacting the black matrix through the hole, a third oxide film formed on the resulting substrate including the gate line, a data line formed on the third oxide film and orthogonal to the gate line, and a data line. And a pixel electrode formed on the planarization film.

Description

Thin film transistor substrate and liquid crystal display (LCD) and method of manufacturing the same

The present invention relates to a thin film transistor substrate and a method of manufacturing the same, and more particularly to a thin film transistor substrate for a liquid crystal display device for forming a black matrix layer formed on the thin film transistor substrate and a gate line formed thereon using the same mask; It relates to a manufacturing method.

In today's information society, the role of electronic display devices becomes more and more important, and various electronic display devices are widely used in various industrial fields.

In general, an electronic display device refers to a device that transmits various information to a human through vision. That is, an electronic display device may be defined as an electronic device that converts electrical information signals output from various electronic devices into optical information signals that can be recognized by a human vision, and plays a role of a bridge between humans and electronic devices. It may be defined as.

In such an electronic display device, when an optical information signal is displayed by a light emitting phenomenon, it is called an emissive display device, and when the information is displayed by light modulation by reflection, scattering, interference, or the like. It is called a non-emissive display device.

Light emitting displays, also called active display devices, include cathode ray tubes (CRTs), plasma display panels (PDPs), light emitting diodes (LEDs), and electroluminescent displays (electroluminescent displays). And ELD). In addition, the light receiving display device, which is a passive display device, includes a liquid crystal display (LCD), an electrochemical display (ECD), an electrophoretic image display (EPID), and the like.

Cathode ray tubes (CRTs) used in image display devices such as televisions and computer monitors occupy the highest share in terms of display quality and economy, but have many disadvantages such as heavy weight, large volume and high power consumption. .

However, due to the rapid progress of semiconductor technology, the electronic display device suitable for the new environment, that is, the thin and light, the low driving voltage and the low power consumption of the electronic device, according to the miniaturization, low voltage and low power of various electronic devices, and the miniaturization and light weight of the electronic device, The demand for flat panel display devices with features is rapidly increasing.

Among the various flat panel display devices currently developed, liquid crystal displays are thinner and lighter than other display devices, have low power consumption and low driving voltage, and are widely used in various electronic devices because they can display images close to cathode ray tubes. Is being used.

A liquid crystal display is composed of two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and a display for controlling the amount of light transmitted by rearranging liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. Device.

Among the liquid crystal display devices currently used, a device including a thin film transistor that has electrodes formed on two substrates and switches voltage applied to each electrode, and the thin film transistor is generally formed on one of two substrates to be.

As the resolution of the liquid crystal display panel increases, the redundancy of the gate line also increases. However, the increase in redundancy increases the possibility of causing disconnection of the gate line, and as a result, generation of defective pixels can be caused.

Accordingly, the present invention was derived to solve the above problems, and an object of the present invention is to allow a black matrix connected through a gate line and a contact hole to take the role of a gate line when the gate line is disconnected. This is to prevent the increase of defective pixels due to disconnection.

Another object of the present invention is to maintain a good interface between the gate pattern and the gate insulating film.

In order to achieve the above object, the thin film transistor substrate of the present invention comprises: a black matrix formed between adjacent unit pixels on the transparent insulating substrate, and preventing light leakage between the unit pixels; A first oxide film formed on the black matrix; An active polycrystalline silicon layer pattern formed in the active region on the first oxide film; A second oxide film formed on the resulting substrate including the active polycrystalline silicon layer pattern, the second oxide film including a first contact hole exposing a predetermined portion of the black matrix; A gate line formed in a predetermined portion of the second oxide film and electrically contacting the black matrix through the first contact hole; A third oxide film formed on the resulting substrate including a gate line; A data line formed over the third oxide film and orthogonal to the gate line; A planarization film formed on the third oxide film including a data line; And a pixel electrode formed on the planarization film.

Preferably, the black matrix and the gate pattern have the same pattern shape.

Further, preferably, the thickness of the first oxide film is the same as the thickness of the second oxide film formed on the active polycrystalline silicon layer.

Preferably, any one of the gate pattern and the black matrix pattern may be formed in an island structure.

According to another aspect of the present invention for achieving the above object, there is provided a method of manufacturing a thin film transistor substrate for a liquid crystal display device. The method includes forming a black matrix formed between adjacent unit pixels on the transparent insulating substrate to prevent light leakage between the unit pixels; Forming a first oxide film on the black matrix; Forming an active polycrystalline silicon layer pattern in an active region on the first oxide film; Forming a second oxide film on the exposed surface of the active polycrystalline silicon layer pattern; Forming a first contact hole exposing the black matrix in a predetermined portion of the second oxide film; Forming a gate pattern on a predetermined portion of the first contact hole and the second oxide film; Forming a third oxide film on the resulting substrate including the gate pattern; Forming a second contact hole in a predetermined portion of the third oxide film to expose a predetermined portion of the active layer pattern; Forming a data line in a predetermined portion of the second contact hole and the third oxide film; Forming a planarization film over the third oxide film including the data line; Forming a pixel electrode on the planarization layer.

Preferably, the black matrix and the gate pattern are formed using the same mask.

According to still another aspect of the present invention, a thin film transistor substrate for a liquid crystal display device includes: a black matrix formed between adjacent unit pixels on a translucent insulating substrate to prevent light leakage between the unit pixels; A first oxide film formed on the black matrix and having a first contact hole exposing a predetermined portion of the black matrix; An active polycrystalline silicon layer pattern including a first active polycrystalline silicon layer pattern formed in an active region on the first oxide layer and a second active polycrystalline silicon layer pattern formed in the first contact hole and in contact with the black matrix; A second oxide film formed on the active polycrystalline silicon layer pattern; A gate line formed on a predetermined portion of the second oxide film; A third oxide film formed on the resulting substrate including the gate line; Data formed on the third oxide layer, perpendicular to the gate line, and in contact with the source region of the first active polycrystalline silicon layer pattern through a second contact hole formed in the third oxide layer and the second oxide layer below the third oxide layer. line; A third contact hole formed on the third oxide film and formed in the third oxide film on the gate line and a fourth contact hole formed in the third oxide film on the second active polycrystalline silicon layer pattern and a second oxide film below A metal pattern electrically connecting the gate line and the second active polycrystalline silicon layer pattern to each other; A planarization film formed on the third oxide film including the data line; And a pixel electrode formed on the planarization film.

Preferably, the gate line has a structure jumped by an island structure or a metal line.

According to another aspect of the present invention for achieving the above object, a method of manufacturing a thin film transistor substrate for a liquid crystal display device is formed between adjacent unit pixels on the transparent insulating substrate, to prevent light leakage between the unit pixels Forming a black matrix: forming a first oxide film on the black matrix; Forming a first contact hole exposing a portion of the black matrix; Forming a first active polycrystalline silicon layer pattern in an active region on the first oxide layer and a second active polycrystalline silicon layer pattern in contact with the black matrix in the first contact hole; Forming a second oxide film on the first active polycrystalline silicon layer pattern and the second active polycrystalline silicon layer pattern; Forming a gate pattern on a predetermined portion of the second oxide film; Forming a third oxide film on the resulting substrate including the gate pattern; A second contact hole exposing a source region of the active polysilicon layer pattern to the third oxide film and a second oxide film under the third oxide film, a third contact hole exposing a predetermined portion of the gate pattern, and the second active polycrystalline silicon Forming a fourth contact hole exposing a predetermined portion of the layer pattern; A first data pattern contacting the source region through the second contact hole on the third oxide layer, and connecting the gate pattern and the second active polycrystalline silicon layer pattern through the third and fourth contact holes Forming a data pattern; Forming a planarization layer on the third oxide layer including the first and second data patterns; Forming a pixel electrode on the planarization layer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example 1

1 to 3 are plan views illustrating a method of manufacturing a thin film transistor substrate for a liquid crystal display according to a preferred embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along the line 4-4 'of FIG. 3.

Referring to FIG. 1, a lower black matrix pattern 102 is formed on a light transmissive insulating substrate 100 such as quartz (SiO ₂ ) or glass by one side of a boundary line of a unit pixel region through a conventional photolithography process. (First mask).

Optionally, the black matrix pattern 102 is formed continuously without being separated for each unit pixel region.

As the first oxide film 104, a high temperature oxide (HTO) is formed on the entire surface of the substrate 100 including the black matrix pattern.

Referring to FIG. 2, an active layer pattern 106 is formed on the top surface of the first oxide film 104. That is, a heavily doped polysilicon pattern 106 doped with a high concentration of impurities so as to partially overlap the black matrix pattern 102 of the unit pixel region is formed through a conventional photolithography process (second mask).

The active layer pattern 106 is formed for each unit pixel region.

As the active layer pattern 106, amorphous silicon may be used instead of polycrystalline silicon doped with the above-mentioned impurities in high concentration. The active layer pattern 106 includes a source region, a drain region, and a channel region. The source and drain regions are formed by implanting pentavalent or trivalent impurity ions using ion implantation or doping. Fourth mask). When the ion implantation method is applied, the gate line to be described later functions as an ion implantation mask.

Optionally, the active layer 106 may have a lightly doped drain (LDD) structure.

Then, a silicon oxide film, which is the second oxide film 108, is formed on the resulting substrate including the active layer pattern 106.

Next, as shown in FIG. 3, at least one first contact hole C1, C2 is formed in the second oxide layer 108 to electrically connect the black matrix pattern 102 and the active layer pattern 106. (Fifth mask). The contact hole is formed to be located above the black matrix 102.

Preferably, the second oxide film 108 formed on the active polycrystalline silicon layer 106 may be formed to have the same thickness as the first oxide film 104.

Next, a gate pattern 110 is formed on the second oxide film 108 including the first contact hole (sixth mask). The gate pattern 110 is formed by depositing and patterning a polycrystalline silicon film or metal doped with impurities. Since the gate pattern 110 is patterned by a conventional photolithography process using a second mask used to form the black matrix 102, the gate pattern 110 is formed in the same pattern as the black matrix pattern 102.

The gate pattern 110 includes a gate line arranged along the transverse direction of the drawing, and a gate electrode branched from the gate line and overlapping the channel region of the active layer pattern 106.

Alternatively, optionally one of the gate pattern 110 and the black matrix pattern 102 may be formed in an island structure.

Next, a third oxide film 112 is formed on the entire surface of the resulting substrate including the gate pattern 110.

Then, a second contact hole exposing a predetermined portion of the third oxide film 112, that is, the source region of the active layer pattern 106, is formed (seventh mask).

Next, a metal film for data lines is deposited to a predetermined thickness on the entire surface of the third oxide film 112 including the second contact hole. This data line metal film is patterned by a normal photolithography process to form a data line (not shown) (eighth mask).

Next, a planarization film is formed on the third oxide film 112 including the data line. A third contact hole (not shown) for exposing the drain region of the active layer pattern is formed in the planarization layer through a normal photolithography process (ninth mask).

Meanwhile, the pixel region is defined by the formation of the gate line and the data line 118 described above. In order to form a pixel electrode in a defined pixel region, a transparent conductive film such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited to a predetermined thickness on the entire surface of the resulting substrate. The deposited conductive film is patterned to form a pixel electrode contacting the drain electrode through the third contact hole.

In the thin film transistor substrate formed through the above process, the active layer pattern 106 and the pixel electrode have a data potential input through the data line, and since the black matrix pattern 102 is connected with the gate line, it has a gate potential. .

Example 2

5 is a cross-sectional view illustrating a structure and a manufacturing method of a thin film transistor substrate for a liquid crystal display according to another exemplary embodiment of the present invention.

Referring to FIG. 5, a black matrix 202 is positioned to prevent light leakage between unit pixels along one direction on the transparent insulating substrate 200.

The first oxide film 204 is disposed on the black matrix 202. The first oxide film 204 has a first contact hole 206 exposing a predetermined portion of the black matrix 202.

The first active polycrystalline silicon layer pattern 208 and the second active polycrystalline silicon layer pattern 210 are positioned on the first oxide film 204. The first active polycrystalline silicon layer pattern 208 is positioned in the active region, and the second active polycrystalline silicon layer pattern 210 is placed in contact with the first contact hole 206 and the black matrix 202. The first active polycrystalline silicon layer pattern 211 includes a source region and a drain region.

Second oxide layers 212 and 214 are positioned on the first and second active polycrystalline silicon layer patterns 208 and 210. The gate pattern 216 is positioned on a predetermined portion of the second oxide films 212 and 214. The gate pattern 216 includes a gate line arranged along the transverse direction of the drawing, and a gate electrode branched from the gate line and overlapping a channel region of the first active polycrystalline silicon layer pattern 208. Optionally, the gate line may have an island structure or may have a structure that is jumped by a metal wire.

The third oxide film 218 is positioned on the resulting substrate including the gate pattern 216.

The first data pattern 226 is positioned on the third oxide film 218. The first data pattern 226 is orthogonal to the gate pattern 216, and the first active polycrystalline silicon is formed through the second contact hole 220 formed in the third oxide film 218 and the second oxide film 212 below. The source region of the layer pattern 208 is contacted. The first data pattern 226 includes a source electrode formed over the first active polycrystalline silicon layer pattern and a data line perpendicular to the gate line.

In addition, the second data pattern 228 is placed on the third oxide film 218. The second data pattern 228 may include a third contact hole 222 formed in the third oxide film 218, a third oxide film 218 on the second active polycrystalline silicon layer pattern 210, and a second oxide film below the second data pattern 218. The gate line 216 and the second active polycrystalline silicon layer pattern 210 are electrically connected to each other through the fourth contact hole 224 formed in 214. The black matrix 202 is electrically connected to the gate pattern 216, that is, the gate line, by the second data pattern 228 and the second active polycrystalline silicon layer pattern 210.

A passivation film 230 is positioned on the third oxide film 218 including the first and second data patterns 226 and 228. The pixel electrode 232 is positioned on the planarization layer 230.

The manufacturing method of the thin film transistor substrate for a liquid crystal display device having the above structure is as follows.

The lower black matrix pattern 202 is formed through a conventional photolithography process so as to be arranged on one side of the boundary line of the unit pixel region on the transparent insulating substrate 200 such as quartz (SiO ₂ ) or glass.

Optionally, the black matrix pattern 202 is formed continuously without being separated for each unit pixel region.

As the first oxide film 204, a high temperature oxide (HTO) is formed on the entire surface of the substrate 200 including the black matrix pattern 202.

Next, the first contact hole 206 is formed through a normal photolithography process.

First and second active layer patterns 208 and 210 are formed on an upper surface of the first oxide layer 204 including the first contact hole 206. That is, polycrystalline silicon (Heavily doped polysilicon) patterns 208 and 210 doped with a high concentration of impurities so as to partially overlap the black matrix pattern 202 of the unit pixel region are formed through a conventional photolithography process.

The first and second active polysilicon layer patterns 208 and 210 are formed for each unit pixel region.

As the first and second active polysilicon layer patterns 208 and 210, amorphous silicon may be used instead of polycrystalline silicon doped with the above-mentioned impurities. The first active polysilicon layer pattern 208 includes a source region, a drain region, and a channel region, and the source and drain regions are formed by implanting pentavalent or trivalent impurity ions using an ion implantation method or a doping method. do. When the ion implantation method is applied, the gate line to be described later functions as an ion implantation mask.

Optionally, the first and second active polysilicon layer patterns 208 and 210 may have a lightly doped drain (LDD) structure.

Next, silicon oxide films, which are second oxide films 212 and 214, are formed on the first and second active polysilicon layer patterns 208 and 210. The second oxide films 212 and 214 are formed only on the corresponding first and second active polysilicon layer patterns 208 and 210.

Next, a gate pattern 216 is formed on a predetermined portion on the second oxide film 212. The gate pattern 216 is formed by depositing and patterning a polycrystalline silicon film or metal doped with impurities. The gate pattern 216 is patterned by a conventional photolithography process using a mask used to form the black matrix 202, so that the gate pattern 216 has the same pattern as the black matrix pattern 202.

Next, a third oxide film 218 is formed on the entire surface of the resulting substrate including the gate pattern 216.

Then, the second contact hole 220 exposing a predetermined portion of the third oxide film 218 and / or the second oxide film 212 or 214, that is, the source region of the first active polysilicon layer pattern 208; The third contact hole 222 exposing a predetermined portion of the gate pattern 216 and the fourth contact hole 224 exposing a predetermined portion of the second active polysilicon layer pattern 210 are formed.

Next, a metal layer for data pattern is deposited on the entire surface of the third oxide layer 230 including the second, third, and fourth contact holes 220, 222, and 224. The data pattern metal film is patterned by a normal photolithography process to form a first data pattern 226 and a second data pattern 228. Due to the formation of the second data pattern 228, the gate pattern 216 is electrically connected to the black matrix 202.

Next, the planarization film 230 is formed on the third oxide film 218 including the first and second data patterns. A fifth contact hole (not shown) is formed in the planarization layer 230 to expose a drain region of the first active polysilicon layer pattern through a normal photolithography process.

Meanwhile, the pixel region is defined by the formation of the gate line and the data line described above. In order to form a pixel electrode in a defined pixel region, a transparent conductive film such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited to a predetermined thickness on the entire surface of the resulting substrate. The deposited conductive film is patterned to form a pixel electrode contacting the drain electrode through the fifth contact hole.

In the thin film transistor substrate formed through the above-described process, the first active polysilicon layer pattern 208 and the pixel electrode 232 have a data potential input through the data line, and the black matrix pattern 202 is connected to the gate line. Since it is connected, it has a gate potential.

In addition, since the first embodiment performs a photolithography process to form contact holes in the black matrix before deposition of the gate pattern, there is a possibility of contamination by impurities or the like at the interface between the gate pattern and the gate insulating film. An example can keep the interface state between the gate pattern and the gate insulating film satisfactorily.

As described above, according to the present invention, since the black matrix has the same pattern as the gate pattern, defects caused by the opening of the gate line can be reduced. In addition, since the black matrix and the gate pattern are formed using the same mask, it is possible to improve the yield.

In addition, it is possible to obtain an effect that the channel region is formed in the active layer through the oxide layer which is in contact with the black matrix instead of the black matrix.

Although the present invention has been described with reference to the preferred embodiments, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. I can understand.

1 to 3 are plan views illustrating a manufacturing process of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a cross-sectional view taken along line 4-4 'of FIG. 3.

5 is a cross-sectional view illustrating a structure and a manufacturing method of a thin film transistor substrate for a liquid crystal display according to another exemplary embodiment of the present invention.

Claims (14)

A black matrix formed between adjacent unit pixels on the transparent insulating substrate to prevent light leakage between the unit pixels: A first oxide film formed on the black matrix; An active polycrystalline silicon layer pattern formed in an active region on the first oxide film; A second oxide film formed on the resulting substrate including the active polycrystalline silicon layer pattern, the second oxide film including a first contact hole exposing a predetermined portion of the black matrix; A gate line formed in a predetermined portion of the second oxide film and electrically contacting the black matrix through the first contact hole; A third oxide film formed on the resulting substrate including the gate line; A data line formed on the third oxide film and orthogonal to the gate line; A planarization film formed on the third oxide film including the data line; And And a pixel electrode formed on the planarization layer. The thin film transistor substrate of claim 1, wherein the black matrix and the gate line have the same pattern shape. The thin film transistor substrate of claim 1, wherein a thickness of the first oxide film is the same as a thickness of a second oxide film formed on the active polycrystalline silicon layer. The thin film transistor substrate of claim 1, wherein one of the black matrix and the gate line has an island structure. Forming a black matrix formed between adjacent unit pixels on the transparent insulating substrate to prevent light leakage between the unit pixels: Forming a first oxide film on the black matrix; Forming an active polycrystalline silicon layer pattern in an active region on the first oxide film; Forming a second oxide film on the exposed surface of the active polycrystalline silicon layer pattern; Forming a first contact hole exposing the black matrix in a predetermined portion of the second oxide film; Forming a gate line in a predetermined portion of the first contact hole and the second oxide layer; Forming a third oxide film on the resulting substrate including the gate line; Forming a second contact hole in a predetermined portion of the third oxide film to expose a predetermined portion of the active polysilicon layer pattern; Forming a data line in a predetermined portion of the second contact hole and the third oxide film; Forming a planarization layer on the third oxide layer including the data line; And forming a pixel electrode on the planarization layer. 6. The method of claim 5, wherein the second oxide film formed on the active polycrystalline silicon layer is formed to have the same thickness as the first oxide film. The method of claim 5, wherein the black matrix and the gate line are formed using the same mask. 6. The method of claim 5, wherein any one of the black matrix and the gate line is formed in an island structure. A black matrix formed between adjacent unit pixels on the transparent insulating substrate to prevent light leakage between the unit pixels: A first oxide film formed on the black matrix and having a first contact hole exposing a predetermined portion of the black matrix; An active polycrystalline silicon layer pattern including a first active polycrystalline silicon layer pattern formed in an active region on the first oxide layer and a second active polycrystalline silicon layer pattern formed in the first contact hole and in contact with the black matrix; A second oxide film formed on the active polycrystalline silicon layer pattern; A gate line formed on a predetermined portion of the second oxide film; A third oxide film formed on the resulting substrate including the gate line; Data formed on the third oxide layer, perpendicular to the gate line, and in contact with the source region of the first active polycrystalline silicon layer pattern through a second contact hole formed in the third oxide layer and the second oxide layer below the third oxide layer. line; A third contact hole formed on the third oxide film and formed in the third oxide film on the gate line and a fourth contact hole formed in the third oxide film on the second active polycrystalline silicon layer pattern and a second oxide film below A metal pattern electrically connecting the gate line and the second active polycrystalline silicon layer pattern to each other; A planarization film formed on the third oxide film including the data line; And And a pixel electrode formed on the planarization layer. The thin film transistor substrate of claim 9, wherein a thickness of the first oxide film is the same as a thickness of a second oxide film formed on the active polycrystalline silicon layer. The thin film transistor substrate of claim 9, wherein the gate line has an island structure. The thin film transistor substrate of claim 9, wherein the gate line has a structure jumped by a metal line. Forming a black matrix formed between adjacent unit pixels on the transparent insulating substrate to prevent light leakage between the unit pixels: Forming a first oxide film on the black matrix; Forming a first contact hole exposing a portion of the black matrix; Forming a first active polycrystalline silicon layer pattern in an active region on the first oxide layer and a second active polycrystalline silicon layer pattern in contact with the black matrix in the first contact hole; Forming a second oxide film on the first active polycrystalline silicon layer pattern and the second active polycrystalline silicon layer pattern; Forming a gate pattern on a predetermined portion of the second oxide film; Forming a third oxide film on the resulting substrate including the gate pattern; A second contact hole exposing a source region of the active polysilicon layer pattern to the third oxide film and a second oxide film under the third oxide film, a third contact hole exposing a predetermined portion of the gate pattern, and the second active polycrystalline silicon Forming a fourth contact hole exposing a predetermined portion of the layer pattern; A first data pattern contacting the source region through the second contact hole on the third oxide layer, and connecting the gate pattern and the second active polycrystalline silicon layer pattern through the third and fourth contact holes Forming a data pattern; Forming a planarization layer on the third oxide layer including the first and second data patterns; And forming a pixel electrode on the planarization layer. The method of claim 13, wherein the second oxide film formed on the active polycrystalline silicon layer is formed to have the same thickness as the first oxide film.