KR20040061340A - Liquid crystal display panel and fabricating method thereof - Google Patents

Abstract

PURPOSE: An LCD panel is provided to apply an amorphous silicon nitride film as a protective film, in order to obtain an interception capacity for moisture to the maximum, and to form an amorphous silicon oxide film on the protective film in a limited thickness, thereby minimizing surface pollution. CONSTITUTION: A gate electrode(110), a gate insulating film(130), an active layer(136), a source electrode(108), and a drain electrode(112) are sequentially accumulated on a substrate(101). A protective film(138) having an amorphous silicon film material and an amorphous silicon oxide film(139) are formed on a front side of the substrate(101). A drain contact hole(116) and a pixel electrode(114) are formed next. The pixel electrode(114) patterned on an upper side of the amorphous silicon oxide film(139) is electrically contacted with the drain electrode(112) through the drain contact hole(116). An alignment layer having an organic material is formed.

Description

Liquid crystal display panel and its manufacturing method {LIQUID CRYSTAL DISPLAY PANEL AND FABRICATING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel and a method of manufacturing the same, and more particularly, to a liquid crystal display panel and a manufacturing method thereof, which are suitable for minimizing surface contamination of a protective film for protecting a thin film transistor applied as a switching element of a liquid crystal display panel. It is about a method.

In general, a liquid crystal display is a display in which a desired image can be displayed by individually supplying data signals according to image information to unit pixels arranged in a matrix, and adjusting light transmittance of the unit pixels. Device.

Accordingly, the liquid crystal display includes a liquid crystal display panel in which unit pixels are arranged in a matrix; A driver integrated circuit (IC) for driving the unit pixels is provided.

The liquid crystal display panel includes a color filter substrate and a thin film transistor array substrate facing each other, and a liquid crystal layer formed at a distance between the color filter substrate and the thin film transistor array substrate.

On the thin film transistor array substrate of the liquid crystal display panel, a plurality of data lines for transmitting a data signal supplied from a data driver integrated circuit to the unit pixels and a scan signal supplied from the gate driver integrated circuit to the unit pixels. A plurality of gate lines for transmission are orthogonal to each other, and pixels are defined in a rectangular region defined by crossing these data lines and gate lines.

The gate driver integrated circuit sequentially supplies scan signals to a plurality of gate lines so that unit pixels arranged in a matrix form are sequentially selected one by one, and the data is stored in the unit pixels of the selected one line. Data signals in accordance with the image information are separately supplied from the driver integrated circuits.

Meanwhile, a common electrode and a pixel electrode are formed on opposite inner surfaces of the color filter substrate and the thin film transistor array substrate to apply an electric field to the liquid crystal layer. In this case, the pixel electrode is formed per unit pixel on the thin film transistor array substrate, while the common electrode is integrally formed on the entire surface of the color filter substrate. Therefore, by controlling the voltage applied to the pixel electrode in the state where the voltage is applied to the common electrode, the light transmittance of the unit pixels can be adjusted individually.

In order to control the voltage applied to the pixel electrode for each unit pixel, a thin film transistor used as a switching element is formed in each unit pixel. In this case, although amorphous silicon is mainly applied as an active layer of the thin film transistor, a thin film transistor to which polycrystalline silicon is applied has been developed.

A protective film for protecting the switching element is formed on the front surface of the thin film transistor array substrate on which the switching element such as the amorphous silicon thin film transistor or the polycrystalline silicon thin film transistor is formed. In this case, an amorphous silicon nitride film having excellent blocking ability against water penetration is mainly used as the protective film.

The components of the liquid crystal display as described above will be described in detail with reference to the accompanying drawings.

First, FIG. 1 is a plan view of a unit pixel of a general liquid crystal display panel.

Referring to FIG. 1, gate lines 4-1 and 4 are arranged in rows spaced apart on a substrate, and data lines 2, 2 + 1 are arranged in columns spaced apart from each other. Thus, the gate lines 4 and the data lines 2 are arranged in a matrix form. In this case, pixels are defined in a rectangular region defined by the intersection of the data line 2 and the gate line 4, and the thin film transistor TFT and the pixel electrode 14 are separately provided.

The TFT may include a gate electrode 10 extending at a predetermined position of the gate line 4; A source electrode 8 extending from a predetermined position of the data line 2 so that the gate electrode 10 and a predetermined region overlap with each other; The drain electrode 12 is formed to correspond to the source electrode 8 based on the gate electrode 10.

The source electrode 8 and the drain electrode 12 are spaced apart from each other so as to partially overlap each other on the gate electrode 10, and the drain electrode 12 is a drain contact hole 16. In contact with the pixel electrode 14 through the. In this case, the pixel electrode 14 is formed of a transparent indium tin oxide (ITO) material having high light transmittance.

In addition, the thin film transistor TFT may include a semiconductor layer (not shown in the drawing) such that a conductive channel may be formed between the source electrode 8 and the drain electrode 12 by the scan signal supplied to the gate electrode 10. Not).

Therefore, when the scan signal is supplied to the gate electrode 10 through the gate lines 4, a conductive channel is formed between the source electrode 8 and the drain electrode 12 of the thin film transistor TFT. The data signal supplied to the source electrode 8 via the data lines 2 is transmitted to the drain electrode 12 via the conductive channel.

Since the drain electrode 12 is connected to the pixel electrode 14 through the drain contact hole 16, the data signal supplied to the drain electrode 12 is applied to the pixel electrode 14.

Therefore, the pixel electrode 14 to which the data signal is applied generates an electric field in the liquid crystal layer together with the common transparent electrode (not shown) formed on the color filter substrate.

As described above, when an electric field is applied to the liquid crystal layer, the liquid crystal rotates by dielectric anisotropy to transmit light, and the amount of transmitted light is controlled by the voltage value of the data signal.

The pixel electrode 14 is connected to the storage electrode 20 through the storage contact hole 22, and the storage electrode 20 is connected to the preceding gate line 4-1 and the gate insulating film ( (Not shown in the figure) and overlapped to function as a storage capacitor 18.

Therefore, the storage capacitor 18 charges the voltage value of the scan signal during the turn-on period of the thin film transistor TFT to which the scan signal is applied to the gate line 4, and then the thin film transistor TFT. The driving of the liquid crystal is maintained by supplying the charged voltage to the pixel electrode 14 during the turn-off period.

FIG. 2 is an exemplary view showing a cross section of a unit pixel cut along the line II ′ of FIG. 1. Referring to this, a cross-sectional structure of a thin film transistor region fabricated on a thin film transistor array substrate will be described in detail as follows.

Referring to FIG. 2, a gate electrode 10 is patterned on the substrate 1, and a gate insulating film 30 is formed on the entire surface of the substrate 1 including the gate electrode 10. In this case, the gate electrode 10 is patterned by extending in one direction at a predetermined position when the gate wiring 4 is patterned.

The ohmic contact layer made of a semiconductor layer 32 made of amorphous silicon and n + amorphous silicon doped with phosphorus (P) at a high concentration is formed on the gate insulating film 30 on the gate electrode 10. An active layer 36 in which contact layers 34 are stacked is formed.

In addition, the source electrode 8 and the drain electrode 12 are patterned on the active layer 36 so that the gate electrode 10 partially overlaps with the gate electrode 10.

The ohmic contact layer 34 formed on the semiconductor layer 32 in a region where the source electrode 8 and the drain electrode 12 are spaced apart is removed in the process of patterning the source electrode 8 and the drain electrode 12.

A protective film 38 made of an amorphous silicon nitride film is formed on the entire surface of the substrate 1 including the source electrode 8 and the drain electrode 12.

A drain contact hole 16 exposing a part of the drain electrode 12 is formed on the passivation layer 38.

The pixel electrode 14 is formed on the passivation layer 38, and the pixel electrode 14 and the drain electrode 12 are electrically contacted through the drain contact hole 16.

An alignment layer made of an organic material such as polyimide is formed on the upper surface of the resultant patterned pixel electrode 14 and then rubbed. At this time, rubbing rubs the cloth on the surface of the alignment film at a uniform pressure and speed, so that the polymer chains on the surface of the alignment film are aligned in a predetermined direction so that the liquid crystals are arranged in a constant direction.

As described above, the amorphous silicon nitride film applied as the protective film 38 is known to have the best blocking ability against water penetration, and will be described in detail as follows.

In general, the penetration depth of moisture is limited by the internal structural defects of the inorganic insulating film with respect to moisture penetration into the atmosphere, and therefore the amorphous silicon nitride film having a large internal structural defect and forming a trap site of moisture is infiltrated with moisture. Excellent blocking ability against the has been applied as a protective film (38).

The absolute value of the blocking ability against water infiltration in the inorganic insulating film is in the order of amorphous silicon nitride film> amorphous silicon oxide film> crystalline silicon nitride film> crystalline silicon oxide film.

Referring to the graph of FIG. 3, when the amorphous silicon nitride film (SiN) and the amorphous silicon oxide film (SiO) having a thickness of 30 nm are left in the air, the blocking ability of the amorphous silicon nitride film (SiN) against water penetration is reduced. It can be seen that it is excellent.

On the other hand, in the case of the amorphous silicon oxide film (SiO), the time to block the moisture infiltration is superior to the amorphous silicon nitride film (SiN), but because the blocking ability against water infiltration is not excellent as an interlayer insulating film that emphasizes the relative dielectric constant. Mainly applied.

As described above, the absolute value of the blocking ability against water infiltration is in the order of amorphous silicon nitride film> amorphous silicon oxide film> crystalline silicon nitride film> crystalline silicon oxide film, but the surface adsorption rate and surface bonding force of water are inversely opposite to amorphous silicon nitride film <amorphous silicon oxide film < The crystalline silicon nitride film is shown in this order. This is because the better the blocking ability against water penetration, the more concentrated and combined the membrane surface and water.

Therefore, the moisture bonding layer formed on the surface of the amorphous silicon nitride film is very tightly and tightly bonded to the moisture bond layer compared to the moisture bonding layer of the other inorganic insulating film.

When forming an alignment layer made of an organic material such as polyimide in a state in which a water bonding layer is formed on the surface of the amorphous silicon nitride film, surface contamination occurs, and when cleaning the water bonding layer formed on the surface of the amorphous silicon nitride film, Since the adhesion degree of the moisture is very dense and strongly bonded, it is disadvantageous in terms of cleaning time and cleaning effect compared to the moisture bonding layer of other inorganic insulating films.

That is, referring to the graph of FIG. 4, when the amorphous silicon nitride film (SiN) and the amorphous silicon oxide film (SiO) having a film thickness of 30 nm are left in the air, they are compared with the amorphous silicon nitride film (SiO). It can be seen that the surface contamination of SiN) is very large.

As described above, when the alignment layer made of an organic material such as polyimide is formed on the surface of the amorphous silicon nitride layer (SiN) applied as the protective layer 38, the surface contamination is much higher than that of other inorganic insulating layers, and the surface contamination is the alignment layer. As a result, the DC voltage component accumulates in the liquid crystal display panel and an unintended electric field may be applied to the liquid crystal layer.

In particular, in an in-plane switching (IPS) type liquid crystal display panel, in which a pixel electrode and a common electrode are formed on the same substrate and are sensitive to surface contamination, an afterimage occurs due to the DC electric field, causing an image to deteriorate.

In order to solve the above problem, conventionally, the state and material management of the alignment layer, the atmospheric exposure time management until the alignment layer is formed on the surface of the amorphous silicon nitride layer (SiN), and even by a separate heat treatment or plasma treatment, the amorphous silicon nitride layer (SiN) After removing the surface contamination of), various efforts have been made, such as forming an alignment film.

However, even if the deterioration of the image of the liquid crystal display panel is prevented by the above-mentioned efforts, it is difficult to prevent the image deterioration of the liquid crystal display panel because the reproducibility is not constant.

Accordingly, the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a liquid crystal capable of minimizing surface contamination of a protective film for protecting a thin film transistor applied as a switching element of a liquid crystal display panel. A display panel and a method of manufacturing the same are provided.

1 is an exemplary view showing a planar configuration of a unit pixel of a general liquid crystal display panel.

FIG. 2 is an exemplary view illustrating a cross section of a unit pixel cut along the line II ′ of FIG. 1;

Figure 3 is an exemplary diagram comparing the blocking ability of the amorphous silicon nitride film and the amorphous silicon oxide film with respect to water infiltration, respectively.

4 is an exemplary diagram in which the surface contamination levels of the amorphous silicon nitride film and the amorphous silicon oxide film are compared in a graph.

FIG. 5 is an exemplary view showing a cross-sectional structure of a thin film transistor array substrate for a unit pixel of a liquid crystal display panel according to a first embodiment of the present invention.

*** Explanation of symbols for main parts of drawing ***

101: substrate 108: source electrode

110: gate electrode 112: drain electrode

114: pixel electrode 116: drain contact hole

130: gate insulating film 132: semiconductor layer

134: ohmic contact layer 136: active layer

138: protective film 139: amorphous silicon oxide film

A liquid crystal display panel for achieving the object of the present invention includes a thin film transistor formed on one side on the substrate; A protective film formed on the entire upper surface of the substrate including the thin film transistor; And an amorphous silicon oxide film formed on the upper surface of the protective film.

A method of manufacturing a liquid crystal display panel for achieving the object of the present invention comprises the steps of forming a gate line, a data line and a thin film transistor on the upper surface of the substrate; Forming a protective film on the entire upper surface of the substrate on which the gate line, the data line and the thin film transistor are formed; And forming an amorphous silicon oxide film on the upper surface of the protective film.

The liquid crystal display panel and the method of manufacturing the same according to the present invention as described above are described in detail.

First, the planar configuration of the unit pixel of the liquid crystal display panel according to the present invention is arranged in rows with the gate lines uniformly spaced apart on the substrate as in the planar configuration of FIG. 1 described above, and the data lines are regularly spaced apart from each other. Are arranged. Thus, the gate lines and the data lines are arranged in a matrix form. In this case, pixels are defined in a rectangular region defined by the intersection of the data line and the gate line, and include thin film transistors and pixel electrodes.

The thin film transistor may include a gate electrode extending at a predetermined position of the gate line; A source electrode extending at a predetermined position of the data line and overlapping the gate electrode with a predetermined region; A drain electrode is formed to correspond to the source electrode with respect to the gate electrode.

The source electrode and the drain electrode are spaced apart from each other so as to partially overlap each other on the gate electrode, and the drain electrode is in electrical contact with the pixel electrode through the drain contact hole. In this case, the pixel electrode is formed of a transparent ITO material having high light transmittance.

In addition, the thin film transistor includes a semiconductor layer such that a conductive channel can be formed between a source electrode and a drain electrode by a scan signal supplied to the gate electrode.

Therefore, when the scan signal is supplied to the gate electrode through the gate lines, a conductive channel is formed between the source electrode and the drain electrode of the thin film transistor, and at this time, the data signal supplied to the source electrode through the data lines is connected to the conductive electrode. Via the transfer to the drain electrode.

Since the drain electrode is connected to the pixel electrode through the drain contact hole, the data signal supplied to the drain electrode is applied to the pixel electrode.

Accordingly, the pixel electrode to which the data signal is applied generates an electric field in the liquid crystal layer together with the common transparent electrode formed on the front surface of the color filter substrate or formed on the same surface as the pixel electrode of the thin film transistor substrate.

As described above, when an electric field is applied to the liquid crystal layer, the liquid crystal rotates by dielectric anisotropy to transmit light, and the amount of transmitted light is controlled by the voltage value of the data signal.

Meanwhile, the pixel electrode is connected to the storage electrode through a storage contact hole, and the storage electrode is overlapped with a front gate line and a gate insulating layer therebetween to function as a storage capacitor.

Therefore, the storage capacitor charges the voltage value of the scan signal during the turn-on period of the thin film transistor to which the scan signal is applied to the gate line, and then supplies the charged voltage to the pixel electrode during the turn-off period of the thin film transistor. As a result, the driving of the liquid crystal is maintained.

FIG. 5 is an exemplary view illustrating a cross-sectional structure of a thin film transistor array substrate with respect to unit pixels of a liquid crystal display panel according to a first embodiment of the present invention.

Referring to FIG. 5, a gate electrode 110 is patterned on a substrate 101, and a gate insulating layer 130 is formed on an entire surface of the substrate 101 including the gate electrode 110. In this case, when the gate wiring of the liquid crystal display panel is patterned, the gate electrode 110 extends in one direction at a predetermined position and is patterned.

In addition, an ohmic contact layer including a semiconductor layer 132 made of amorphous silicon and n + amorphous silicon doped with phosphorus (P) at a high concentration on the gate insulating layer 130 on the gate electrode 110. An active layer 136 is formed by stacking contact layers 134.

In addition, the source electrode 108 and the drain electrode 112 are patterned on the active layer 136 so as to partially overlap the gate electrode 110 and face each other.

The ohmic contact layer 134 formed on the semiconductor layer 132 in a region where the source electrode 108 and the drain electrode 112 are spaced apart is removed in the process of patterning the source electrode 108 and the drain electrode 112.

A protective film 138 made of an amorphous silicon nitride film is formed on the entire surface of the exposed substrate 101 including the source electrode 108 and the drain electrode 112, and an amorphous silicon oxide film ( 139) is formed.

A portion of the passivation layer 138 and the amorphous silicon oxide layer 139 are etched to form a drain contact hole 116 exposing a portion of the drain electrode 112.

In addition, a pixel electrode 114 is formed on an upper surface of the amorphous silicon oxide layer 139, and the pixel electrode 114 and the drain electrode 112 are electrically contacted through the drain contact hole 116.

An alignment layer made of an organic material such as polyimide is formed on the top surface of the resultant patterned pixel electrode 114 and then rubbed. At this time, rubbing rubs the cloth on the surface of the alignment film at a uniform pressure and speed, so that the polymer chains on the surface of the alignment film are aligned in a predetermined direction so that the liquid crystals are arranged in a constant direction.

The protective film 138 is preferably applied to the amorphous silicon nitride film excellent in blocking ability to penetrate the water.

However, as described above, when the amorphous silicon nitride film is applied as the passivation layer 138, the moisture bonding layer is formed to have a very dense and strong bond of moisture to the surface of the amorphous silicon nitride film. When the alignment layer is formed, surface contamination is very severely generated, and the surface contamination of the amorphous silicon nitride film affects the alignment layer, thereby deteriorating an image of the liquid crystal display panel.

Therefore, in the present invention, the amorphous silicon nitride film is applied to the protective film 138 to ensure maximum blocking ability against water infiltration, and the amorphous silicon oxide film 139 is formed on the upper surface of the protective film 138 to which the amorphous silicon nitride film is applied. We propose a technique that can minimize surface contamination.

Since the amorphous silicon oxide layer 139 has a lower surface contamination than the amorphous silicon nitride layer as described in detail with reference to the exemplary view of FIG. 4, the surface of the amorphous silicon oxide layer 139 is formed when the alignment layer is formed through a subsequent process. Deterioration of the image of the liquid crystal display panel can be prevented by reducing the adhesion of moisture or organic matter to the liquid crystal display panel.

Meanwhile, when the amorphous silicon oxide film 139 is formed on the upper surface of the protective film 138 to which the amorphous silicon nitride film is applied, the amorphous silicon nitride film and the amorphous silicon oxide film 139 are applied when an electric field is applied to the liquid crystal layer to drive the liquid crystal display panel. ) May cause an afterimage at the interface.

That is, in the process of polarization by the electric field applied to the liquid crystal layer, electrons or holes may be trapped at the interface between the amorphous silicon nitride film and the amorphous silicon oxide film 139 to cause polarity that causes afterimages.

Accordingly, in order to prevent afterimages from occurring at the interface between the amorphous silicon nitride film and the amorphous silicon oxide film 139, the amorphous silicon oxide film 139 is limited to a thickness such that an interface with the amorphous silicon nitride film is formed, thereby reducing the thickness of the amorphous silicon nitride film. The distinction between the interface and the amorphous silicon oxide film 139 should not be clear.

The amorphous silicon oxide film 139 may be formed to have a thickness of, for example, 50 to 150 kPa, particularly 100 kPa. As a result, the amorphous silicon oxide film 139 may be SiN-> SiON-in the thickness range. Have an intermediate state that changes to> SiO.

The silicon oxide layer 139 may be formed by forming an amorphous silicon nitride layer as the passivation layer 138 and then plasma treating the surface of the amorphous silicon nitride layer in an oxygen atmosphere.

As described above, in the first embodiment of the present invention, the gate electrode 110, the gate insulating layer 130, the active layer 136, the source electrode 108, and the drain electrode 112 are sequentially disposed on the substrate 101. After forming, the protective film 138 and the amorphous silicon oxide film 139 made of an amorphous silicon nitride film material are formed on the entire surface of the substrate 101, and the drain contact hole 116 and the pixel electrode 114 are formed to form an amorphous silicon oxide film ( The patterned pixel electrode 114 on the upper surface of the 139 is electrically contacted with the drain electrode 112 through the drain contact hole 116, an alignment layer made of organic material was formed, and then rubbing was performed.

Meanwhile, the second embodiment of the present invention will be described in detail as follows.

First, the gate electrode 110, the gate insulating layer 130, the active layer 136, the source electrode 108, and the drain electrode 112 are sequentially formed on the substrate 101 as in the first embodiment of the present invention. To form.

A protective film 138 formed of an amorphous silicon nitride film is formed on the entire surface of the substrate 101, and then the drain contact hole 116 and the pixel electrode 114 are formed differently from the first embodiment of the present invention, thereby forming the protective film 138. The pixel electrode 114 patterned on the upper surface of the substrate 100 may be in electrical contact with the drain electrode 112 through the drain contact hole 116.

An oxide process is performed on the substrate 101 on which the pixel electrode 114 is patterned to form an amorphous silicon oxide film 139 on the upper surface of the passivation layer 138 exposed by patterning the pixel electrode 114.

In addition, an alignment layer made of an organic material such as polyimide is formed on the upper surface of the resultant product on which the amorphous silicon oxide film 139 is formed, followed by rubbing.

The second embodiment of the present invention is the same as the first embodiment of the present invention described above by applying an amorphous silicon nitride film to the protective film 138 to ensure the maximum blocking ability against water penetration, the protective film to which the amorphous silicon nitride film is applied An amorphous silicon oxide film 139 may be formed on the upper surface of 138 to minimize surface contamination.

Therefore, as in the first exemplary embodiment of the present invention, since an afterimage may be generated at the interface between the amorphous silicon nitride film and the amorphous silicon oxide film 139, the amorphous silicon oxide film 139 may be separated from the amorphous silicon nitride film. By limiting the thickness of the interface of the amorphous silicon nitride film and the amorphous silicon oxide film 139, the boundary between the amorphous silicon nitride film and the amorphous silicon oxide film 139 should be clear.

The amorphous silicon oxide film 139 may be formed to have a thickness of, for example, 50 to 150 kPa, particularly 100 kPa. As a result, the amorphous silicon oxide film 139 may be SiN-> SiON-in the thickness range. Have an intermediate state that changes to> SiO.

As described above, the liquid crystal display panel and the method of manufacturing the same according to the present invention apply an amorphous silicon nitride film as a protective film to ensure maximum blocking ability against water penetration, and limit the thickness of the amorphous silicon oxide film on the protective film to which the amorphous silicon nitride film is applied. By forming a surface contamination can be minimized.

Therefore, by reducing the adhesion of moisture or organic matter to the surface of the amorphous silicon oxide film in the subsequent process of forming the alignment film of the organic material, it is possible to prevent the image of the liquid crystal display panel from deteriorating.

In particular, the process of forming the amorphous silicon oxide film is superior in reproducibility compared to the conventional alignment film state and material management, air exposure time management until the alignment film is formed on the surface of the amorphous silicon nitride film, removal of surface contamination of the amorphous silicon nitride film, etc. Accordingly, it is possible to minimize the surface contamination of the protective film relatively simply to prevent image deterioration of the liquid crystal display panel.

Claims (16)

A thin film transistor formed on one side of the substrate; A protective film formed on the entire upper surface of the substrate including the thin film transistor; And an amorphous silicon oxide film formed on an upper surface of the protective film. The liquid crystal display panel according to claim 1, wherein the amorphous silicon oxide film has a thickness of 50 to 150 GPa. The liquid crystal display panel according to claim 1, wherein the amorphous silicon oxide film has a thickness of 100 GPa. The liquid crystal display panel of claim 1, wherein an amorphous silicon nitride film is applied as the passivation film. The liquid crystal display panel of claim 1, wherein the substrate is a thin film transistor array substrate. The liquid crystal display panel of claim 1, wherein the thin film transistor is individually provided in a plurality of pixels arranged in a matrix form on a substrate. Forming a gate line, a data line, and a thin film transistor on an upper surface of the substrate; Forming a protective film on the entire upper surface of the substrate on which the gate line, the data line and the thin film transistor are formed; And forming an amorphous silicon oxide film on the upper surface of the protective film. The method of claim 7, wherein an amorphous silicon nitride film is formed as the passivation film. 8. The method of claim 7, wherein the amorphous silicon oxide film is formed by plasma treatment of the surface of the protective film in an oxygen atmosphere. 8. The method of claim 7, wherein the amorphous silicon oxide film is formed to a thickness of 50 to 150 GPa. 8. The method of claim 7, wherein the amorphous silicon oxide film is formed to a thickness of 100 GPa. Forming a gate line, a data line, and a thin film transistor on an upper surface of the substrate; Forming a protective film on the entire upper surface of the substrate on which the gate line, the data line and the thin film transistor are formed; Etching a portion of the passivation layer to form a drain contact hole exposing the drain electrode of the thin film transistor; Forming a pixel electrode on the upper surface of the passivation layer and patterning the transparent conductive material to form a pixel electrode in the unit pixel and electrically contacting the data line through the drain contact hole; And selectively forming an amorphous silicon oxide film on an upper surface of the protective film. The method of claim 12, wherein an amorphous silicon nitride film is formed as the passivation film. The method of claim 12, wherein the amorphous silicon oxide film is formed through an oxidation process. The method of claim 12, wherein the amorphous silicon oxide film is formed to a thickness of 50 to 150 GPa. The method of claim 12, wherein the amorphous silicon oxide film is formed to a thickness of 100 GPa.