KR20040061189A - crystallizing method of silicon layer and manufacturing method of polycrystalline silicon thin film transistor using the same - Google Patents

Abstract

PURPOSE: A crystallization method of an amorphous silicon layer is provided to form a silicon oxide film on an amorphous silicon layer, and to crystallize the silicon oxide film by a laser, in order to form a polycrystalline silicon layer having an improved surface roughness with large-sized grains, thereby improving electric properties of a TFT. CONSTITUTION: When laser beams are irradiated on an amorphous silicon layer(130), The amorphous silicon layer(130) is melted/coagulated/crystallized, forming a polycrystalline silicon layer(150). A buffer layer(120) and a silicon oxide film(140) are formed in lower/upper parts of the amorphous silicon layer(130). The buffer layer(120) is made of a silicon oxide film as well. The silicon oxide film(140) covers a surface of the amorphous silicon layer(130).

Description

Crystallization method of silicon layer and manufacturing method of polycrystalline silicon thin film transistor using the same

The present invention relates to a crystallization method, and more particularly, to a crystallization method of amorphous silicon and a manufacturing method of a thin film transistor using the same.

Recently, with the rapid development of the information society, there is a need for a flat panel display having excellent characteristics such as thinness, light weight, and low power consumption. It is excellent in color display and image quality, and is actively applied to notebooks and desktop monitors.

In general, a liquid crystal display device is formed by arranging two substrates on which electric field generating electrodes are formed so that the surfaces on which two electrodes are formed face each other, injecting a liquid crystal material between the two substrates, and then applying voltage to the two electrodes. By moving the liquid crystal molecules by an electric field, the device expresses an image by the transmittance of light that varies accordingly.

The lower substrate of the liquid crystal display includes a thin film transistor which is a switching element. In general, an active layer used in the thin film transistor is made of amorphous silicon (a-Si: H). This is because amorphous silicon can be formed on a large substrate such as a low cost glass substrate at low temperature.

However, because amorphous silicon has disordered atomic arrangements, weak Si-Si bonds and dangling bonds exist, and thus they become metastable when irradiated with light or applied with electric fields. This problem is emerging. In particular, amorphous silicon has a problem in that its properties are deteriorated by irradiation of light, and its electrical characteristics (field effect mobility: 0.1-1.0 cm 2 / V · s) and reliability are poor, making it difficult to use in driving circuits.

Therefore, the amorphous silicon thin film transistor is used only as a switching element of the pixel, and the driving circuit is mounted in a manner of connecting an insulating substrate and a printed circuit board (PCB) using a tape carrier package (TCP) driving IC. As a result, the driving IC and the mounting cost take a large part of the cost.

In addition, when the resolution of the liquid crystal panel for a liquid crystal display device is increased, the pad pitch outside the substrate connecting the gate wiring and the data wiring of the thin film transistor substrate with the TCP becomes short, and the TCP bonding itself becomes difficult.

On the other hand, since polycrystalline silicon has much higher field effect mobility than amorphous silicon, a driving circuit can be made on a substrate, thereby reducing driving IC cost and simplifying mounting.

In addition, polycrystalline silicon has a higher field effect mobility than amorphous silicon, and is advantageous as a switching device of a high resolution panel. The polycrystalline silicon may be applied to a display in which a lot of light is emitted due to less light current than amorphous silicon.

As a method of forming polycrystalline silicon, a laser annealing method of growing an amorphous silicon thin film by applying an excimer laser while heating the substrate temperature to about 250 ° C., and depositing a metal on the amorphous silicon to produce polycrystalline silicon as a seed The metal induced crystallization (MIC) method to be formed, the solid phase crystallization (SPC) method of forming amorphous silicon by heat treatment for a long time at high temperature, and the method of depositing polycrystalline silicon directly on a substrate.

Here, the solid phase crystallization method forms a buffer layer with a predetermined thickness to prevent diffusion of impurities on a quartz substrate that can withstand high temperatures of 600 ° C. or higher, deposits amorphous silicon on the buffer layer, and then, for a long time at a high temperature in a furnace. Since the solid crystallization method is performed for a long time at high temperature, it is impossible to obtain a desired polycrystalline silicon phase, and because the grain growth direction is irregular, the gate insulating film in contact with the polycrystalline silicon grows irregularly when applied to a thin film transistor. Therefore, the breakdown voltage of the device is lowered. In addition, the grain size of the polycrystalline silicon is non-uniform, thereby lowering the electrical characteristics of the device, and there is a problem of using an expensive quartz substrate.

In the metal induction crystallization method, the metal may lower the crystallization temperature of amorphous silicon to use a large-area glass substrate, but the metal material used as a catalyst may remain in the silicon film to act as an impurity.

Laser heat treatment method is the most widely studied method of polycrystalline silicon formation, which supplies instantaneous laser energy to the substrate on which amorphous silicon is deposited (tens of tens to hundreds of nanoseconds) to make the amorphous silicon in a molten state and then polycrystalline by cooling It is a method of forming silicon.

Hereinafter, a crystallization method using a laser will be described with reference to the accompanying drawings.

1A to 1C are cross-sectional views illustrating a crystallization process of amorphous silicon using a general laser crystallization method.

First, as shown in FIG. 1A, a buffer layer 20 is formed on a substrate 10, and an amorphous silicon layer 30 is formed thereon. The buffer layer 20 prevents impurities in the substrate 10 from diffusing into the amorphous silicon film 30 in a subsequent process.

Subsequently, as shown in FIG. 1B, when the laser is irradiated to the amorphous silicon layer 30, the amorphous silicon layer 30 is crystallized to form the polycrystalline silicon layer 40. Here, the light energy of the laser beam irradiated with the amorphous silicon layer 30 is converted into thermal energy to melt the amorphous silicon layer 30, and then the thermal energy is dissipated so that the amorphous silicon layer 30 that has been melted is solidified. Silicon layer 40 is formed.

Looking at the crystallization process in one grain of the polycrystalline silicon layer 40, the center of the grain solidifies first, and then the grain boundary 42 is solidified. Therefore, the center of the grain is in a solid phase and the grain boundary 42 is in a liquid phase. Since the density of the solid phase is greater than the density of the liquid phase, the grain boundary 42 goes from the center of the grain to the grain boundary 42. The height of the surface of the grain becomes high. In this case, since the buffer layer 20 is formed below the amorphous silicon layer 30, but the air layer is positioned at the upper portion, the degree of dissipation of thermal energy is changed to the upper and lower portions of the amorphous silicon layer 30, which is a grain boundary 42. Affects its height.

Thus, as shown in FIG. 1C, the polycrystalline silicon layer 40 has a very large grain boundary 42, and the surface becomes very rough. The surface roughness at this time is about 200 to 500 kPa. Such roughness adversely affects the interface characteristics between the polycrystalline silicon layer 40 and the gate insulating film to be formed thereon, thereby lowering the electrical characteristics of the thin film transistor.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a method for crystallizing an amorphous silicon layer which can improve the surface roughness of the polycrystalline silicon layer.

Another object of the present invention is to provide a method of manufacturing a polycrystalline silicon thin film transistor capable of improving electrical characteristics.

1A to 1C are cross-sectional views illustrating a crystallization process of amorphous silicon using a general laser crystallization method.

2A to 2C are cross-sectional views illustrating a crystallization process of an amorphous silicon layer according to the present invention.

3A to 3E are cross-sectional views illustrating a manufacturing process of a polycrystalline silicon thin film transistor according to the present invention.

<Description of Symbols for Main Parts of Drawings>

110 substrate 120 buffer layer

130: amorphous silicon layer 140: silicon oxide film

150: polycrystalline silicon layer 152: grain boundary

In order to achieve the above object, a method of crystallizing an amorphous silicon layer according to the present invention comprises the steps of forming a buffer layer on a substrate, forming an amorphous silicon layer on the buffer layer, a silicon oxide film formed on the amorphous silicon layer And irradiating a laser beam to the substrate on which the silicon oxide film is formed and crystallizing the amorphous silicon layer to form a polycrystalline silicon layer.

Here, it is preferable that a buffer layer consists of a silicon oxide film.

Forming the silicon oxide film includes exposing the amorphous silicon layer to oxygen to oxidize it.

In the present invention, the surface roughness of the polycrystalline silicon layer may be about 50 GPa or less.

A method of manufacturing a polycrystalline silicon thin film transistor according to the present invention comprises the steps of forming a buffer layer on a substrate, forming an amorphous silicon layer on the buffer layer, forming a silicon oxide film on the amorphous silicon layer, the silicon oxide film Irradiating a laser beam on the formed substrate, crystallizing the amorphous silicon layer to form a polycrystalline silicon layer, patterning the polycrystalline silicon layer and the silicon oxide film to form a polycrystalline silicon pattern and a first gate insulating film, Forming a second gate insulating layer on the first gate insulating layer, forming a gate electrode on the second gate insulating layer, and implanting impurities into the polycrystalline silicon pattern using the gate electrode as a mask to form an active layer, a source, and a drain Forming a region, said source and de Activating an impurity in the phosphorus region, forming an interlayer insulating film covering the gate electrode and having first and second contact holes respectively exposing the source and drain regions, and forming an interlayer insulating film on the interlayer insulating film And forming source and drain electrodes connected to the source and drain regions through two contact holes, respectively.

Here, it is preferable that a buffer layer consists of a silicon oxide film.

In addition, the forming of the silicon oxide film includes exposing the amorphous silicon layer to oxygen to oxidize it.

The sum of the thicknesses of the first and second gate insulating layers may be about 1,700 to 2,000 mm 3.

In the present invention, the step of activating impurities in the source and drain regions may be performed by a laser heat treatment method.

As described above, in the present invention, by forming a silicon oxide film on the amorphous silicon layer and laser crystallizing, a polycrystalline silicon layer having a large grain size and improved surface roughness can be formed. When the polycrystalline thin film transistor is formed using the polycrystalline silicon layer, the silicon oxide film may be used as the gate insulating film, and the interfacial properties between the polycrystalline silicon layer and the gate insulating film may be improved to improve the electrical characteristics of the thin film transistor.

Hereinafter, a method of crystallizing an amorphous silicon layer and a method of manufacturing a polycrystalline silicon thin film transistor using the same will be described in detail with reference to the accompanying drawings.

2A to 2C are cross-sectional views illustrating a crystallization process of an amorphous silicon layer according to the present invention.

First, as shown in FIG. 2A, a buffer layer 120 is formed on a substrate 110 and an amorphous silicon layer 130 is formed thereon. The buffer layer 120 may be formed of a silicon oxide layer, and prevents impurities from flowing into the amorphous silicon layer 130 from the substrate 110. The amorphous silicon layer 130 may be formed using a plasma vapor deposition (PECVD) device or a low pressure vapor deposition (LPCVD) device. Subsequently, the amorphous silicon layer 130 is exposed to a nitrogen atmosphere to be dehydrogenated, and then annealed at a high pressure in an oxygen atmosphere to oxidize the surface of the amorphous silicon layer 130 to thereby oxidize the silicon oxide layer 140. To form. In general, the amorphous silicon layer 130 for crystallization is formed to a thickness between 300 kPa and 800 kPa. In the present invention, since the surface of the amorphous silicon layer 130 is oxidized to form a silicon oxide film 140, the silicon oxide film 140 In consideration of the thickness of the amorphous silicon layer 130 is preferably formed to be thicker.

Next, as shown in FIG. 2B, when the laser beam is irradiated onto the amorphous silicon layer 130, the polycrystalline silicon layer 150 is formed by melting and solidifying the amorphous silicon layer 130. Here, the buffer layer 120 and the silicon oxide film 140 are formed on the lower and upper portions of the amorphous silicon layer 130, respectively. Since the buffer layer 120 is also made of a silicon oxide film, the thermal energy of the laser beam is an amorphous silicon layer. The degree of dissipation to the top and bottom of the 130 is the same. In addition, since the silicon oxide film 140 covers the surface of the amorphous silicon layer 130, the degree of the grain boundary 152 protruding during crystallization may be reduced.

Therefore, the polycrystalline silicon layer 150 formed as shown in FIG. 2C has a large grain size, and the height of the grain boundary 152 is lowered. The surface roughness of the polycrystalline silicon layer 150 is about 50 GPa or less.

When the thin film transistor is formed by using the polycrystalline silicon of the present invention, the interface property between the polycrystalline silicon layer and the gate insulating film is improved, thereby improving the electrical properties of the thin film transistor. In addition, a silicon oxide film on the polycrystalline silicon layer can be used as the gate insulating film, whereby the interfacial properties are further improved.

A method of manufacturing the polycrystalline silicon thin film transistor will be described in detail with reference to FIGS. 3A to 3E. 3A to 3E are cross-sectional views illustrating a manufacturing process of a polycrystalline silicon thin film transistor according to the present invention.

First, as shown in FIG. 3A, a buffer layer 220 is formed on a substrate 210 and an amorphous silicon layer (not shown) is formed thereon. Next, after the amorphous silicon layer is crystallized by the method of FIGS. 2A to 2C, the polycrystalline silicon layer and the silicon oxide layer are patterned to form an island-type polycrystalline silicon pattern 230 and a first gate insulating layer 240. Here, the buffer layer 220 may be formed of a silicon oxide film, and serves to prevent the impurities in the substrate 210 from diffusing into the amorphous silicon layer.

Subsequently, as shown in FIG. 3B, the second gate insulating layer 242 and the metal layer are sequentially deposited on the first gate insulating layer 240, and then the metal layer is patterned to form the gate electrode on the polycrystalline silicon pattern 230 (FIG. 3A). 250 is formed, respectively. In general, the thickness of the gate insulating film is about 1,700 kPa to 2,000 kPa. In the present invention, since the first gate insulating film 240 is formed by oxidizing the amorphous silicon layer, the thickness of the second gate insulating film 242 deposited is 1st. The thickness of the gate insulating layer 240 is determined. Here, the first and second gate insulating layers 240 and 242 may be formed to have the same shape as the gate electrode 250. Next, ion doping is performed on the polycrystalline silicon pattern 230 of FIG. 3A using the gate electrode 250 as a mask. After ion doping, the polycrystalline silicon pattern 230 (in FIG. 3A) is divided into source and drain regions 234 and 236 implanted with impurities and an active layer 232 not implanted.

Next, as shown in FIG. 3C, heat treatment is performed using a laser to activate impurities implanted into the source and drain regions 234 and 236. On the other hand, the semiconductor structure of the source and drain regions 234 and 236 may change from polycrystalline to amorphous due to the ion doping energy in the ion doping of Figure 3b, not only activate the doped ions by heat treatment using a laser In addition, the amorphous source and drain regions 22 and 23 may be restored to a polycrystalline state.

Next, as shown in FIG. 3D, an interlayer insulating film 260 is formed of a silicon oxide film or a silicon nitride film, and patterned together with the first and second gate insulating films 240 and 242 to form the source and drain regions 234 and 236. Respective first and second contact holes 261 and 262 are formed, respectively.

Subsequently, as shown in FIG. 3E, a material such as a metal is deposited and patterned to form source and drain electrodes 272 and 274. The source and drain electrodes 272 and 274 contact the source and drain regions 234 and 236 through the first and second contact holes 261 and 262.

Such a thin film transistor using polycrystalline silicon has a high field effect mobility and a fast response speed. When the polycrystalline silicon thin film transistor is used in a liquid crystal display device, a driving circuit can be formed on the same substrate, thus manufacturing process and cost of the liquid crystal display device. Can be reduced.

The present invention is not limited to the above embodiments, and various changes and modifications can be made without departing from the spirit of the present invention.

In the crystallization method of the amorphous silicon layer according to the present invention, the grain size can be increased by making the heat energy dissipation uniform, and the surface roughness of the polycrystalline silicon layer can be improved. When the thin film transistor is formed using this, it is possible to improve the interface between the polycrystalline silicon layer and the gate insulating film.

Claims (9)

Forming a buffer layer over the substrate; Forming an amorphous silicon layer on the buffer layer; Forming a silicon oxide film on the amorphous silicon layer; And Irradiating a laser beam to the substrate on which the silicon oxide film is formed and crystallizing the amorphous silicon layer to form a polycrystalline silicon layer Crystallization method of the amorphous silicon layer comprising a. The method of claim 1, The buffer layer is a crystallization method of an amorphous silicon layer made of a silicon oxide film. The method of claim 1, The forming of the silicon oxide film may include exposing the amorphous silicon layer to oxygen to oxidize it. The method of claim 1, Wherein the surface roughness of the polycrystalline silicon layer is about 50 GPa or less. Forming a buffer layer on the substrate; Forming an amorphous silicon layer on the buffer layer; Forming a silicon oxide film on the amorphous silicon layer; Irradiating a laser beam on the substrate on which the silicon oxide film is formed, and crystallizing the amorphous silicon layer to form a polycrystalline silicon layer; Patterning the polycrystalline silicon layer and the silicon oxide film to form a polycrystalline silicon pattern and a first gate insulating film; Forming a second gate insulating film on the first gate insulating film; Forming a gate electrode on the second gate insulating layer; Implanting impurities into the polycrystalline silicon pattern using the gate electrode as a mask to form an active layer, a source and a drain region; Activating impurities in the source and drain regions; Forming an interlayer insulating film covering the gate electrode and having first and second contact holes respectively exposing the source and drain regions; And Forming a source and a drain electrode connected to the source and drain regions through the first and second contact holes, respectively, on the interlayer insulating layer; Method of manufacturing a polycrystalline silicon thin film transistor comprising a. The method of claim 5, wherein And the buffer layer is a silicon oxide film. The method of claim 5, wherein The forming of the silicon oxide film includes exposing the amorphous silicon layer to oxygen to oxidize the polycrystalline silicon thin film transistor. The method of claim 5, wherein The sum of the thicknesses of the first and second gate insulating films is about 1,700 to 2,000 Å. The method of claim 5, wherein And activating the impurities in the source and drain regions by a laser heat treatment method.