KR20040060239A - Thin Film Transistor for Liquid Crystal Display Device and method of fabricating the same - Google Patents

Abstract

PURPOSE: A TFT of an LCD device is provided to form titanium layers contacted with semiconductor layers under aluminum-neodymium, thereby preventing a leakage current from increasing owing to a mutual dispersion between aluminum of source/drain electrode layers and poly silicon of the semiconductor layers as suppressing element property deterioration. CONSTITUTION: A buffer layer(105) is formed on a substrate(100). Semiconductor layers(110) consisting of three parts are formed on the buffer layer(105). A gate insulating film(125) and a gate electrode(130) are formed on an active channel layer(110a) among the semiconductor layers(110). An interlayer insulating film(140) is formed on the gate electrode(130). Source/drain electrodes(150,155) are formed on the interlayer insulating film(140) as being contacted with ohmic contact layers(110c). Titanium layers(150a,155a), aluminum-neodymium layers(150b,155b), molybdenum layers(150c,155c) are sequentially accumulated. A protective layer(160) is formed on the drain electrode(155). A pixel electrode(170) is formed on the protective layer(160) in connection with the drain electrode(155).

Description

Thin Film Transistor for Liquid Crystal Display and Manufacturing Method Thereof {Thin Film Transistor for Liquid Crystal Display Device and method of fabricating the same}

The present invention relates to a liquid crystal display device, and more particularly, to a method for manufacturing a thin film transistor of a liquid crystal display device using polysilicon.

Recently, liquid crystal displays have been spotlighted as next generation advanced display devices having low power consumption, good portability, technology-intensive, and high added value.

The liquid crystal display device injects a liquid crystal between an array substrate including a thin film transistor (TFT) and a color filter substrate to obtain an image effect by using a difference in refractive index of light according to the anisotropy of the liquid crystal. Means an image display device by a non-light emitting element.

Currently, an active matrix liquid crystal display (AM-LCD) in which the thin film transistor and the pixel electrode are arranged in a matrix manner has been attracting the most attention because of its excellent resolution and video performance. Hydrogenated amorphous silicon (a-Si: H) is mainly used because the low-temperature process is possible, so that an inexpensive insulating substrate can be used.

However, because hydrogenated amorphous silicon has disordered atomic arrangements, weak Si-Si bonds and dangling bonds exist, which are converted into a quasi-stable state when irradiated with light or applied with an electric field, and used as a thin film transistor device. It is difficult to use as a driving circuit due to poor stability and low electrical characteristics (low field effect mobility: 0.1 to 1.0 cm2 / V · s).

Therefore, in general, a driving device manufactured separately is connected to the liquid crystal panel, and as a representative example, the driving device is manufactured in TCP (Tape Carrier Package) and attached to the liquid crystal panel. Accordingly, in the TCP, a plurality of circuit parts are attached between a PCB (Printed Circuit Board) substrate and a liquid crystal panel to receive a signal input from the PCB substrate and transfer the signal to the liquid crystal panel. However, such a configuration occupies a large part of the cost of the actual equipment of the driver IC, and as the resolution of the liquid crystal panel increases, the pad pitch outside the substrate connecting the gate wiring and the data wiring of the thin film transistor substrate with the TCP is short. TCP bonding itself is becoming difficult.

On the other hand, since polysilicon has a greater field effect mobility than amorphous silicon, a driving circuit can be made on a substrate. When the polysilicon is used to make a driving circuit directly on a substrate, driving IC costs can be reduced and mounting is simplified.

1 is a schematic view of a driving circuit unit integrated liquid crystal display device constructed using a general polysilicon.

As shown, the driving circuit portion 5 and the pixel portion 3 are formed on the insulating substrate 1 together. The pixel portion 3 is positioned at the center of the substrate 1, and the gate and data driving circuit portions 5a and 5b are positioned at one side of the pixel portion 3 and the other side not parallel thereto. In the pixel portion 3, a plurality of gate lines 7 connected to the gate driving circuit part 5a and a plurality of data lines 9 connected to the data driving circuit part 5b cross each other, and the two wires cross each other. The pixel electrode 10 is formed in the pixel region P defined by the pixel region, and the thin film transistor T connected to the pixel electrode 10 is positioned at the intersection of the two wires.

In addition, the gate and data driving circuit unit are connected to an external signal input terminal 12.

The gate and data driver circuits 5a and 5b internally adjust an external signal input through the external signal input terminal 12 to control the display to the pixel unit 3 through the gate and data lines 7 and 9, respectively. Apparatus for supplying signals and data signals.

Accordingly, the gate and data driver circuits 5a and 5b are formed with a complementary metal-oxide semiconductor (CMOS) structure thin film transistor (not shown), which is an inverter, to properly output an input signal. It is.

The CMOS is a semiconductor technology used in a thin film transistor for driving circuits requiring high-speed signal processing. The CMOS uses extra electrons (n-type semiconductor) and negatively charged holes (p-type semiconductor) charged with negative electricity. It is used as a complementary method for forming a conductor and forming a current gate by effective electrical control of the two kinds of semiconductors.

2 is a cross-sectional view of a thin film transistor of a liquid crystal display using polysilicon.

As shown, a buffer layer 25 made of an inorganic insulating material such as silicon oxide (SiO ₂ ) is formed on the entire surface of the substrate 20 on the insulating substrate 20, and a semiconductor layer (above the buffer layer 25) is formed on the insulating substrate 20. 30 is formed, and a gate insulating layer 45 is formed on the entire surface of the semiconductor layer 30. In addition, a gate electrode 50 is formed on the gate insulating film 45, and an interlayer 70 is formed on the gate electrode 50. Semiconductor layer contact holes 73a and 73b for contacting the semiconductor layer 30 are formed in the gate insulating layer 45 and the interlayer insulating layer 70, and the semiconductor layer contact hole 73a is disposed on the interlayer insulating layer 70. , 73b), and the source and drain electrodes 80a and 80b are formed to be spaced apart from the gate electrode 50 by a predetermined distance. A protective layer 90 including a drain electrode contact hole 95 is formed on the drain electrode 80b, and the drain electrode 80 is formed on the protective layer 90 through the drain electrode contact hole 95. ) Is connected to the pixel electrode 97.

In the semiconductor layer 30, a portion of the lower portion of the gate insulating layer 45 corresponding to the gate electrode 50 forms an active channel layer 30a, and a portion of the semiconductor layer 30 contacting the source and drain electrodes 80a and 80b is n. ⁺ Doped to form an n-type ohmic contact layer 30c, and an n ⁻ doped Lightly Doped Drain (LDD) layer 30b is formed between the active layer 30a and the n-type ohmic contact layer 30c. The LDD layer 30b is doped at a low concentration to disperse hot carriers, thereby preventing an increase in leakage current I _off and preventing a loss of current in an on state. do.

Although not shown, referring to the p-type thin film transistor using polysilicon for a while, the p-type thin film transistor is the same as the n-type thin film transistor structure described above, except that the configuration of the semiconductor layer is p + doped to form a p-type ohmic contact layer. The semiconductor layer under the gate electrode without p + doping forms an active channel layer, and the LDD layer of n− is not formed. Otherwise, the structure is the same as the n-type thin film transistor described above. In this case, the drain electrode contact hole and the pixel electrode are not formed.

A method of manufacturing a thin film transistor of a liquid crystal display device using the aforementioned polysilicon will be described with reference to the drawings.

As shown in FIG. 3A, an inorganic insulating material such as silicon oxide (SiO ₂ ) is deposited on the transparent insulating substrate 20 to form a buffer layer 25. After depositing amorphous silicon (a-Si) on the substrate 20 on which the buffer layer 25 is formed, performing a dehydrogenation process, and performing a laser crystallization process, the amorphous silicon layer is a polysilicon layer. Crystallize. Thereafter, the polysilicon layer is patterned to form a semiconductor layer 30 by performing a mask process.

Next, as shown in FIG. 3B, the gate insulating layer 45 is formed by depositing silicon oxide (SiO ₂ ) on the entire surface of the substrate 20 on which the semiconductor layer 30 is formed. Thereafter, a metal material, for example, molybdenum (Mo) is deposited on the gate insulating layer 45, and then a mask process is performed to form the gate electrode 50. Using the gate electrode 50 as a blocking mask, n- doped LDD (Lightly doped drain) doping is performed on the entire surface of the substrate 20 by ion implantation. In this case, the dose of LDD doping is approximately 1E13 / cm 2 to 5E13 / cm 2. At this time, the semiconductor layer 30a under the gate electrode 50 of each of the pixel portion and the driving circuit portion is not doped, and other semiconductor layers 30b are n-doped.

Next, as shown in FIG. 3C, the PR pattern is formed on the entire surface of the n-doped substrate 20 and a mask process is performed to form a PR pattern except for the gate insulating layer on the semiconductor layer to be n + doped. Block. Thereafter, n + doping is performed by ion implantation having a high concentration of dose. At this time, the semiconductor layer of the portion not blocked by the PR pattern is n + doped to form an n-type ohmic contact layer 30c. At this time, the dose of the n + doping has a value of approximately 1E15 / ㎠ to 9E15 / ㎠. A portion of the semiconductor layer 30 in which n− and n + doping are blocked by the gate electrode 50 forms an active channel layer 30a, and is formed between the active channel layer 30a and the n-type ohmic contact layer 30c. The n-doped portion forms the LDD layer 30b.

In the p-type thin film transistor, the semiconductor layer is formed of p + doping, not n + doping. A p-type ohmic contact layer is formed by the p + doping, and an undoped portion forms an active channel layer, and an n− LDD layer is formed. It doesn't work.

Next, referring to FIG. 3D, an interlayer insulating film 70 is deposited by depositing an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ) on the entire surface of the substrate 20 on which the n-type ohmic contact layer 30c is formed. To form. Subsequently, the gate insulating layer 45 and the interlayer insulating layer are subjected to a mask process, and collectively etched to form semiconductor layer contact holes 73a and 73b exposing a part of the ohmic contact layer 30c to the outside. Subsequently, aluminum-neodymium (AlNd) and molybdenum (Mo) are sequentially deposited on the substrate 20 on which the interlayer insulating film 70 is formed, sequentially etched by a mask process, and the semiconductor layer contact hole 73a. And source and drain electrodes 80a and 80b connected to the ohmic contact layer 30c through 73b.

Next, as shown in FIG. 3E, silicon nitride (SiNx) is deposited on the substrate 20 on which the source and drain electrodes 80a and 80b are formed, and a mask process is performed to form the drain contact hole 95. The branches form a protective layer 90. At this time, the formation of the drain contact hole 95 is applied only when the thin film transistor is used as a switching element. In the n-type or p-type thin film transistor used in CMOS, the drain contact hole is not formed. Thereafter, a hydrogenation heat treatment process is performed to improve characteristics of the device.

Since it belongs to the manufacturing process on the array substrate, but will be briefly described as it is associated with the thin film transistor manufacturing process. After the entire process of depositing indium tin oxide (ITO) on the substrate on which the protective layer 90 is formed in a process corresponding to only a thin film transistor, which is a switching element, a mask process is performed to drain electrodes through the drain contact holes 95. A pixel electrode 97 connected to 80b is formed.

In the above-described thin film transistor of a liquid crystal display using polysilicon, a double-conducted source and drain electrode of aluminum-neodymium (AlNd) / molybdenum (Mo) and a semiconductor layer during a hydrogenation heat treatment process for improving device characteristics Interdiffusion occurs at the part in contact with the polysilicon interface.

4a to 4c show the change in the interface shape with the thickness and heat treatment time of aluminum and polysilicon.

Aluminum and polysilicon are interdiffused with the passage of the hydrogenation heat treatment to form an interface that is initially formed and a very different interface from the initial as the heat treatment time passes.

4A shows the state before the hydrogenation heat treatment, and the interface between aluminum and polysilicon is clearly distinguished.

On the other hand, Figure 4b shows that after a certain amount of time has passed since the start of the hydrogenation heat treatment, the aluminum and polysilicon are interdiffused to change the interface.

4C shows that after the end of the hydrogenation heat treatment, the polysilicon having a thin thickness is completely diffused into the aluminum layer having a thick thickness, thereby forming an interface different from the initial interface.

5A and 5B are views showing the progress after the hydrogenation heat treatment of the above-described conventional polysilicon thin film transistor. FIG. 5A is a reflection mode and FIG. 5B is a transmission mode observation using an optical microscope.

As shown, aluminum-neodymium (AlNd) of the source and drain electrodes in contact with the semiconductor layer of polysilicon has been diffused into the semiconductor layer. The diffusion of aluminum-neodymium (AlNd) and silicon is an important variable in the thickness or volume of each layer. Although not shown in the drawing, a thick data line made of aluminum-neodymium (AlNd) exists on the drain electrode side, while the source electrode is made of only aluminum-neodymium (AlNd) of its own, so that aluminum diffuses rapidly on the drain electrode side. On the other hand, the source electrode side did not diffuse much.

The diffusion of the metal material into the semiconductor layer causes deterioration of device characteristics such as an increase in leakage current.

In order to solve the above problems, in the present invention, by adding an additional layer to the source and drain electrodes of the conventional double structure of aluminum-neodymium (AlNd), titanium (Ti) contacting the semiconductor layer under the aluminum-neodymium (AlNd) To form a thin film transistor of an excellent quality liquid crystal display device which suppresses deterioration of device characteristics such as an increase in leakage current by mutual diffusion of aluminum of the source and drain electrode layers and polysilicon of the semiconductor layer. do.

1 is a schematic diagram of a liquid crystal display using general polysilicon.

2 is a cross-sectional view of a thin film transistor of a conventional liquid crystal display using polysilicon.

3A to 3E are cross-sectional views of a manufacturing process of a thin film transistor of a liquid crystal display device using a conventional polysilicon.

Figures 4a to 4c is a view showing the change in the interface shape with the heat treatment time of aluminum and polysilicon during the hydrogenation heat treatment process.

5A to 5B are views showing before and after a hydrogenation heat treatment process of a thin film transistor of a liquid crystal display device using a conventional polysilicon.

6 is a cross-sectional view of a thin film transistor of a liquid crystal display using polysilicon according to an embodiment of the present invention.

7A to 7F are cross-sectional views illustrating a manufacturing process of a thin film transistor of a liquid crystal display using polysilicon according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

100: insulating substrate 105: buffer layer

110 semiconductor layer 125 gate insulating film

130: gate electrode 140: interlayer insulating film

145a and 145b: semiconductor layer contact hole 150: triple structure source electrode

155: triple structure drain electrode 160: protective layer

165 drain electrode contact hole 170 pixel electrode

In order to achieve the above object, a thin film transistor of a liquid crystal display using polysilicon according to an embodiment of the present invention comprises an insulating substrate; A buffer layer on the insulating substrate; A semiconductor layer of polysilicon on the buffer layer; A gate insulating film on the semiconductor layer; A gate electrode on the gate insulating film; An interlayer insulating film having a semiconductor layer contact hole formed over the gate electrode; And a source and drain electrode having a triple structure formed on the interlayer insulating layer and contacting the semiconductor layer through the semiconductor layer contact hole.

In this case, the source and drain electrodes of the triple structure are characterized in that the lower layer is made of a titanium (Ti) layer, the middle layer is an aluminum-neodymium (AlNd) layer and the upper layer is a molybdenum (Mo) layer.

A method of manufacturing a thin film transistor of a liquid crystal display using polysilicon according to an embodiment of the present invention includes forming a buffer layer on an insulating substrate; Forming a semiconductor layer of polysilicon on the buffer layer; Forming a gate insulating film on the semiconductor layer; Forming a gate electrode on the gate insulating film; Forming a ohmic contact layer and an active channel layer on a semiconductor layer by doping the entire surface of the substrate on which the gate electrode is formed; Forming an interlayer insulating film on the substrate on which the ohmic contact layer and the active channel layer are formed; Forming a semiconductor layer contact hole on the interlayer insulating film; Forming a source and drain electrode having a triple structure on the interlayer insulating layer to contact the semiconductor layer through the semiconductor layer contact hole; Performing a hydrogenation heat treatment process on the substrate on which the source and drain electrodes are formed; After the hydrogenation heat treatment process includes forming a protective layer on the entire surface of the substrate on which the source and drain electrodes are formed.

In this case, the forming of the source and drain electrodes of the triple structure may include forming a titanium (Ti) layer by depositing titanium (Ti) on the interlayer insulating layer and performing a mask process; Depositing aluminum-neodymium (AlNd) on the entire surface of the titanium (Ti) layer; Depositing molybdenum (Mo) on the aluminum-neodymium (AlNd); The process of masking the deposited aluminum-neodymium (AlNd) and molybdenum (Mo), and further etched to form an aluminum-neodymium (AlNd) / molybdenum (Mo) layer. In addition, the hydrogenation heat treatment process is carried out at 380 degrees Celsius to 430 degrees Celsius, it is characterized in that for 60 minutes to 180 minutes.

In addition, the titanium (Ti) layer is 250 kPa to 400 kPa, the aluminum-neodymium (AlNd) layer is characterized in that the deposition of a thickness of 2000 kPa to 3500 kPa, the molybdenum (Mo) layer of 300 kPa to 1500 kPa.

Hereinafter, a thin film transistor of a liquid crystal display using polysilicon according to an embodiment of the present invention will be described with reference to the drawings.

The thin film transistor of the liquid crystal display using polysilicon may be largely used as a switching element or divided into n-type or p-type thin film transistors of CMOS. In the embodiment of the present invention, only a cross-sectional view of a thin film transistor as a switching element and a cross-sectional view of a manufacturing process are shown, and differences in the thin film transistors of CMOS will be described without drawings.

6 is a cross-sectional view of a thin film transistor of a liquid crystal display using polysilicon according to the present invention.

As shown, a buffer layer 105 made of an inorganic insulating material, for example, silicon oxide (SiO ₂ ), is formed on the entire surface of the substrate 100 on the insulating substrate 100, and is n-type on the buffer layer 105. A semiconductor layer 110 including three portions of an ohmic contact layer 110c, an LDD layer 110b, and an active channel layer 110a is formed, and a gate insulating layer over the active channel layer 110a of the semiconductor layer 110 is formed. A 125 and a gate electrode 130 are formed, and an interlayer insulating film 140 including semiconductor layer contact holes 145a and 145b is formed on the gate electrode 130, respectively. The source and drain electrodes 150 and 155 having a triple structure are formed to contact the ohmic contact layer 110c among the semiconductor layers through the semiconductor layer contact holes 145a and 145b. . The source and drain electrodes 150 and 155 are formed at the bottom of the titanium (Ti) layers 150a and 155a, the aluminum-neodymium (AlNd) layers 150b and 155b, and the molybdenum (Mo) layers 150c and 155c. They are stacked to form source and drain electrodes 150 and 155 having a triple structure. A passivation layer 160 including a drain electrode contact hole 165 is formed on the drain electrode 155 of the triple structure, and through the drain electrode contact hole 165 on the passivation layer 160. The pixel electrode 170 is formed in connection with the drain electrode 150b.

In more detail with respect to the semiconductor layer 110, the semiconductor layer region under the gate insulating layer 125 corresponding to the gate electrode 130 forms an active channel layer 110a and the source and drain electrodes 150 and 155. ) Is in contact with the semiconductor layer region n ⁺ doped n-type ohmic contact layer (110c), doped with a low concentration n- between the active channel layer (110a) and n-type ohmic contact layer (110c), A lightly doped drain (LDD) layer 110b is formed to prevent hot carrier dispersion and leakage current increase.

Although not shown, a brief description will be given of the p-type semiconductor layer structure of the p-type thin film transistor of CMOS. Since the p-type semiconductor layer uses holes as carriers, the carrier is less affected by deterioration and leakage current than the n-type thin film transistor. Thus, the LDD layer is not formed, and the active channel layer and the p-type ohmic contact layer are formed.

As described above, a method of manufacturing a thin film transistor of a liquid crystal display device using polysilicon according to the present invention will be described.

7A to 7F are cross-sectional views of manufacturing thin film transistors using polysilicon according to an exemplary embodiment of the present invention, respectively.

First, as shown in FIG. 7A, the buffer layer 105 is formed of an inorganic insulating material such as silicon oxide (SiO ₂ ) over the transparent insulating substrate 100. When the amorphous silicon layer is crystallized into a polysilicon layer, the buffer layer 105 may generate alkali ions, such as potassium ions (K +), sodium ions (Na +), and the like, which exist inside the substrate 100 by heat. This is to prevent the film quality of the polysilicon layer from deteriorating due to such alkali ions. Thereafter, amorphous silicon is deposited on the buffer layer 105 over the entire surface, and the amorphous silicon is crystallized using a laser to form a polysilicon layer. Thereafter, a mask process is performed to pattern the polysilicon layer to form the semiconductor layer 110.

Next, as shown in FIG. 7B, silicon oxide (SiO ₂ ) is entirely deposited on the entire surface of the substrate 100 on which the semiconductor layer 110 is formed, and then a metal material such as molybdenum (Mo) is deposited on the silicon oxide ( After the deposition on the SiO ₂ ) film, the masking process is performed, and the patterning is performed, the continuous etching is performed to form the gate insulating film 125 and the gate electrode 130. Subsequently, light doped drain (LDD) doping of n− is performed by ion implantation having a dose of about 1E13 / cm 2 to 5E13 / cm 2 using the gate electrode 130 as a mask. The semiconductor layer 110a corresponding to the gate electrode 130 is not doped by the n-doping, and all of the other semiconductor layers 110b are n-doped.

Next, as shown in FIG. 7C, the photoresist PR is applied onto the n-doped semiconductor layer 110b including the gate electrode 130, and patterned by performing a mask process to pattern the PR pattern 131. ). The PR pattern 131 may be formed to cover a portion of the semiconductor layer 110 including the gate electrode 130 and extended to both sides of the gate electrode 130. Thereafter, n + doping is performed on the entire surface of the substrate 100 on which the PR pattern 131 is formed by high concentration ion implantation having a dose of 1E15 / cm 2 to 9E15cm 2. The n + -doped semiconductor layer by n- and n + doping is blocked by the ohmic contact layer 110c, the n-doped semiconductor layer is blocked by the LDD layer 110b, and the gate electrode 130 so as not to be doped. The semiconductor layer forms an active channel layer 110a.

Although not shown, the semiconductor layer of the p-type thin film transistor of CMOS will be briefly described. The semiconductor layer performs p + doping instead of n + doping. P + doping by ion implantation having a dose of 1E15 / cm 2 to 9E15cm 2 is blocked by the p-type ohmic contact layer and the gate electrode to prevent doping, and the semiconductor layer forms an active channel layer.

Thereafter, the substrate on which the ohmic contact layer 110c and the LDD layer 110b are formed is heated in a furnace 100, or an activation process such as rapid thermal annealing (RTA) is performed in the chamber. This is to re-crystallize the semiconductor layer 110 amorphous by doping and to electrically activate the doped impurities.

Next, as illustrated in FIG. 7D, an inorganic insulating material, for example, silicon oxide (SiO ₂ ), is deposited on the entire surface of the substrate 100 on which the n-type ohmic contact layer 120c is formed to form the interlayer insulating film 140. Form. Subsequently, a mask process is performed on the interlayer insulating layer 140 to form semiconductor layer contact holes 145a and 145b exposing a portion of the ohmic contact layer 110c of the semiconductor layer.

Next, as shown in FIG. 7E, titanium (Ti), which is a metal material, is deposited on the entire surface of the substrate 100 over the interlayer insulating layer 140, and a mask process is performed to form the semiconductor layer contact holes 145a and 145b. Titanium (Ti) on the interlayer insulating layer 140 except for the titanium (Ti) layers 150a and 155a formed on the ohmic contact layer 110c is etched and removed. Subsequently, aluminum-neodymium (AlNd) and molybdenum (Mo) are sequentially deposited on the entire surface of the substrate 100, a mask process is performed, and batch etching is performed to form the source and drain electrodes 150 and 155 having a triple structure. do. The source and drain electrodes 150 and 155 may include titanium (Ti) layers 150a and 155a in contact with the ohmic contact layer 110c and aluminum-neodymium (AlNd) layers on the titanium (Ti) layers 150a and 155a. (150b, 155b), and the aluminum-neodymium (AlNd) layer (150b, 155b) is formed in a triple structure consisting of molybdenum (Mo) layer (150c, 155c), each metal layer formed is a titanium The (Ti) layers 150a and 155a are 250 kPa to 400 kPa, the aluminum-neodymium (AlNd) layers 150b and 155b are 2000 kPa to 3500 kPa, and the molybdenum (Mo) layers 150c and 155c are 300 kPa to 1500 kPa.

Next, as shown in FIG. 7F, a surface insulating material such as silicon nitride (SiNx) is deposited on the substrate 100 on which the source and drain electrodes 150 and 155 having the triple structure are formed, and a mask process is performed. The protective layer 160 having the drain electrode contact hole 165 exposing the drain electrode 155 is formed.

Thereafter, a hydrogenation heat treatment process is performed on the substrate 100 on which the protective layer 160 is formed to improve characteristics of the device. The hydrogenation heat treatment process is performed for 60 minutes to 180 minutes in an atmosphere of 380 degrees Celsius to 430 degrees Celsius, and in this case, aluminum-neodymium (AlNd) and a semiconductor layer having good ductility and conductivity among the metal materials forming the source and drain electrodes 150 and 155. Polysilicon of is diffused by heat. Conventionally, the aluminum-neodymium (AlNd) and polysilicon are in direct contact with each other, thereby deteriorating device characteristics due to interfacial property changes. However, in the present invention, titanium (Ti) layers 150a and 155a which do not diffuse substantially are sourced. And the lower layers of the drain electrodes 150 and 155 to be in contact with the ohmic contact layer 110c of the semiconductor layer, thereby suppressing the deterioration of interfacial properties due to mutual diffusion of aluminum and polysilicon during hydrogenation heat treatment. By forming the titanium (Ti) layer (150a, 155) during the hydrogenation heat treatment process of 380 degrees Celsius to 430 degrees Celsius, aluminum and titanium (Ti), polysilicon and titanium (Ti) before the mutual diffusion of aluminum and polysilicon occurs Reaction occurs, and a TiAl ₃ layer is formed between the aluminum-neodymium (AlNd) layers 150b and 155b of the source and drain electrodes 150 and 155 and the titanium (Ti) layers 150a and 155a. The TiSi ₂ layer is formed between the semiconductor layer 110 and the titanium (Ti) layers 150a and 155a. Since the TiAl ₃ layer and the TiSi ₂ layer formed by the hydrogenation heat treatment process are both conductors, the device characteristics are not degraded.

After the hydrogenation heat treatment process for 60 minutes in an atmosphere of 380 degrees Celsius, the thickness of the titanium (Ti) layer reacting with the polysilicon and aluminum is about 200 kW to 220 kW, and the thickness of the titanium (Ti) deposited in consideration of the reaction thickness. Determine.

The above process is a process of manufacturing a thin film transistor of a liquid crystal display device using polysilicon, and after that, only a thin film transistor which is a switching element belongs to an array substrate manufacturing process, not a thin film transistor manufacturing process. I will mention it for a moment because Indium-Tin-Oxide (ITO) or Indium-Zinc-Oxide (IZO), which is a transparent conductive material, is deposited on the entire surface of the substrate 100 on which the drain contact hole 165 is formed. The mask process is performed to form the pixel electrode 170 in contact with the drain electrode 150b through the drain contact hole 165.

As described above, when fabricating a thin film transistor of a liquid crystal display device using polysilicon according to the present invention, polysilicon of the semiconductor layer and aluminum of the source and drain electrodes are suppressed from interfering with each other during the hydrogenation heat treatment process. In addition, a titanium (Ti) layer was added to the source and drain electrodes underneath to form a triple structure. Hydrogen heat treatment of the triple structure source and drain electrodes having the titanium (Ti) layer formed at the lower portion thereof, before the titanium layer is inter-diffused with polysilicon and aluminum, the titanium (Ti), polysilicon and titanium (Ti) ) And aluminum react to form TiSi ₂ and TiAl ₃ as conductors, thereby reducing device characteristics such as leakage current increase due to mutual diffusion of aluminum and polysilicon. Can provide.

Claims (7)

An insulating substrate; A buffer layer on the insulating substrate; A semiconductor layer of polysilicon on the buffer layer; A gate insulating film on the semiconductor layer; A gate electrode on the gate insulating film; An interlayer insulating film having a semiconductor layer contact hole formed over the gate electrode; A source and drain electrode having a triple structure formed on the interlayer insulating layer and contacting the semiconductor layer through the semiconductor layer contact hole. Thin film transistor of the liquid crystal display device comprising a The method of claim 1, The thin film transistor of the liquid crystal display device, wherein the source and drain electrodes of the triple structure include a titanium (Ti) layer, an intermediate layer of aluminum-neodymium (AlNd), and an upper layer of molybdenum (Mo). Forming a buffer layer on the insulating substrate; Forming a semiconductor layer of polysilicon on the buffer layer; Forming a gate insulating film on the semiconductor layer; Forming a gate electrode on the gate insulating film; Forming a ohmic contact layer and an active channel layer on a semiconductor layer by doping the entire surface of the substrate on which the gate electrode is formed; Forming an interlayer insulating film on the substrate on which the ohmic contact layer and the active channel layer are formed; Forming a semiconductor layer contact hole on the interlayer insulating film; Forming a source and drain electrode having a triple structure on the interlayer insulating layer to contact the semiconductor layer through the semiconductor layer contact hole; Performing a hydrogenation heat treatment process on the substrate on which the source and drain electrodes are formed; Forming a protective layer on the entire surface of the substrate on which the source and drain electrodes are formed after the hydrogenation heat treatment process Method of manufacturing a thin film transistor of the liquid crystal display device comprising a. The method of claim 3, wherein The forming of the source and drain electrodes of the triple structure may include forming a titanium (Ti) layer by depositing titanium (Ti) on the interlayer insulating layer and performing a mask process; Depositing aluminum-neodymium (AlNd) on the entire surface of the titanium (Ti) layer; Depositing molybdenum (Mo) on the aluminum-neodymium (AlNd); Masking the deposited aluminum-neodymium (AlNd) and molybdenum (Mo), and etching them collectively to form an aluminum-neodymium (AlNd) / molybdenum (Mo) / titanium (Ti) layer Method of manufacturing a thin film transistor of the liquid crystal display device comprising a. The method of claim 3, wherein The hydrogenation heat treatment process is a method of manufacturing a thin film transistor of the liquid crystal display device characterized in that proceeds from 380 degrees to 430 degrees Celsius. The method of claim 3, wherein The hydrogenation heat treatment process is performed for 60 to 180 minutes, the method of manufacturing a thin film transistor of the liquid crystal display device. The method of claim 4, wherein The titanium (Ti) layer is 250 Å to 400 Å, the aluminum-neodymium (AlNd) layer is 2000 Å to 3500 Å, and the molybdenum (Mo) layer is deposited to a thickness of 300 두께 to 1500 Å Way.