KR20040059744A - Wire stack type semiconductor package and its structure - Google Patents

Abstract

PURPOSE: A wire-stacked semiconductor package is provided to facilitate a re-work when at least two semiconductor chips are packaged even if a defect occurs in one of chips of the semiconductor package by additionally forming out-wires on the upper and lower surfaces of a package such that the out-wires are vertically connected to a leadframe in each package and the end of the out-wire is of a latch type and by interconnecting the out-wires of different semiconductor packages. CONSTITUTION: A leadframe is vertically connected to the upper and lower surfaces of the semiconductor package to form a plurality of out-wires(220) protruding to the outside of the package wherein the end of the out-wire is of a latch type. A support unit(230) of a predetermined height is formed on the outside of the package having the out-wire.

Description

WIRE STACK TYPE SEMICONDUCTOR PACKAGE AND ITS STRUCTURE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a structure thereof, and more particularly to a wire stack type semiconductor package and a structure of which a rework is easy even when a defect occurs in one chip when at least two or more semiconductor chips are packaged.

At present, all electronic systems using semiconductor chips and the like (for example, computers, PCS, cellular phones, PDAs, etc.) are gradually increasing in functionality and light weight in order to satisfy users' needs. With the development of design and manufacturing process technology, semiconductor chips employed in electronic systems are also becoming highly functional and light and thin.In response to this trend, semiconductor packages are also becoming light and thin. The technology to mount on is widely used.

1 is a view showing a case in which several semiconductor chips are mounted on a single PCB by the prior art alone. Referring to FIG. 1, an example of a conventional semiconductor package may include a first semiconductor chip (Chip1) 12, a second semiconductor chip (Chip2) 14, a third semiconductor chip (Chip3) 16, and the like. It shows what is mounted on the upper surface of one PCB (10). Such a semiconductor package has been difficult to mount many semiconductor chips since the semiconductor chips 12, 14, and 16 occupy a large area on the surface of the PCB 10.

In order to solve this problem, a technique of packaging several semiconductor chips into one has been proposed.

2 is a diagram illustrating a case where a plurality of semiconductor chips are stacked in a single PCB by a conventional technique. Referring to FIG. 2, another example of the conventional semiconductor package is stacking a first semiconductor chip (Chip1) 24 and a second semiconductor chip (Chip2) 26 on a single PCB substrate 20. Attached between these substrates 20 and chips 24 or adhesives 22 to secure them between chips 24 and 26 and the leads (not shown) of each chip 24 and 26 are connected to the substrate 20. An external lead frame (not shown) is connected to the wire 28 to complete the package.

Such a stacked semiconductor package has an advantage of reducing the footprint of the PCB substrate, but there is a problem in that the package cannot be used because a rework of replacing a defective chip is impossible when a defect occurs in one chip.

An object of the present invention is to connect the lead frame of the inside of the package perpendicular to the upper or lower surface of the package in order to solve the problems of the prior art as described above, and to add the end wires of the clasp-shaped end of the different semiconductor package When the at least two semiconductor chips are packaged by connecting the out wires to each other and forming a stack-type package, even if a defect occurs in the chips in any one semiconductor package, a wire stack can be easily reworked to improve product yield. It is to provide a type semiconductor package and its structure.

In order to achieve the above object, a wire stack-type semiconductor package according to the present invention includes a semiconductor chip, and a semiconductor frame connected to a semiconductor chip and a lead frame through a wire, each of which has a lead frame perpendicular to an upper surface or a lower surface of the semiconductor package. And a plurality of out wires protruding out of the package, the ends of which are clasp-shaped.

In order to achieve the above object, the wire stack type semiconductor package structure of the present invention includes at least two semiconductor packages in which a semiconductor chip, a semiconductor chip, and a lead frame are connected through a wire, the lead on the upper or lower surface of the package. The frames are vertically connected to each other to protrude out of the package and to have respective out wires of the lower first semiconductor package connected to each other through the clasps in the first and second semiconductor packages having a plurality of out wires having end caps.

1 is a view showing a case in which several semiconductor chips are mounted on a single PCB by the prior art alone;

2 is a view showing a case in which a plurality of semiconductor chips are mounted in a stack in a single PCB according to the prior art;

3A and 3B illustrate top and vertical cross sections of a wire stack semiconductor package according to the present invention;

4A and 4B are diagrams illustrating a case in which the wire stack semiconductor package according to the present invention is mounted in a stack.

<Description of the code | symbol about the principal part of drawing>

100: upper first semiconductor package

110, 210: support groove

120, 220: out wires

200: the bottom of the second semiconductor package

230: support

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3A and 3B are views illustrating a top surface and a vertical cross section of a wire stack type semiconductor package according to the present invention. Referring to this, the semiconductor package of the present invention has the following structure.

As shown in FIGS. 3A and 3B, there is a semiconductor chip 130 inside the semiconductor package 100, which is connected to the lead frame 134 through a wire 132 and the lead frame 134. The metal layer 140 is connected to the upper or lower surface of the). The package 100 is molded with a resin 114 except for the semiconductor chip 130 and the wire 132 region. In addition, the out wire 120 protrudes out of the package through the via 142 penetrating the mold layer and is connected to the lead frame 134 on the metal layer 140. Although not shown in the drawings, the semiconductor package 100 of the present invention may additionally install an out wire on the bottom surface of the package. In this case, a plurality of vias 112 through which out wires (not shown) are inserted are formed below the metal layer 140 and vertically connected to the lead frame 134.

The end wire 120 of the semiconductor package 100 according to the present invention has a clasp shape, and at least two or more packages may be stacked in a stacked structure when the clasp portions of the out wire 120 cross each other. .

Therefore, in the semiconductor package 100 of the present invention, when the out wire 120 is formed on the upper surface (or lower surface) of the package to stack at least two or more packages in a stacked structure, the package having the out wire 120 is present. It is preferable to include a support 130 of a predetermined height on the outer surface of the. And the package surface should be further provided with a groove (not shown) in which the support 130 is inserted.

If the four semiconductor package 100 is to be mounted in a stacked structure, the support and the insertion groove thereof are inserted into each other so that the out-wire 120 is vertically stacked with another layer semiconductor package even on the surface of the package in which the out-wire 120 is not connected to each other. It must be correct.

4A and 4B are diagrams illustrating a case in which the wire stacked semiconductor package according to the present invention is mounted in a stack. A process of mounting two semiconductor packages in a stacked structure according to an embodiment of the present invention will be described with reference to these drawings.

First, according to the present invention, first and second semiconductor packages 100 and 200 having a plurality of out wires having end caps on the top or bottom surface of a semiconductor package are prepared.

If the first semiconductor package 100 is to be mounted on the PCB substrate in a stacked structure having the second semiconductor package 200 as the lower layer, the plurality of out wires on the upper surface of the first semiconductor package 100 The 120 is aligned with the plurality of out wires 220 on the upper surface of the second semiconductor package 200 so that the end clasps cross each other. Although not shown in the drawing, the semiconductor chip of the first semiconductor package 100 is connected to the semiconductor chip of the second semiconductor package 200 through the out wires 120 and 220.

Then, as shown in FIG. 4B, when the first semiconductor package 100 and the second semiconductor package 200 have a stacked structure stacked vertically in a state facing each other, the PCB is mounted on a PCB substrate (not shown). The area occupied by the stacked semiconductor package on the substrate can be minimized.

In addition, the present invention fits the support 230 of a certain height on the outer surface of the second semiconductor package 200 to the support groove (not shown) in the upper surface of the first semiconductor package 100, these stacked structures Semiconductor packages can be securely fixed. In this case, the support 230 may preferably have a height greater than or equal to that of the first semiconductor package 100 and the out wires 120 and 220 of the second semiconductor package 200. This is because the support 230 determines the vertical space height between the first semiconductor package 100 and the second semiconductor package 200 which are vertically connected to each other through the out wires 120 and 220.

Meanwhile, in the description of the present invention, two semiconductor packages each having vertically connected upper lead and lower leads to an inner lead frame and having end wires having a clasp shape are mounted, but in a stacked structure having three or more stacked according to user requirements. It can also be mounted on a PCB substrate.

As described above, the present invention is a stack type by adding out wires connected to the lead frame inside the package and vertically connected to the upper and lower surfaces of the package, respectively, and having end caps and connecting out wires of different semiconductor packages to each other. By fabricating at least two semiconductor chips by fabricating them as a structured package, even if defects occur in a chip in one semiconductor package, these packages can be easily separated and replaced with other normal packages, thereby improving product yield. It has an effect.

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

Claims (8)

A semiconductor package in which a semiconductor chip, the semiconductor chip and a lead frame are connected through a wire, Wire lead-type semiconductor package structure, characterized in that the lead frame is vertically connected to the upper surface or the lower surface of the semiconductor package, each of which has a plurality of out wires protruding out of the package and the end of the semiconductor package. The wire stack type semiconductor package structure of claim 1, further comprising a support having a predetermined height on an outer surface of the package having the out wire. The wire stack type semiconductor package structure according to claim 1 or 2, further comprising a groove into which a support is inserted into the package surface. In at least two semiconductor packages in which a semiconductor chip, the semiconductor chip and a lead frame are connected through a wire, Each of the lower first semiconductor packages in the first and second semiconductor packages having a plurality of out wires protruding outward from the package and having end caps vertically connected to the upper or lower surfaces of the package, respectively. A wire stack type semiconductor package characterized in that the out wires are connected to each other through the latch. The wire stack type semiconductor package structure of claim 4, further comprising: a support having a predetermined height on an outer surface of the first and second semiconductor packages, the outer wire of which one of the packages is located. 6. The wire stack type semiconductor package of claim 5, wherein the support is greater than or equal to an overall height at which out wires of the first and second semiconductor packages are connected to each other. 6. The wire stack type semiconductor package structure of claim 5, further comprising a groove into which a support is inserted into surfaces of the first and second semiconductor packages. 8. The wire stack type semiconductor package according to claim 5 or 7, wherein the supports of the first and second semiconductor packages and the grooves thereof are aligned and inserted.